KR100207453B1 - Apparatus for on screen displaying put on the edge osd character - Google Patents

Abstract

The present invention discloses an on-screen display device that overlays the OSD text. The apparatus of the present invention comprises: a RAM for storing an attribute value of a box drawing and addressing a ROM under control of a main controller; A ROM for storing data obtained by encoding a font of a character for each horizontal sync signal and a dot clock, and outputting the data in parallel under the control of the main controller; A parallel-to-serial conversion unit which receives data output from the ROM in parallel and converts the data in series in synchronization with the horizontal synchronization signal and the dot clock output from the main control unit; An edge drawing unit for outputting an edge signal by controlling the attribute value of the box drawing and the main control unit output from the RAM; A mixing unit for mixing the video signal, the character signal output from the parallel-serial conversion unit, and the edge signal output from the edge drawing unit; And a main controller for specifying a RAM address, controlling a read / write of a RAM and a read command of a ROM, and controlling overall signal processing and timing of the system. Therefore, according to the present invention, the user can make a desired border on a letter, word, or sentence by covering each letter according to the user's selection, and the OSD text can be seen more clearly.

Description

On-screen display device that overlays OSD text

1 is a block diagram showing the configuration of a conventional on-screen display device.

Figure 2 is a block diagram showing the configuration of an on-screen display device that borders the OSD characters in accordance with the present invention.

3 is a detailed block diagram of the box drawing circuit shown in FIG.

4a to 4d are views showing an embodiment of an on-screen display device that borders the OSD characters in accordance with the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an on-screen display device that overlays an OSD text, and more particularly, to an on-screen display device that can be viewed more clearly by covering an on-screen display text according to a user's selection.

1 is a block diagram showing the configuration of a conventional on-screen display device, which addresses the RAM 4, controls the read / write of the RAM 4 and the read command of the ROM 6, and the overall signal processing of the system. And the main control unit 2 for controlling the timing and timing, the RAM 4 for designating the address of the ROM 6 under the control of the main control unit 2, and the font of the characters. The ROM 6 stores the coded data for each clock Dot_ck and receives the ROM 6 outputting the data in parallel under the control of the main controller 2 and the data output from the ROM 6 in parallel. and a serial-to-serial conversion section 8 for converting serially and outputting a text signal in synchronism with a sync and a dot clock (Dot_ck), and mixing the text signal with a video signal to finally display an OSD signal containing the text in the video signal. A mixing unit 10 for outputting is provided.

The on-screen display device shown in FIG. 1 is usually implemented with an integrated circuit (IC). In general, when the display performance is 'on' in an IC that performs an on-screen display (hereinafter referred to as OSD) function used in a television receiver or a video cassette recorder, the ROM 6 is controlled by the control of the main controller 2. The font of the recorded characters is read, mixed with the video signal by the mixing unit 10, and displayed on the screen. The OSD text displayed on the screen by the conventional method may not be clearly separated from the OSD text by the luminance signal or the chroma signal of the video signal. That is, if the OSD text is white and the brightness signal of the video signal is bright, the OSD text and the video image are not distinguished. Even if the OSD text is black and the chroma signal of the video signal is black, the OSD text and video image are not distinguished. There is a drawback that you cannot see text and images clearly.

In order to solve the problems as described above, an object of the present invention is to create a border for each letter to the border on the OSD characters to make the characters more clearly visible by covering the on-screen display characters by the user's selection An on-screen display device is provided.

In order to achieve the above object, an on-screen display device which includes a border on an OSD character according to the present invention comprises: a RAM for storing an attribute value of a box drawing and specifying an address of a ROM under control of a main control unit; A ROM for storing data obtained by encoding a font of a character for each horizontal sync signal and a dot clock, and outputting the data in parallel under the control of the main controller; A parallel-to-serial conversion unit which receives data output from the ROM in parallel and converts the data in series in synchronization with the horizontal synchronization signal and the dot clock output from the main control unit; An edge drawing unit for outputting an edge signal by controlling the attribute value of the box drawing and the main control unit output from the RAM; A mixing unit for mixing the video signal, the character signal output from the parallel-serial conversion unit, and the edge signal output from the edge drawing unit; And a main control unit for addressing a RAM, controlling a read / write of a RAM and a read command of a ROM, and controlling overall signal processing and timing of the system.

In the on-screen display device to the border on the OSD text, the border drawing unit is a first register to receive the two-bit border attribute values (D15, D14) output from the RAM to latch by a latch clock (Latch_ck), and A first register connected in series to the first register and a latch clock (Latch_ck) and a dot clock (Dot_ck) are inputted, and a first signal outputting a border signal of the first column of pixels forming a letter whenever the address of the RAM is changed. An edge signal generator, a second edge signal generator for receiving the first horizontal synchronization signal a and the dot clock of the start of a letter and outputting a border signal of a first row of pixels forming a letter; An edge control signal generator that gates signals output from the first register, the second register, the first edge signal generator, and the second edge signal generator to generate edge control signals; The shift register 39 preferably outputs the output of the call generator in accordance with the phase of the character output from the parallel-to-serial converter.

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the present invention.

2 is a block diagram showing the configuration of an on-screen display device that overlays the OSD text according to the present invention, which specifies the address of the ROM 24 under the control of the main controller 20 and stores the attribute value of the box drawing. RAM 22, a ROM 24 for storing data obtained by encoding a font of a character for each horizontal sync signal and dot clock, and outputting the data in parallel under the control of the main controller 20, and in the ROM 24. Parallel-to-serial conversion section 26 and RAM 22 for receiving the output data in parallel and converting them in series in synchronization with the horizontal synchronization signal H. sync and the dot clock Dot_ck outputted from the main controller 20. The edge drawing unit 28 for outputting the edge signal under the control of the main controller 20 and the attribute value of the box drawing, and the video signal and the character signal and frame output from the parallel-serial conversion unit 26. Edge output from the drawing part 28 Mixing unit 29 for mixing and outputting signals, assigning addresses of RAM 22, controlling read / write of RAM 22 and read commands of ROM 24, and controlling overall signal processing and timing of the system. The main control part 20 is provided.

FIG. 3 is a detailed block diagram of the box drawing part 28 shown in FIG. 2, and receives the 2-bit edge attribute values D15 and D14 output from the RAM 22 and latches the latches with latch latches. Each time the address of the RAM 22 is changed by receiving the first register 30, the second register 32 connected in series with the first register 30, the latch clock Latch_ck and the dot clock Dot_ck, The first border signal generator 34 outputting the edge signal of the first column of pixels forming the letters, the first horizontal synchronous signal a and the dot clock (Dot_ck) at the beginning of the letters are input to form letters. The second edge signal generator 36 that outputs the edge signal of the first row of pixels, the first register 30, the second register 32, the first edge signal generator 34, and the second edge An edge control signal generator 38 which gates a signal output from the signal generator 36 to generate an edge control signal, and an edge The shift register 39 is configured to output the output of the control signal generator 38 in accordance with the phase of the character output from the parallel-to-serial converter 26.

FIG. 4A is a diagram illustrating a letter composed of 12 dot clocks and 18 horizontal synchronization signals per letter, and FIG. 4B is a diagram illustrating a memory structure of the RAM 22. FIG. 4C illustrates a frame specification corresponding to the attribute values D15 and D14 of the frame stored in the RAM 22. FIG. 4D illustrates a frame box using the frame specification shown in FIG. 4C. Figure shows an embodiment.

Referring to the present invention in more detail by the above-described configuration is as follows.

The ROM 24 shown in FIG. 2 is a memory that stores characters, and one character is stored for each address of the ROM 24. As shown in FIG. In this system, the output (RAM-out) of the RAM 22 becomes the address of the ROM 24, and stores '1' data in a character and '0' data in a blank, thereby storing 216 data in one address. Save to (24). The RAM 22 stores the address values D13 to D0 of the ROM 24 and the attribute bits 2 bits D15 and D14 for the border of the character.

FIG. 4B shows the memory structure of the RAM 22. Assuming that 16 bits are configured for each address, the upper two bits D15 and D14 are edge attribute values, and the lower 14 bits D13 to D0 are ROM 24. ) And other information. In the case of an on-screen display device displaying 360 characters, an attribute value corresponding to the shape shown in FIG. 4C may be stored in the upper two bits of the RAM 22 and then the edge may be displayed according to the user's intention.

That is, (a) of FIG. 4C is a frame specification when the output values box0 and box1 of the first register 30 are '00', and (b) shows the output values box0 and box1 of the first register 30. Is a frame specification when '01', (c) is a frame specification when the output values box0 and box1 of the first register 30 are '10', and (d) is a frame specification of the first register 30. The frame specification when the output values box0 and box1 are '10', and (e) indicates that the output values box0 and box1 of the first register 30 are '00' and the output values P_box0 and the second register 32 are set to '00'. Border specification when P_box1) is '10'.

The main controller 20 controls the operation of the on-screen display device. The main controller 20 is a read / write command of the RAM 22, a read command of the ROM 24, a parallel-to-serial converter 26, and an edge drawing unit 28. Generates an operation timing signal and an enable signal; That is, the main controller 20 controls the RAM 22, and the signal RAM_out output from the RAM 22 is applied to the edge drawing unit 28 and the ROM 24. The edge drawing unit 28 receives the edge attribute values D15 and D14 and outputs the edge signal to the mixing unit 29, and the ROM 24 receives the signal output from the RAM 22 and the main controller 20. It receives the output signal and outputs data in 12 bit units. The parallel-to-serial converter 26 receives the parallel data output from the ROM 24 and converts the serial data into serial data in synchronization with the horizontal synchronization signal and dot clock output from the main controller 20.

The mixing unit 26 receives the edge signal, the parallel-serial converter 26, and the video signal output from the edge drawing unit 28, and outputs a character when the value output from the parallel-serial converter 26 is '1'. When the value output from the edge drawing unit 28 is '1', the edge is output, and in other cases, the video signal is output.

3 is an essential part of the present invention, whenever the address of the RAM 22 is changed, the edge attribute value stored in the RAM 22 is received, and the edge signal is output using the specifications as shown in FIG. 4C. The latch clock Latch_ck shown in FIG. 1 is generated by one clock each time the address is changed, and the latch clocks of the first and second registers 30 and 32 are the same signal.

The first register 30 latches the edge attribute values D15 and D14 output from the RAM 22, and the second register 32 is connected in series with the first register 30 to the first register 30. Latches a value output from the first register 30, and outputs the values box0 and box1 output from the first register 30 and the values P_box0 and P_box1 output from the second register 32 to the edge control signal generator 38. . In addition, the first edge signal generator 34 receives the latch clock and the dot clock and receives the edge signal of the first column of the pixels forming the letters, that is, the edge signal corresponding to (b) of FIG. 4C. A signal hdot0 is generated, and the second edge signal generator 36 receives the horizontal sync signal H. sync and the dot clock Dok_ck, and thus the edge signal of the first row of pixels constituting the letters. A signal (dotline0_1h) corresponding to (c) of FIG. 4c is generated and output to the edge control signal generator 38.

The edge control signal generator 38 gates a signal output from the first register 30, the second register 32, the first edge signal generator 34, and the second edge signal generator 36 to provide an edge control signal. It generates and outputs to the shift register 39, the shift register 39 outputs the output of the edge control signal generator 38 in accordance with the phase of the character output from the parallel-to-serial converter 26.

As described above, the on-screen display device for covering the OSD text according to the present invention can make a desired border on a letter or a word or sentence by covering the on-screen display text according to a user's selection. Therefore, the on-screen display can be diversified and OSD characters can be seen more clearly.

Claims (2)

A ROM for storing predetermined data obtained by coding a font of a character for each horizontal sync signal and a dot clock, and outputting the stored data in parallel; A RAM for storing an attribute value of a border drawing and an address of the ROM for setting a box-shaped frame of display characters according to a user's intention; A main control unit for generating a predetermined control signal for addressing the RAM; A parallel-to-serial converter for inputting data output from the ROM in parallel and converting the parallel data in series in synchronization with a horizontal synchronization signal and a dot clock output from the main controller; A first border signal for covering the first column of one pixel, a second border signal for covering the first row of one pixel, and the first row and the first according to the attribute value of the border drawing output from the RAM A border drawing unit for generating a third edge signal for covering the first column or a fourth border signal for covering only the intersection of the first row and the first column; And mixing the text signal output from the parallel-serial converter and the frame signal output from the edge drawing unit to output an OSD character having a box-shaped frame around one or more characters, and outputting the OSD text and the video signal. An on-screen display device including an OSD character, comprising a mixing unit for mixing and outputting the mixed signal. The memory device of claim 1, wherein the frame drawing unit comprises: a first register configured to latch a frame attribute value output from the RAM by the latch clock; A second register connected in series with the first register to latch an output of the first register; A first edge signal generator configured to receive the latch clock and the dot clock and output a border signal of a first column of pixels forming letters to display; A second edge signal generator which receives a horizontal sync signal H. sync and a dot clock and outputs a border signal of a first row of pixels forming the letter to be displayed; An edge control signal generator configured to logically combine an output of the first register, an output of the second register, an output of the first edge signal generator, and an output of the second edge signal generator to generate an edge control signal; And a shift register configured to output an output of the edge control signal generator according to a phase of a character output from the parallel-to-serial converter.