JPS62267792A - Synchronous control circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a method for synchronously operating a plurality of controlled systems having different operating speeds, such as a character/graphic display device that can display characters and graphics in an overlapping manner. The present invention relates to a synchronous control circuit suitable for.

[Conventional technology]

1 bit of information stored in memory corresponds to 1 pixel,
A graphics screen that displays graphics as a collection of pixels, a character generator that corresponds to a code (for example, a character code specified in JISC6226-1983), and a character generator that converts this code into a collection of pixels that form a character. In a character/graphics display device that displays characters in a superimposed manner on a character screen, a display timing control circuit (hereinafter referred to as CRTC) that controls the display of the graphic screen and a display timing control circuit (hereinafter referred to as CRTC) that controls the display of the character screen are used. By operating the two in synchronization, graphics and characters may be displayed in a superimposed manner.

Since the processing word length of the drawing processor or central processing unit (hereinafter referred to as CPU) that controls the drawing of figures on the figure screen is often configured in units of 8 to 16 pixels, the display control of the figure screen is also performed in units of 8 pixels or 166 pixels. pixel by pixel (this is often done.

On the other hand, in the display control of the character screen, for example, JI
In order to display the 24-bit character shape specified in SC6234-1983, the width of the character must be 24 pixels 1
If the spacing between characters is 4 pixels, 28 full-width characters
8-pixel half-width characters must have 14 pixels as a unit.As a result, two CRTCs are provided, one that controls the graphic screen and the other that controls the character screen, and each of the two CRTCs has a clock with a different frequency. It is necessary to use and drive it.

FIG. 4 is a block diagram showing the general configuration of the display device as described above, in which 1 is a CPU for writing graphics and character codes, and 2 is a CRT for controlling the display of a graphics screen.
C, 3 is a CRTC that controls the display of the character screen, 4 is an excavation circuit that generates a dot clock C corresponding to the display time of one pixel, and 5 is a clock C1l corresponding to the display time corresponding to the width of one character (for example , if the width of one character is 14 pixels, a frequency dividing circuit that generates a clock with a frequency of 1/14 of the dot clock C), 6 corresponds to the display time equivalent to the number of bits in one word of CPU1. 7.8 is a frequency dividing circuit that generates a clock Crn (for example, if one word is 16 bits, a clock with a frequency of 1/16 of the dot clock C), and 7.8 is an address signal generated by the CPU1. 10 is a graphic VRAM for displaying graphics by storing bit information representing the brightness of pixels on the display screen;
1 is a character generator (hereinafter referred to as CG) that generates a pixel group constituting a corresponding character from the character code read from the text VRAM 9 under the control of the CRTC 3; 12 is a graphic V under the control of the CRTC 2;
CG11 for the graphic information read from RAMl0
a delay circuit that delays the time required to read out the data; 13;
°14 is CG11. A parallel-to-serial conversion circuit 15 converts the output of the graphic VRAM 10 from parallel to serial; 15 is an overlapping circuit that switches between pixels representing characters and pixels representing figures output from the parallel-to-serial conversion circuit 13 and 14 to enable overlapping display; A matching control circuit 16 is a display device such as a CRT.

In the same figure, CRTC3 is supplied with horizontal and vertical synchronization signals from the outside, and according to these synchronization signals, text (VR)
A character code is read from AM9.

If the division ratio of the frequency division circuit 5 is n9, and the division ratio of the frequency division circuit 6 is m, then when displaying the aforementioned 24-dot characters, for example, m=16. It is set to n==14. For this reason, CR
There will be a difference between the cycle in which graphic information is read from the graphic VRAM 1o by the TC2 and the cycle in which character codes are read out from the text VRAM 9 by the CRTC3. However, 1 on CRT16
When CRTC2 and CRTC5 are synchronized at the time when screen display starts, that is, when CRTC2) starts displaying one screen, CRTC3 starts displaying one screen at the same time. can be displayed in an overlapping manner.

This will be explained using FIG. 5. 5th '54 (
A) shows the relationship between the n-divided clock supplied from the frequency dividing circuit 5 to the CRTC 3 and the character outputted by the CG 11 from the character code read by the CRTC 3 based on the n-divided clock. Here, one character is displayed in one cycle of the n-divided clock. Further, FIG. 5(b) shows the m-divided clock supplied from the frequency dividing circuit 6 to the CRTC 2, and the CRTC 2 based on this m-divided clock.
shows the relationship with the figure read out from the graphic VRAM 1o. Furthermore, FIG. 5(c) shows the phase relationship between the n-divided clock and the m-divided clock, and the characters (2
) shows how shapes are superimposed.

As shown in FIG. 5(e), if the display start time of characters and the display start time of graphics match, the overlapping display of the characters and graphics is also performed from the display start time.

On the other hand, if there is a shift between the start time of character display and the start time of graphic display, a shift will occur in the superposition of the character display and the graphic display at the start time of superimposed display.

This is shown in FIG. Figure 6(a) shows the case where the character display start time is earlier than the graphic display start time, and Figure N6) shows the case where the character display start time is later than the graphic display start time. In FIG. 4, the timing of display on the CRT 16 is determined by the CRTC 2, which controls the graphic display. Therefore, as shown in FIG. 6(a), if character display starts too early, one character Part of the left side of the eye may not be displayed, and as shown in Figure 6(b), if the start of character display is too late, an unnecessary space may be created to the left of the first character. 1) Since the display period of one screen is constant, when displayed as shown in Figure 6(b), even if the first character is displayed correctly, the last character in one line is displayed to the right of it. Parts will be displayed missing.

In order to solve the above-mentioned problems, it is necessary to synchronize the m-divided clock and the n-divided clock at the time of starting display.

Conventionally, in order to achieve this, m
The frequency dividing circuit 6 that generates the frequency divided clock and the frequency dividing circuit 5 that generates the n frequency divided clock are reset synchronously.

FIG. 7 is a block diagram showing an example of a synchronous control circuit in a conventional display device based on the above idea.
7 is a pulse generation circuit, and parts corresponding to those in Figure @4 are given the same reference numerals. Further, FIG. 8 is a timing chart showing signals of each part in FIG. 7.

The operation of synchronous control in this conventional example will be explained below.

CRTC2 generates a synchronization signal Sy before starting display.

This synchronization signal Sy is provided by the CRTC 3, the pulse generation circuit 17,
and CR1M6 (FIG. 4). With this synchronization signal sy, the CRTC3 starts displaying the next screen,
After a predetermined time, the pulse generating circuit 17 generates a reset signal Rs having a predetermined time width. This reset signal Rs is supplied to the frequency divider circuit 5.6, and the frequency divider circuit 5.6 is reset and performs the division operation of the dot clock C from the oscillation circuit 4 from the initial point in time.

As a result, at the start of display, the m-frequency clock Cm
The phases of the m-frequency clock Cm and the m-frequency clock Cm can be matched.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, the m-divided clock eclipse and the m-divided clock C at the time when the reset signal Rs is generated.
If there is a shift in the phase relationship with m, there is a problem that the division operation is interrupted by the reset signal R3, and as a result, a branch clock with an abnormally short width is generated from the CRTCs 5 and 6, which may lead to malfunction. Ta.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization control circuit that can synchronize two CRTCs while ensuring stable operation of the CRTCs.

[Means for solving problems]

In order to achieve the above object, the present invention provides a specific CRTC
outputs a synchronizing signal, a pulse generating circuit forms a reset signal of a predetermined width, and the reset signal and the output signal of a frequency dividing circuit that supplies a frequency divided clock to CRTCs other than the specific CRT C are connected to a gate circuit. and reset control of the frequency dividing circuit is performed by the output signal of the gate circuit. When reset, the frequency divider circuit is held in a reset state until the reset signal is no longer supplied. Therefore, the output signal of each frequency dividing circuit can be synchronized with the synchronizing signal in a predetermined phase relationship, and short pulses are not output from each frequency dividing circuit.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the synchronous control circuit according to the present invention, in which 18 is a gate circuit, 19 is a reset timing circuit, and parts corresponding to FIGS. 4 and 7 are given the same reference numerals. I'm wearing it. Further, FIG. 2 is a timing chart showing signals of each part in FIG. 1.

In FIG. 1, the synchronization signal Sy output from the CRTC2 is transmitted to the CRT(j), the pulse generation circuit 17, and the CRT16.
(Figure 4). The CRTC 5 starts the display operation of the next screen in response to the synchronization signal Sy, and the pulse generation circuit 17 generates a reset signal R of a constant width in synchronization with the synchronization signal Sy.
generate s. This reset signal Ra is applied to the gate circuit 18
, and the other sword is the frequency dividing circuit 5.
The gate circuit 18 is supplied with the n-divided clock Cn which is the operation clock of the CRT (j), and the gate circuit 18 has the reset signal Rs at the logic level %H/C and the n-divided clock Cn from the frequency divider circuit 5 at the logic level. The frequency divider circuit 5 is caused to perform the reset operation only during the period when the level is 'H'.The frequency divider circuit 5 continues to output the logic level 1H during the reset operation, so after starting the reset operation is in the reset state and holds the output level at the logic level "H" until the reset signal Rs is released. Therefore,
By setting the width of the reset signal R8 to be synchronized with the phase of the m-divided clock Cm output from the frequency divider circuit 6, the n-divided clock Cn output from the frequency divider circuit 5 and the frequency divider circuit 6 It is possible to synchronize the phase with the m-divided clock signal outputted by the m-frequency clock signal.

FIG. 2 shows an example in which the n-divided clock Cn and the m-divided clock fall simultaneously when the reset signal Rs is released. The initial phases of the clock Cn and the m-frequency divided clock Cm can be arbitrarily set. In other words, if the width of the reset signal Rs is increased, the n-divided clock Cn
The phase of the n-divided clock Cn lags behind the m-divided clock Cm, and conversely, if the width of the reset signal R3 is shortened, the phase of the n-divided clock Cn advances with respect to the m-divided clock Cm. By using this, it is also possible to adjust the display positions of characters and graphics on a pixel-by-pixel basis.

In the embodiment shown in FIG. 1 described above, short pulses are not generated at the output of the frequency divider circuit during synchronous operation, so
It is possible to operate the RTC stably. Further, the number of parts involved in this embodiment is small, and it can be implemented at low cost.

FIG. 3 is a block diagram showing another embodiment of the synchronous control circuit according to the present invention, 20 is a pulse width setting circuit that can be changed by the CPU 1, and parts corresponding to those in FIG. is attached.

In FIG. 3, the pulse width setting circuit 20 controls the width of the reset signal R3 generated by the pulse generation circuit 17, and controls the width of the reset signal R3 generated by the pulse generation circuit 17.
The initial phase of the n-divided clock Cn generated by the frequency-dividing circuit 5 is determined relative to the m-divided clock Cn generated by the frequency-dividing circuit 6 when the RTCs 2 and 3 operate synchronously.

In this embodiment, the phase relationship between the n-divided clock Cn and the m-divided clock Cm at the time of display start can be varied by setting the pulse width setting circuit 20, as shown in FIGS. 6(a) and 6(b). It is possible to intentionally generate and adjust the discrepancy between text display and graphic display. CRT
Since C2 controls the graphic display and generates the synchronization signal Sy, the discrepancy between the character display and the graphic display means that the display position of the character is displayed shifted to the left or right relative to the entire display screen. . Since the amount of shift in the display position of characters can be adjusted on a pixel-by-pixel basis, smooth horizontal scrolling can be achieved compared to normal horizontal scrolling on a character-by-character basis.

〔Effect of the invention〕

As explained above, according to the present invention, a plurality of CRTC
When operating synchronously at different frequencies, each CR
The display start position of the TC can be adjusted without causing instability of operation, and the number of required parts increases only slightly, so that it can be implemented at low cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the synchronous control circuit according to the present invention, FIG. 2 is a timing chart showing its operation, and FIG. 3 is a block diagram showing another embodiment of the synchronous control circuit according to the present invention. , FIG. 4 is a block diagram showing a general overlapping display device, FIGS. 5 and 6 are explanatory diagrams showing the relationship between the phase of the CRTC clock and the overlapping display state in FIG. 4, and FIG. 7 is a block diagram showing an example of a conventional synchronous control circuit, and FIG. 8 is a timing chart showing its operation. 2.3... Timing control circuit 4... Oscillation circuit 5.6... Frequency division circuit 17.
...Pulse generation circuit 18...Gate circuit 19...
Reset timing generation circuit 20...Pulse width setting circuit Figure 1 and Figure 2 C ° ° V Figure 3 Figure 6 (b) (b) Table E Start wealth δ diagram (C)

Claims (1)

[Claims] 1. A plurality of frequency dividing circuits having different frequency division ratios and dividing the same reference clock, and each frequency dividing circuit is provided with an output of the frequency dividing circuit as an input clock. Consisting of a plurality of timing control circuits, one specific timing control circuit of the timing control circuits generates a synchronization signal phase-synchronized with the input clock, and the timing control circuits other than the specific timing control circuit is supplied with the synchronization signal, and the timing control circuit causes different controlled systems to operate at mutually different operating speeds according to the input clock and in synchronization with each other, A reset timing circuit is provided for each of the frequency divider circuits that supply clocks to timing control circuits other than the control circuit, and the reset timing circuit forms a reset signal of a predetermined width based on a synchronization signal from the specific timing control circuit. and a gate circuit that receives the reset signal and the output signal of the frequency divider circuit, and starts resetting the frequency divider circuit after the reset signal is generated by the output signal of the gate circuit. A synchronous control circuit characterized in that it is configured to be able to hold the frequency dividing circuit in a reset state from the time to the end of the reset signal.