JPS61193195A - Crt display system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CRT display system, and is particularly directed to a raster scan type CRT display system.

Note that a raster scan type display device is disclosed in, for example, Japanese Patent Laid-Open No. 147026/1983.

The present invention was made in order to provide a pixel data generation circuit that can reduce the memory capacity for generating character patterns 7 in a CRT display device. The present invention has also been made in order to provide a pixel data generation circuit that can easily switch between displaying characters and graphics.

This invention attempts to regularly form pixel data forming interline spaces or intercharacter spaces in character display using predetermined timing pulses. Furthermore, in displaying graphics in addition to character display, the present invention composes complementary bit information of specific digits of the code information of the two, and uses this information to switch the pixel data of the two. This is what we are trying to do.

The present invention will be specifically described below with reference to embodiments. FIG. 1 is a block diagram of a CRT display device showing an embodiment of the present invention.

The outline of the CRT display device in the second embodiment is as follows.

Information to be displayed is written in the input source such as a keyboard or a CPU (microprocessor). This information is.

Generally, ASCII code is used, and the addresses of the fresh memory (2) mentioned above correspond to the addresses of the CRT display screen. Therefore, the refresh memory (2) has a memory capacity capable of storing code information for one screen displayed on a CRT screen.

Reading of this refresh memory (2) is as follows.

This is performed sequentially for each character in synchronization with the raster timing of the CRT. This read code information is converted by the pattern generation circuit (4, 5) into a pattern signal composed of dots for each character.

The pattern generation circuit (4, 5) was composed of a read-only memory (ROM) K that stores pixels such as characters, symbols, or figures □. Therefore, by giving the characters, etc. to be displayed 1 from the refresher memory (2) to the pattern generation circuit (4, 5), that is, by specifying the address of the pattern generation circuit (4, 5), the output is This is a pattern signal such as characters that is synchronized with the raster scan timing.

This pattern output is converted into serial pixel data by a parallel/serial conversion circuit (hereinafter referred to as P/S circuit 5; 6). That is, it is converted into a video signal for each raster.

This video signal is combined with a synchronization pulse (SYNC) by a video control circuit (7) to display characters, etc. on the CRT screen.

The timing controller (8) controls the address timing pulse (MA) of these Nori Freshe memories (2),
Forms the grid clock pulse (CLK), which is the basis of the raster address timing pulse (RA) of the pattern generation circuit (4, 5), and the video clock pulse (VCLK) for obtaining serial pixel data such as character patterns. It is something.

The CRT control circuit (hereinafter referred to as CRTC) specifies various control registers such as a horizontal display character register and a vertical display character register, and the 2 Revcier memory (2), in other words, addresses on the CRT screen. The CR consists of a one-character, one-line counter, a CRT horizontal and vertical synchronization signal generation circuit, a raster control circuit, a cursor control circuit, etc.
The pixel data as described above is formed by synchronizing with the raster of T, addressing (MA) of the fresh memory (2), and raster designation (RA) of the pattern generation circuit (4, 5). and forms a synchronizing pulse for the CRT.

As this CRTC (1), for example, “Product name, HD46
A 505J monolithic semiconductor integrated circuit can be used.

In the CRT display device as described above, the character pattern generation circuit (4) is configured as follows.

For example, as shown in FIG.
), it consists of 32 characters horizontally and 16 characters vertically (line),
The dot configuration of this one-character display screen (11) is 7 dots horizontally and 12 dots vertically (raster), as shown in FIG. The dots used to actually display characters are 5 horizontal dots.

Assume that a dot matrix (27) of 7 vertical dots is used. Spaces are provided on the top, bottom, left and right of the above dot matrix (27) because the displayed characters are close to each other.
This is to prevent this from happening if it is too large.

In this case, only 5 and 7 dots are used to represent one character, but pixel data for space is also required to form a single character display screen (11) on the CRT screen. Therefore, it is necessary to write a dot pattern of 7×12 dots into the pattern generation circuit.

In this embodiment, focusing on the fact that the pixel data forming the space is a regular signal, the space forming between one row is formed by a raster address signal, and the pattern generation circuit (4) is configured. This is an attempt to reduce the number of bits per character in ROM.

That is, as shown in FIG. 3, a 7×8 dot matrix (12
) is written into the ROM, and the pixel data for the lower space is formed from raster address information.

The operation of this pattern generation circuit (4) can be explained as follows.

For example, when displaying the alphabet rAJ on the nth line and the nth character on the display screen, the CR indicating the nth line and the nth character is
The information @41" written in the above address of the 9 fresh memory (2) and indicated by the ASCII code is read out by the row counter output and character counter output of the TC (1). 4) is the code information “41” from this refresh memory (1) and the CRTC (1
) Raster (RAo to RA+t)K synchronized pixel data is output in parallel with the output (RA) of the raster counter in 7 bits. The P/S circuit (6) is for converting this into serial pixel data (video signal). As a result, in FIG. 3, the raster (RAG~
RAu ) and video clock (V CL Ko~V
CLKs) to form a dot matrix on the display screen, and by displaying one dot with diagonal lines as white, for example, the letter rAJ of the alphabet is obtained. If you want to display the alphabet rBJ, use the above code as 4.
2”, rB with dot configuration as shown in the figure
J can be displayed.

In this embodiment, the raster (RAa to RA,,
) is 0”, the address (RA
(1~RA?), and when it is '1'', it is a space (R
A, ~RAII). Therefore, as shown in FIG. 5, this raster address output (A3) causes the input of the gate circuit (G, ) provided at the output of the P/S circuit (6) to become 0 via the gate circuit CG, ). '', pixel data that regularly forms space portions is obtained regardless of the output of the P/8 circuit (6).

In this case, the output (Q) of the Tsuritubu flop (F/F)
is 'l''. This will be explained later.

As mentioned above, the line spacing between one character is the raster address (A, -
If necessary, the first raster (RAo) may also be pixel data formed under the logical conditions of Aa, AI, At, and As.

Also, regarding the character spacing, when inputting to the shift register that constitutes the P/S circuit (6), it is sufficient to always input 0'' for the most significant digit and the least significant digit. As for the pattern generation circuit (4), the number of storage bits for displaying one character is reduced to 5 to 7 bits, resulting in a significant reduction in capacity.

In this embodiment, the pattern generation circuit (5) draws arbitrary figures in addition to the 64 characters and symbols that can be displayed using the ASCII code, for example, when displaying a bar graph as shown in FIG. All or one of the figures required in the case
The pixel data forming the part is formed.

Therefore, as shown in the same figure, this pattern generation circuit needs to draw one figure using the entire display screen, so the line spacing, as in the display of characters, etc.
It is not possible to create spaces between characters. This is because if these spaces exist, a discontinuous graphic pattern will be drawn.

1- Therefore, as shown in Figure 4, when configuring these figures, all 7 x 12 bits (dots) that make up a single character display screen should be used and written in the ROM. . This memory bit will display the intersection (11') of the XY lines in the graph shown in FIG.

If this is addressed and read out in the same manner as described above, and is converted into pixel data synchronized with the raster video clock, a figure as shown in FIG. 3 can be drawn using the dot matrix on the display screen of the CRT described above. can.

In this example, the one-character code is composed of 8 bits, with the most significant digit (A,) set to "ON", and the 7 bits from 0 to 6 digits are ASCII code.On the other hand, the code composing the above figure is is an arbitrary 8-bit code with the most significant digit being 'ml'.

Therefore, the most significant digit (person, ) of the code information read from the refresh memory (2) is 0''.

It is possible to determine whether character display or graphic display is to be performed by l''. In other words, it can be determined whether pixel data should be formed in the pattern generation circuit (4) or pixel data should be formed in the pattern generation circuit (5).

Therefore, as shown in FIG. 5, this information (A?) is used as a chip select signal for the pattern generation circuit (4, 5) to make the above judgment and to form a regular space. [Used as a set input for a clip-flop CF/F) that determines whether

Thus, for example, if the code information is a character code, the code information from the fresh memory (2).

The pattern generation circuit (4) converts it into pixel data, and the output (Q) of the flip-flop (F/F) is 1".
As described above, the regular space pixel data generation circuit as described above is operated. On the other hand, if it is a graphic code, the code information from the refresh memory (2) is converted into pixel data by the pattern generation circuit (5), the output of the clip-flop (F/F) is set to 10'', and the gate circuit ( G, ) control input is 61", P/S circuit (6)
Based on the output of (pixel data, that is, pixel data obtained by serially converting the output of the pattern generation circuit (5)).

According to this embodiment circuit, in addition to simplifying the configuration of one figure code, switching control of one character and one figure becomes extremely simple, and figures and characters are displayed in parallel on the CRT display screen while being spatially divided. This makes it possible to expand the display function of the CRT display device.

The present invention is not limited to the above-mentioned implementation, and the line spacing in character display is such that parallel pixel data that displays the space is forced on the input side of the P/8 circuit (6) by raster information that makes up the space. It is also possible to have the user input the information.

Furthermore, any code information may be used. The one-character code and the graphic code must have complementary bit information in corresponding digits.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a CRT display device showing an embodiment of the present invention, FIG. 2 is a diagram showing a fifth display example of the configuration of a CRT display screen, and FIG. 3 is a diagram showing a character display operation. FIG. 4 is a diagram showing one-figure display operation, and FIG. 5 is a pixel data generation circuit diagram showing one embodiment of the present invention. (1)...CRTC circuit, (2)...refresh memory. (3)...Address selector, (4)...Character pattern generation circuit, (5)...Graphic pattern generation circuit, (
6)...P/S circuit, (power...video control circuit, (8)...timing controller% (9)
...Pass driver, Q (1...Display screen, fit...
・1 character display screen, (8 dots on 12...7, α3・
...7 dots on 5. Fig. 1 A//' Fig. 5 Hardness ≦ Q'-J

Claims (1)

[Claims] 1. Code information corresponding to the information to be displayed and CR
The pixel data generating means receives the raster information of T and forms pixel data constituting the information to be displayed in synchronization with the raster scanning of the CRT, and displays the pixel data on the screen of the CRT according to the formed pixel data. In a CRT display system in which a display is performed, pixel data constituting a space formed between pieces of information displayed adjacently in the vertical direction on a CRT screen is added to the pixel data formed by the pixel data generating means. 1. A CRT display system comprising: means for controlling the display; and a control means for controlling the means.