JPS5837687A - Crt display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CRT display device that displays images on a CRT using a rask scan method, and is capable of modifying and displaying desired characters among the imaged characters. be.

In a device equipped with a CRT, the characters displayed on the screen (in this specification, the concept is used broadly to refer only to characters and include symbols, etc.) or other characters may be displayed in a flashing manner. There may be cases where it is desired to draw the user's attention to that part by displaying it in a different brightness. The operation of blinking certain characters on the screen in this manner is generally called 7 tribits (hereinafter simply referred to as decoration).

The present invention aims to provide a means for modifying characters displayed on a CRT.

FIG. 1 is a diagram showing the principle of displaying characters on a CRT screen. In FIG. 1, reference numeral 1 represents a refresh memory, which stores data for displaying images, and here stores character codes as data. 3 represents a character generator which inputs the character code and outputs a parallel signal for each raster representing a character. Reference numeral 5 represents a parallel-to-serial converter (hereinafter simply referred to as a ps converter), which converts a parallel signal into a serial signal. 7 is a cathode ray display tube (hereinafter simply C
(denoted as RT).

In order to display characters on C11'rliUii11ii, the CRT screen must be constantly scanned and the screen refreshed.
It is necessary to do so. For this reason, a typical CRT display device uses a method in which data is stored in a storage section (not shown) and the screen is refreshed based on this content. In FIG. 1, a character code is written into the flexible memory 1 from CI)U (not shown) via a data bus. Since the character code written by the CPU is usually ASCII code, it cannot be displayed as characters on both sides of the CRT as it is. Therefore, the character generator 3 converts the character code into a character pattern. Since the character generator 3 outputs a parallel signal PD for each raster, the p3 converter 5
The signal is converted into a serial signal V and characters are displayed on the CRT screen.

FIG. 2 is a diagram showing an example of modifying characters displayed on a CRT screen. Both the top line and the bottom line 1 are modified with the letters YEW. The modification on the line -1- indicates inverse display, and the display is performed in black and white with the other characters reversed. The bottom line shows a plink display, in which characters are displayed in alternating black and white. The present invention is not limited to the modification example shown in FIG. 2, but includes characters that are specially displayed so as to be easily distinguished from other displayed characters.

The following two methods can be considered to carry out the modification described above.

(1) Include modification information in the character code in the refresh memory 1.

(3) (ii) At each address in the refresh memory 1, a modification code area is provided and used separately from the character code area.

However, the above-mentioned means have the following drawbacks.

Regarding (1), the MSB is normally used to distinguish between the character code and the modification code, but as a result, the specified times fi+
: The number of characters is 1. The disadvantage is that it decreases to /2.

Regarding (11), it is necessary to access two memory areas simultaneously or to detect the modification prior to display, which has the disadvantage that the display operation becomes complicated.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a means for mixing character codes and modification codes to perform modification without reducing the number of characters that can be specified.

FIG. 3 is a diagram showing an example of the configuration of a CRT display device according to the present invention. In FIG. 3, the constituent elements numbered 1 to 7 are the same as those explained in FIG. 1, and therefore a redundant explanation thereof will be omitted. 2 is a latch that holds (4) the output data CI of the refresh memory 1 over a fixed period and determines the display timing.
Even if this latch 2 is loose, the present invention will still work. 9 represents a converter (hereinafter 111 will be referred to as C1, 3U), which inputs a character code to the refresh memory 1 via the data bus, and refreshes via the address bus.
Specify an address in memory 1 and write the character code 1 into that address.

Also, when reading the contents of refresh memory 1, the CP
Specify the address to be read from U9 via the address bus and read the character code. A decoder 11 inputs the character code stored in the refresh memory 1 according to the read address signal and detects a modification code mixed in this character code. It represents a 13-digit modification signal generation circuit, which introduces the signal AC from the decode 11 and outputs the modification signal AS with a pulse width corresponding to the number of characters to be decorated. A video circuit 15 receives the output signal V of the ps converter 5 and the modification signal As, performs a logical operation, and outputs a signal for driving the CRT 7. 1.7 represents the read L, AT 1/counter, which inputs the clock signal (CHCI) to display the contents of the refresh memory 1 in CR'l'K, and reads the contents of the refresh memory 1 at a constant cycle. outputs a synchronization signal. 19 represents a multiplexer which writes/writes the address signal from C1''U9 and the output of the read address counter 17.
It is switched according to the read timing.

21d represents the skip circuit and inputs it to the decoder 11-"? The read address of the refresh memory 1 is changed by one step in synchronization with the detection of a qualified load.

FIG. 5 shows a time chart of the signals of each part in FIG. 3, and (f) in FIG. The operation of the device shown in Fig. 3 will be described in detail with reference to Fig. 5.The character font is 8x8, and the J character is a 5x7 dot matrix type.

The clock pulse ClIC'l? is applied to the KN output address color/re17. is applied. clock pulse CICP
As shown in FIG. 5(a), the period corresponds to the horizontal traversal time of one character. The address number ma in FIG. 3 is the output fresh memory read address of the read address counter 17, and is the - part of the address of the character generator. Here, we are assuming 8x8 as the character font, so the signal R
A is 5 bits. Signal ITIFL is therefore repeatedly incremented over eight rasters.

A time chart showing this relationship is shown in FIG.

That is, when displaying one character horizontally on a CRT, one clock pulse CTICP is input to form one raster. In this case, read address counter 1
The operation of 7 is the clock pulse CI■CP from 0 to
Until (r-1), zero is output as signal RA,
When counting the Ith shot, the signal becomes nA minus 1. 2 more T
When counting the number of shots, the signal RAil:2 becomes (al
-1) This means that one row of characters in the horizontal direction is displayed by counting the number of views.

The contents of the refresh memory 1 are sequentially read out by the signal MΔ passed through the multiplexer 19 to obtain character code data CD. The contents of the character code data CD are shown in Figure 5 (b) (7). In (b) t. D indicates the output delay time of the refresh memory. In FIG. 5(b), the contents shown in parentheses at the bottom of the waveform indicate the address of the fresh memory 1. In other words, no character code is stored at address n of memory 1, and Y is stored at address (n+1.).
The character code representing the character (n
+2) A character code representing the character E is stored at the address, and a character code representing the character W is stored at the (n + 3) address.
4) The address again shows a state in which no character code is stored. The n address indicated by diagonal lines in this ←) and (n
+4) The code of the address is called a modification code, and the apparatus of the present invention operates to modify the characters in the part sandwiched between these two modification codes.

That is, modification codes must be written in advance under the control of CI'U9 at addresses corresponding to the front and rear of the character or character string to be modified. Note that information on a modification method, such as inverse display or plink display, is written in this modification code instead of the character code. Character codes (including modification codes in this specification) (8) The CDs are sequentially read from the memory 1 and introduced into the character generator 3 and decoder 1 via the latch 2. Note that f→ in FIG. 5 indicates the output CDI of latch 2, but since latch 2 outputs in synchronization with the falling edge of clock pulse c+rcp, the phase is shifted from the waveform in (b). It is.

The decoder 11 decodes the signal CD' (see FIG. 5).
As shown in the figure, the modification code is detected and the output pulse AC is transmitted to the modification signal generation circuit 13 at the next stage. The modification signal generation circuit 13 outputs a modification signal As synchronized with the rise of the clock pulse CIrC1). The modification signal AS is a signal with a pulse width corresponding to 411 times during the modification period, as shown by θ in FIG.

On the other hand, character code data CD' output from latch 2
is applied to the character generator 6 together with the signal RA, and a character dot pattern is output as parallel data PD every horizontal scan. The contents of this parallel data pD are shown in FIG. 5(c). Next, this parallel data P
D is converted into a serial video signal V as shown in FIG. 5(g) by a ps converter 5 using a shift register (not shown).

The video signal V is logically operated with the modified signal As in the video circuit 15, and converted into the modified video signal V.
Sent to nT 7. A specific example of the video circuit 15 is shown in FIG. In Figure 4, 23 is Excl, usJ, ve
Represents an OR circuit, in which case modified characters are displayed in reverse. This modified video signal V is shown in FIG. indicates a raster when RA=φ.

As described above, in the CRT display device according to the present invention, the pair of modification codes operates to modify the characters in the marked portion.

Note that character generator 3 operates to generate a space when a modification code is input, so
As shown in FIG. 5, the screen portion cn''r corresponding to that address is in a blank state with no characters displayed.

In practice, there is no problem even if both ends of a character modified in this way are blank, but especially when displaying by filling in the blank part with characters, the following measures should be taken. Good. That is, as shown in FIG. 3, a skip circuit 21 is provided to shift the read address of the refresh memory 1 by one step in synchronization with the detection of a modification code in the decoder 11. As a result, the contents of the next address in memory 1 are immediately read out and the blank portion is filled with the next character. To explain this relationship with reference to FIG. 5, the skip circuit 21 shifts the read address by one step immediately upon detecting the falling waveform (see FIG. 5). Therefore, the contents of address (n+1) in FIG. 5(g) are read out from the memory 1, so the space shown in FIG. 5(g) disappears.

As described above, according to the present invention, the modification signal is obtained by decoding the character code. Therefore, if there are four types of modification and the character code is 8 bits and 8 bits, there are 256 types of modification signals. By using four types of codes in the character hood as modification specifications, 252 types of υ character codes can be secured. Since there are usually several types of decorations (11), the means according to the present invention allows the number of displayed characters to be reduced to a small number, which is highly effective.

[Brief explanation of drawings]

Figure 1 is a diagram of the principle behind displaying characters on a CRT screen.
FIG. 2 is a diagram showing an example of modifying characters displayed on a CRT screen, FIG. 3 is a diagram showing an example of the configuration of a CRT display device according to the present invention, and FIG. 4 is a diagram showing an example of a video circuit. , FIG. 5 is a time chart of each part of FIG. 3, and FIG. 6 is a diagram showing the operation of the read address counter. 1...Refresh memory, 2...Latch, 3...
・Character generator, 5... pS converter, 7.
...CRT. ? ...C1[)U, 1.1...decoder, 13
...Modification signal generation circuit, 15...Video circuit, 17
. . . Read address counter, 19 . . . Multiplexer, 21 . . . Skip circuit. (12) Figure 2 Exit 11■

Claims (1)

[Claims] (1) A flexible memory that stores a character code at each address, a character generator that inputs the character code and outputs a parallel signal for each raster representing a character, and a ps that converts this parallel signal into a serial signal.
In the device having a function of displaying characters on a CRT screen using a rusk scan method and modifying and displaying desired characters, the characters stored in the refresh memory are The decoder includes a decoder that introduces a code and detects a modification code, a modification signal generation circuit that introduces a signal from the decoder and outputs a modification signal, and a video circuit that performs a logical operation on the serial signal and the modification signal. A CRT display device characterized in that the characters in the sandwiched portion are modified by a pair of modification codes detected by the decoder. CRT display device 0 according to claim 1, further comprising a skip circuit for shifting an address by one step.