JP3461063B2 - Character display device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a character display device suitable for displaying characters that have undergone GB processing.

[0002]

2. Description of the Related Art Generally, when characters are displayed on a television screen or the like, a character ROM in which a dot pattern of a predetermined character font is stored and a video RAM for accessing the address of the character ROM are provided. The video RA
The address of M corresponds to the character display position on the television screen. Now, when displaying RGB-processed characters on the TV screen, specifically, when coloring the characters themselves, adding background color, etc. to the displayed characters, the character code of the character ROM is added to the video RAM. Besides, an attribute code for character modification to the character information read from the character ROM must be stored. A specific storage example will be described below. (Example 1) There is a method of storing a character code and an attribute code together at each address of the video RAM. At this time, the attribute code is information that directly specifies the character color of the displayed character and also information that directly specifies the background color of the displayed character. For example, the attribute code that specifies the character color is 1: 1 for RGB.
3 bits corresponding to, and the attribute code designating the background color also has a 1-to-1 correspondence with RGB and is 3 bits, and the character code is 8 bits.
The bit length of each address of the video RAM is 14 bits. That is, two types of 3 bits, that is, a 6-bit attribute code and an 8-bit character code are stored in each address of the video RAM in a serial 14-bit state. In this case, the character color and background color are each 8
It is possible to specify each type. (Example 2) There is a method of storing the character code and the attribute code together in each address of the video RAM, but the difference from Example 1 is that the attribute code is not the information for directly specifying the character color and the background color. This is that the RGB value of the character color or the background color provided outside is the address value of the external data table in which it is stored. Specifically, the attribute code is set to 4 bits, of which the upper 1 bit is the identification bit of the character color and the background color (the character color if "0", the background color if "1"), and the remaining 3 bits.
Bits are allocated to the addressing bits that select the external data table. Further, if the character code is 8 bits as in Example 1, the bit length of each address in the video RAM is 12 bits. In this case, eight types of character colors and eight types of background colors can be designated. (Example 3) Separately from the above Examples 1 and 2, either the attribute code or the character code is stored in each address of the video RAM without storing the attribute code and the character code in each address of the video RAM together. There is a way to do it. For example, if the character code and the attribute code are each 8 bits, 1 bit is used to identify both codes (when it is “0”, it is identified as the character code, and when it is “1”, it is identified as the attribute code). The bit length of each address is 9 bits. An example of a 9-bit breakdown in which the attribute code is stored is that the most significant bit is the identification bit that is the attribute code, that is, "1", and the remaining 3 bits are the identification bit of the character color and the background color, and the character. It is assigned to an ON / OFF bit for coloring or not, and an ON / OFF bit for coloring or not for background color, and the remaining 3 bits are bits for storing RGB information for directly designating a character color or a background color. Allocated In this case, eight types of character colors and eight background colors can be designated.

[0003]

The problems in the above-mentioned conventional technique will be described below. (Example 1) By accessing the video RAM once,
At the same time as reading the character code, there is an advantage that a character color and a background color that modify the display character corresponding to the character code can be obtained. However, in order to increase the gradation (the degree of color change) of the character color and the background color, it is necessary to increase the number of bits allocated to the attribute code that directly specifies the RGB value, and as a result, the video RAM becomes large. I have a problem to do. (Example 2) The attribute code stores address information designating an external data table. Therefore, when increasing the gradation of the character color and the background color, it suffices to increase the data bit number of the RGB value stored in each address of the external data table, and the bit number of the attribute code is not changed. The bit length of each address in the RAM remains unchanged. However, when increasing the types of character colors and background colors, it is necessary to increase the number of addresses in the external data table. In this case, the number of bits of the attribute code increases as the address information increases, which causes a problem of increasing the size of the video RAM. In particular, the need for the external data table has the problem of increasing the size of the peripheral circuit. (Example 3) Since the attribute code and the character code are stored in different addresses of the video RAM, the bit length of each address can be shorter than in Examples 1 and 2.
As described above, the attribute code can include not only the RGB values that directly specify the character color and the background color but also various kinds of modification information for modifying these characters.
However, in order to increase the gradation of the character color and the background color, it is necessary to increase the bit length for RGB values. As a result, the bit length of each address of the video RAM increases, which causes a problem of increasing the size of the video RAM. On the contrary, if the bit length of each address of the video RAM is fixed, a part of various modification information cannot be added to the attribute code itself, and there is a problem that correct character modification cannot be realized.

The present invention is intended to solve the problem shown in Example 3, and video R even when various types of character modification are performed.
It is an object of the present invention to provide a character display device capable of preventing the AM peripheral circuit from increasing in size and the video RAM itself from increasing in size.

[0005]

The present invention has been made to solve the above problems, and is characterized in that a character code for accessing a character ROM at a predetermined storage address or The character information read from the character ROM includes a video RAM for storing an attribute code for applying a predetermined modification, and the attribute code read from the video RAM and the character information read from the character ROM In a character display device for displaying characters having a predetermined modification based on the above, modification data corresponding to the attribute code is stored in a specific storage area of the video RAM and read from the specific storage area of the video RAM. Modified data and characters read from the character ROM By signal processing and data information, it is that performs character display having been subjected to predetermined modifications.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION The details of the present invention will be specifically described with reference to the drawings. FIG. 1 is a circuit block diagram showing a character display device of the present invention. Note that FIG. 1 is realized by a microcomputer. In FIG. 1, (1) is a video RA
M, the character code corresponding to the display character is stored at the address corresponding to the display portion of the TV screen, and the attribute code indicating the modification information such as the color and the background color of the display character is the head that needs to be modified. The character code corresponding to the display character is stored at the address immediately before the stored address. In particular, in the case where a part or all of the displayed characters are continuously displayed in the same modified state on the television screen, the video RAM (1) immediately before the character code of the first character whose modified state is changed is stored. Only the attribute code is stored in the address of.

In the present embodiment, the video RAM (1)
Each address is composed of 9 bits, the most significant bit MSB is allocated for determining the character code or the attribute code, and the remaining 8 bits are allocated as the content of the character code or the attribute code. For example, if the most significant bit MSB is "0", this means the determination of the character code, and if the most significant bit MSB is "1", this means the determination of the attribute code. , "000
~ 0FF "H (H is hexadecimal) 256 kinds of character codes can be stored in a predetermined address of the video RAM (1), and" 100 to 1FF "H 25
Six types of attribute codes can be stored in the remaining predetermined addresses of the video RAM (1). Then, by reading the stored code from the video RAM (1) and simultaneously detecting the most significant bit MSB of the stored code, it is possible to determine what kind of code the code is.

In the video RAM (1),
The lower storage area separated by a broken line is a storage area (hereinafter referred to as palette data storage area) in which modification data for adding a color or a background color to display characters is stored.
This is an area that is accessed using the attribute code read from AM (1) as address data. That is, the video RAM (1) is configured to store the modification data itself, which is a feature of the present invention, at a specific internal address.

A concrete map example of the video RAM (1) is shown in FIG. The video RAM (1) has a vertical direction of "00-
The intersection position of any one of 17 types of row address data of 10 "H and 48 types of column address data of" 00 to 2F "H in the horizontal direction is one accessed address. Specifically, the row address data “0
0 to 0F "H and column address data" 00 to 08 "
The initial setting data representing the character display start position on the television screen, the modification information for the character to be displayed on the television screen for the first time, and the like are written in the address designated by the right upward slanted line. In addition, the row address data “00-0
Character codes and attribute codes are written in the addresses designated by F "H and column address data" 09-2F "H, corresponding to the character display position on the television screen. Further, an address (pallet data area) which is specified by row address data “10” H and column address data “00-2F” H and which is drawn with a diagonal line rising to the left.
The modification data is written in. More specifically, the modification data representing the character color itself is written in the address designated by the row address data “10” H and the column address data “00-17” H, and the row address data “10” H and the column address are displayed. Data "18-2
It is assumed that the decoration data representing the background color of the character is written in the address designated by "F" H.

Explaining an example of the bit arrangement of the attribute code, the attribute code has a 9-bit structure as described above, and the most significant bit is the identification code of the attribute code and the character code.
The upper 8 bits are for identifying the character color and the background color, the upper 7 bits are for turning on / off the color of the character, and the upper 6 bits are for turning on / off the color of the background. Five bits are allocated to bits that specify the column address "00 to 17" H of the palette data area.

Here, each address of the palette data area has a 9-bit structure as described above, and all 9 bits can be used as information of RGB values. In this embodiment, R
2 bits are assigned to each GB, and 64 types of color can be designated (the remaining 3 bits are not used). Now, one machine cycle of the above-mentioned microcomputer is based on the decoding result of the program, the CPU timing for performing the read / write operation of the video RAM (1), and the CPU
An OSD (ON SCREEN DI) that performs a read operation of the video RAM (1) regardless of the operation of (not shown)
SPLAY) timing. Specifically, one machine cycle consists of 6 states in which CPU timing (low level) for 3 periods and OSD timing (high level) for 3 periods are alternately repeated (O / C in FIG. 2).
reference). Since the video RAM (1) is independently accessed at the CPU timing and the OSD timing, a single port having a simple structure will suffice.

The video RAM (1) has a data bus (2).
Connected with. The video RAM (1) is the CPU
According to the instruction from, the mode is switched to the writing mode of the character code or the attribute code, or the reading mode of both codes. For example, when the video RAM (1) is in the write mode, the address data, the character code, and the attribute code are loaded into the video RAM (1) via the data bus (2). On the other hand, when the video RAM (1) is in the read mode in order to confirm the contents already written in the video RAM (1), the address data is transferred to the data bus (2).
Is taken into the video RAM (1) for addressing via the video RAM (1), the character code or the attribute code is read from the designated address of the video RAM (1) and is superimposed on the data bus (2).

(3) is a row address register, which is used for video RA during the CPU timing of each machine cycle.
The row address of M (1) is addressed by the row address register (3). Row address data is set in the row address register (3) from the CPU via the data bus (2). Similarly,
(4) is a column address register, and the column address of the video RAM (1) is addressed by the column address register (4) during the CPU timing of each machine cycle. Column address data is set in the column address register (4) from the CPU via the data bus (2).

(5) is a vertical position control circuit for detecting the vertical start position of a display character, and the video RAM (1) is addressed by the vertical position control circuit (5) during the OSD timing of each machine cycle. . by the way,
The initial setting data representing the vertical start position of the character first displayed on the TV screen is row address data “00-00”.
0F ”H and column address data“ 00 ”H are written. The vertical position control circuit (5) has a timing switching signal O / C and a horizontal synchronizing signal H.
s and the vertical sync signal Vs are applied to operate, and the vertical position control circuit (5) has a rising edge of the horizontal sync signal Hs as means for detecting the vertical start position of the first display character. The row address is reset from "00" H to "00H" while the column address is fixed to "00" H during the falling period of the horizontal synchronization signal Hs (until the next horizontal synchronization signal Hs is generated). A first counter (not shown) to which a clock signal having a frequency that can be changed to 0F "H is applied, and a second counter (not shown) that is reset by the vertical synchronizing signal Vs and counts the horizontal synchronizing signal Hs. ), The binary data written to any one row address of “00 to 0F” H accessed by the first counter and the horizontal data counted by the second counter. Coincidence detecting circuit for performing coincidence detection of the binary data signal Hs (not shown) is provided. Therefore, the horizontal sync signal H that appears during the current horizontal scan
If the data indicating the position of s is written in any one row address of "00-0F" H, that position is recognized as the vertical display start position of the first display character, and the corresponding row address data Is output and the display is started.

Further, in the vertical position control circuit (5),
A third counter (not shown) is provided which is enabled by a match signal output from the match detection circuit and counts the rising of the horizontal synchronizing signal Hs in binary. Here, the font of characters displayed on the television screen is assumed to be m dots vertically × n dots horizontally. When the coincidence signal is output from the coincidence detection circuit, the third counter in the vertical position control circuit (5) starts counting and is reset by counting the rising edge of the horizontal synchronization signal Hs m times. After that, the above-described operation of detecting the vertical display start position is repeated. Since the character ROM described later has a dot pattern for displaying vertical m dots × horizontal n dots stored in advance, the vertical position control circuit (5) is used after the coincidence is detected by the coincidence detection circuit. , The number of rising edges of the m horizontal synchronizing signals Hs are counted in binary, and are applied to the character ROM so that the address control of the character ROM can be performed.

(6) is "10" for designating the row address of the palette data area of the video RAM (1).
It is a palette row address register in which row address data of H is preset. (7) is a row address switching circuit, which switches and outputs row address data output from the row address register (3), the vertical position control circuit (5), and the palette row address register (6). Specifically, a timing switching signal O / C and a palette read signal PR are applied to the row address switching circuit (7), and both signals O / C and PR are applied.
Any one of the row address data can be switched and output according to the combination of the high level and the low level. Both signals O
The generation timings of / C and PR are as shown in the time chart of FIG. That is, when the timing switching signal O / C is at the low level and the palette read signal PR is at the low level, the row address data set in the row address register (3) is switched and output from the row address switching circuit (7). Applied to video RAM (1),
When the timing switching signal O / C is at a high level and the palette read signal PR is at a low level, row address data generated by the vertical position control circuit (5) in response to horizontal scanning is switched from the row address switching circuit (7). Applied to the video RAM (1), and when the timing switching signal O / C and the palette read signal PR are both high level, the row address data set in the palette row address register (6) is switched to the low address. It is applied to the video RAM (1) via the circuit (7).

(8) is a horizontal position control circuit for detecting the horizontal start position of the displayed character. During the OSD timing of each machine cycle, the video RAM (1) outputs the horizontal position control circuit (8). Addressing based on
Inside the horizontal position control circuit (8), a horizontal synchronization signal Hs
Dot clock DC after being reset at the rising edge of
A counter function that counts the rising edge of LK in binary,
Also, it has a register function in which the number of dot clocks DCLK when the dot clocks DCLK are performed up to the horizontal start position of the display character is set in advance in binary. The dot clock DCLK has a frequency such that each horizontal dot of the character data has one cycle. The counter function in the horizontal position control circuit (8) is prohibited from counting until the actual dot clock DCLK reaches the value set in the register function.
After that, the pulse PPC is generated at the same time when the counting is started, and thereafter, the pulse PPC is repeatedly generated every time the dot clock DCLK is counted n times. A column counter (9) generates column address data that is incremented each time the pulse PPC from the horizontal position control circuit (8) is applied via the OR gate (10). As is clear from the above description, the pulse PPC is generated when the horizontal character display is changed.

A column address switching circuit (11) is applied with the timing switching signal O / C and the palette read signal PR in the same manner as the row address switching circuit (7), and has a level of both signals O / C and PR. Accordingly, the outputs of the column address register (4), the column counter (9) and a latch circuit described later are switched and output to output the video RAM.
It is applied to (1). Specifically, when both the timing switching signal O / C and the palette read signal PR are at the low level, the column address data set in the column address register (4) passes through the column address switching circuit (11) to the video RAM ( 1) is applied. When the timing switching signal O / C is at high level and the palette read signal PR is at low level, the column address data counted by the column counter (9) is transferred to the video RAM (1) via the column address switching circuit (11). Applied to. Further, when both the timing switching signal O / C and the palette read signal PR are at high level, the latch output of the latch circuit is applied to the video RAM (1) via the column address switching circuit (11). In this way
The video RAM (1) can access the address specified by the row address data and the column address data and read the data (character code or attribute code) written at the address. In the vertical position control circuit (5), in order to detect the vertical character display start position, the row address "00-0
It is necessary to fetch the data written at the address designated by F "H and the column address" 00 "H. Therefore, all the 9-bit data VDAT of the video RAM (1) read at the falling edge of the timing switching signal O / C.
A is applied to the vertical position control circuit (5).

Reference numeral (12) is an 8-bit character code latch circuit, and only the character code of the read output VDATA of the video RAM (1) is pulsed PP.
It is latched in synchronization with the rising edge of C. (1
Reference numeral 3) is an attribute code latch circuit, and when the most significant bit MSB of the read output of the video RAM (1) becomes logic "1" and the horizontal position control circuit (8) generates the attribute clock ATRCK, the AND gate (14 ), Only the attribute code of the read output VDATA of the video RAM (1) is latched in synchronization with the fall of the same output as the above-mentioned ATRCK. At the same time, the output of the AND gate (14) is also applied to the other input of the OR gate (10), that is, the value of the column counter (9) immediately before the attribute code latch circuit (13) latches the attribute code. It is incremented by +1 in synchronization with the rising edge of the clock ATRCK.

(15) is the above-mentioned latch circuit, which decodes the attribute code latched by the attribute code latch circuit (13) into the column address of the palette data area and latches it in synchronization with the rising edge of the pulse PPC. Is. As a result, the latch circuit (1
5) is data for identifying a character color or a background color (upper 8 bits of the attribute code), character color on / off data (upper 7 bits of the attribute code),
On-off data of the background color (upper 6 bits of the attribute code) and column address data of the palette area are held.

(16) is a modified data latch circuit,
Video RAM designated by fixed row address data of "10" H output from the palette row address register (6) and column address data of "00-2F" H output from the latch circuit (15) ( The modification data read from an arbitrary address in the palette data area 1) is latched in synchronization with the rising edge of the modification data clock PLDCK output from the horizontal position control circuit (8).

(17) is the above-mentioned character ROM, and a predetermined dot pattern having a character font of vertical m dots × horizontal n dots is stored at each address.
(18) is an n-bit shift register, which has a pulse P
Character ROM (17) in synchronization with the rise of PC
It holds the n-bit data read from, and serially outputs the n-bit data in synchronization with the dot clock DCLK.

(19) and (20) are registers A and B, respectively.
When the data latched by the modification data latch circuit (16) is modification data for designating the color of the display character itself, the register A (19) holds the data in synchronization with the rising edge of the pulse PPC. Similarly, the register B (20) holds, in the case of the modification data for adding a background color to the display character, the data in synchronization with the rising edge of the pulse PPC. (21) is the register A (1
9) and the register B (20) is a selection latch circuit for selectively inputting the data of the modified data latch circuit (16) to either one of the registers B (20) and the falling edge of the pulse PPC applied via the inverter (22). In synchronization with this, the data of the character color designation or the background color latched in the latch circuit (15) is latched. For example, the selection latch circuit (2
1) permits input to the register A (19) when "0" is latched, and permits input to the register B (20) when "1" is latched. Reference numeral (23) is an output processing circuit, and based on the output from the color output control latch circuit (24), the dot data output from the shift register (18) and the register A (19) or the register B (2
(0) is subjected to signal processing with respect to the modified data outputted from (0) to output a signal for displaying the characters subjected to the RGB signal processing on the television screen.

The color output control latch circuit (24) latches the character color on / off data and the background color on / off data latched by the latch circuit (15) in synchronization with the rising of the pulse PPC. . By outputting this latch output to the output processing circuit (23), it is possible to control on / off of the character color and the background color. Hereinafter, the operation of FIG. 1, particularly the case where the memory code of the video RAM (1) is read out for the purpose of display and displayed for one horizontal scanning on the television screen (row address is fixed), FIG.
It will be described based on the time chart of. 2 shows the operation after the initial start position of the displayed character can be recognized. Further, it is not necessary to synchronize the timing switching signal O / C and the pulse PPC, but for convenience of explanation, they will be described in a synchronized state.

At time t0, when the pulse PPC rises, the column counter (9) is incremented in synchronization with the rising of the pulse PPC, and the value of the column counter (9) changes from n-1 to n. To do. at the same time,
The character code N-1 corresponding to the column address data n-1 is read from the video RAM (1).
Then, the character code N-1 is latched in the character code latch circuit (12) in synchronization with the rising edge of the pulse PPC. At this time, the timing switching signal O / C is in a state of rising from the low level to the high level, and during the subsequent high level period, the column address data n of the column counter (9) is transferred to the video via the column address switching circuit (11). Applied to RAM (1),
The address specified by the column address n (the row address is fixed at an arbitrary address) of the video RAM (1) is accessed. Then, the code read from the video RAM (1) is changed from N-1 to N in synchronization with the fall of the timing switching signal O / C.
The read code of the video RAM (1) corresponding to the column address n is represented by capital N. Here, when the read code N is an attribute code, the most significant bit MSB is "1", so that the value of the column counter (9) is changed from n to n + 1 in synchronization with the rising edge of the attribute clock ATRCK. The attribute code N is latched in the attribute code latch circuit (13) in synchronization with the fall of the attribute clock ATRCK. still,
Since the palette read signal PR is at a high level while the attribute clock ATRCK is generated, the operation in which the output of the column counter (9) is output from the column address switching circuit (11) is prohibited, and instead, The previous attribute code already latched in the latch circuit (15) is applied to the video RAM (1), and in synchronization with the fall of the timing switching signal O / C, the previous attribute code is changed from the video RAM (1) to the previous attribute code. The corresponding modification data is read. After that, when the modified data clock PLDCK is generated at the same time when the timing switching signal O / C rises, the modified data clock PL
The modification data is latched in the modification data latch circuit (16) in synchronization with the rise of DCK. The code read from the address designated by the value n + 1 of the column counter (9) is assumed to be a character code.

After that, the horizontal dot display of the character font for one character is completed, and the pulse PPC is displayed at time t1.
Rise again, the column counter (9) is incremented in synchronization with the rising of the pulse PPC, and the value of the column counter (9) changes from n + 1 to n + 2.
At the same time, the character code N + 1 corresponding to the column address data n + 1 is read from the video RAM (1), and the character code N + 1 is latched by the character code latch circuit (12) in synchronization with the rising edge of the pulse PPC. It Further, in synchronization with the rising edge of the pulse PPC, the attribute code latch circuit (1
The character ROM (17) in which the attribute code N already latched in 3) is latched in the latch circuit (15) and is accessed with the character code N-1.
The output (N-1) 'read from is set in the shift register (18), and the character color or background color already latched in the latch circuit (15) is designated in synchronization with the fall of the pulse PPC. The pre-qualification data latched by the decoration data latch circuit (16) is registered in the register A (19) or the register B (2
0). At this time, the timing switching signal O / C is in a state of rising from the low level to the high level, and during the subsequent high level period, the column address data n + 2 of the column counter (9) is transferred to the video through the column address switching circuit (11). The column address n + 2 of the video RAM (1) applied to the RAM (1).
The address specified by (row address is fixed at any address) is accessed. Then, the video R is synchronized with the fall of the timing switching signal O / C.
Codes read from AM (1) are N + 1 to N + 2
Is changed to. Here, if the read code N + 2 is a character code, the most significant bit MSB of the character code is "0", so that the value of the column counter (9) is changed even if the attribute clock ATRCK is generated. N + 2 without any change, and A
Since the clock for the attribute code latch circuit (13) is not generated from the ND gate (14), the character code N + 2 is the attribute code latch circuit (1).
The operation latched in 3) is also prohibited. Since the palette read signal PR is at the high level during the period when the attribute clock ATRCK is generated, the output of the column counter (9) is the column address switching circuit (11).
Is prohibited, and instead the attribute code N already latched in the latch circuit (15) is applied to the video RAM (1), in synchronization with the fall of the timing switching signal O / C, Video ram
From (1), the modified data N corresponding to the attribute code N is read. Then, at the same time as the timing switching signal O / C rises, the modified data clock PL
When DCK occurs, the modified data clock PLDCK
Modified data latch circuit (16) in synchronization with the rising edge of
The modification data N is latched at.

After that, the dot display in the horizontal direction of the character font for one character is completed, and at time t2, the pulse P
When PC rises again, the column counter (9) is incremented in synchronization with the rise of the pulse PPC, and the value of the column counter (9) changes from n + 2 to n + 3. At the same time, the character code N + 2 corresponding to the column address data n + 2 is read from the video RAM (1), and the character code N + 2 is latched by the character code latch circuit (12) in synchronization with the rising edge of the pulse PPC. It Further, in synchronization with the rising edge of the pulse PPC, the attribute code N already latched in the attribute code latch circuit (13) is latched again in the latch circuit (15) and is accessed by the character code N + 1.
The output (N + 1) 'read from M (17) is set in the shift register (18), and the character color or background color already latched in the latch circuit (15) is synchronized with the fall of the pulse PPC. The modification data N latched in the modification data latch circuit (16) is registered in the register A (19) or the register B (2
0). At this time, the timing switching signal O / C is in a state of rising from the low level to the high level, and during the subsequent high level period, the column address data n + 3 of the column counter (9) is transferred to the video through the column address switching circuit (11). The column address n + 3 of the video RAM (1) applied to the RAM (1).
The address specified by (row address is fixed at any address) is accessed. Then, the video R is synchronized with the fall of the timing switching signal O / C.
Codes read from AM (1) are N + 2 to N + 3
Is changed to. Here, if the read code N + 3 is an attribute code, the most significant bit MSB of the attribute code is "1". Is incremented by +1. Also, the attribute clock ATRC
Attribute code N + 3 in synchronization with the fall of K
Is latched by the attribute code latch circuit (13). Since the palette read signal PR is at a high level while the attribute clock ATRCK is generated, the operation of outputting the output of the column counter (9) from the column address switching circuit (11) is prohibited,
Instead, the attribute code N already latched in the latch circuit (15) is re-applied to the video RAM (1), and from the video RAM (1) in synchronization with the fall of the timing switching signal O / C. The modification data N corresponding to the attribute code N is read. After that, when the modified data clock PLDCK is generated at the same time as the rising of the timing switching signal O / C, the modified data N is latched in the modified data latch circuit (16) in synchronization with the rising of the modified data clock PLDCK. After that, the above operation is repeated.

Then, between the times t1 and t2,
When the value of the shift register (18) is (N-1) 'and the value of the register A (19) or the register B (20) is the prequalification data, these values are applied to the output processing circuit (23). Then, a predetermined RGB signal is output.
Similarly, when the value of the shift register (18) is (N + 1) 'and the value of the register A (19) or the register B (20) is the modified data N between the times t2 and t3, Is applied to the output processing circuit (23) to output a predetermined RGB signal.

As described above, according to the present invention, the video RAM
The modification data for modifying the display characters, which corresponds to the attribute code read from (1), is converted into the video R
The video RA is stored in a specific address of AM (1) itself.
Only when the attribute code is read from M (1), the corresponding modification data can be read. As a result, since the modification data is stored in a part of the address of the video RAM (1), it is possible to prevent the peripheral circuit from increasing, and
Since only the attribute code can be stored for each address, various types of colors can be specified.

The above-described embodiment is merely an example of the present invention, and various modifications can be made if necessary, and the present invention described in the claims includes all those modifications. It is a thing.

[0031]

According to the present invention, modification data for modifying display characters corresponding to the attribute code read from the video RAM is stored at a specific address of the video RAM itself, and the attribute code is read from the video RAM. Only when read, the corresponding modified data can be read. As a result, the modification data is stored in a part of the address of the video RAM, the increase of the peripheral circuit can be prevented, and since only the attribute code can be stored in one address, it is possible to specify many kinds of colors. To be

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a character display device of the present invention.

FIG. 2 is a time chart showing the operation of FIG.

FIG. 3 is a diagram showing an area map of a video RAM.

[Explanation of symbols]

(1) Video RAM (17) Character ROM (23) Output processing circuit

─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-5-303361 (JP, A) JP-A-62-123492 (JP, A) JP-A-62-170998 (JP, A) JP-A-62- 172389 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G09G 5/00-5/40 H04N 5/445

Claims (2)

(57) [Claims] 1. A video RAM for storing a character code for accessing a character ROM and an attribute code for applying a predetermined modification to character information read from the character ROM, the video RAM being read from the video RAM. In the character display device for displaying a character having a predetermined modification based on the attribute code and the character information read from the character ROM, the character code and the attribute code are
When stored at different addresses in the video RAM
Moni, Ath modified data corresponding to the attribute code
The review code is accessed as address data
That said to be stored in a specific storage area of the video RAM, and that the signal processing and character information read specific and modified data read from the storage area from the character ROM of the video RAM, and predetermined modification A character display device characterized by performing applied character display. 2. The specific storage area of the video RAM is
The character display device according to claim 1, wherein the character display device is a storage area in which a row address is fixed to a certain one address.