JP3789537B2 - Character area access control circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention controls a character area access control circuit for controlling access to a character area for storing a character, in particular, to access only a specific range of the character area in order to display a character such as a character on a television screen or the like. About things.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, there is known a television apparatus that can display RGB-processed color characters on a television screen according to predetermined code data. Note that the code data may be reproduced from the received signal or may be generated internally.
[0003]
When displaying characters in such an apparatus, a character ROM storing a dot pattern (character pattern) of a predetermined character font and a video RAM storing a character code for determining an access address of the character ROM are provided. The video RAM address corresponds to the character display position on the television screen. Therefore, character display can be performed by reading the corresponding character pattern from the character ROM in accordance with the character code stored at each address of the video RAM.
[0004]
Here, the character code stored in the video RAM is always a fixed number of bits, and the area in the character ROM addressed by this character code, that is, the area where one character is stored is always set to a fixed size. Yes. On the other hand, as a character displayed on the screen, there are cases where it is desired to display a large or small character, not always a fixed size. However, as described above, the area for storing the character has a fixed size, and only the fixed size is read and used for display.
[0005]
[Problems to be solved by the invention]
Thus, in the conventional character ROM, even a small character is stored in a large area that can accommodate a large character. Therefore, when a small character is accommodated, there is an area that is not actually used. Therefore, there is a demand for accommodating a plurality of characters in one area from the viewpoint of effective use of ROM.
[0006]
However, the area specified by the character code is an area for one character and cannot be divided. Therefore, a plurality of accommodated characters are read together. Therefore, in the end, a small character is also stored in the area for one character, and there is a problem that the utilization efficiency of the ROM is deteriorated.
[0007]
The present invention has been made to solve the above problems, and an object of the present invention is to provide a character area access control circuit that can divide and read an area for one character.
[0008]
[Means for Solving the Problems]
The present invention provides access to a character storage area in which an area for one character is designated in accordance with a character code read from a video RAM in which character codes are stored in a matrix at positions corresponding to display on the screen. Character area access control circuit to control, an area for one character Inside A vertical reading start position is preset, a counting unit that counts horizontal lines and sequentially increments the reading position, and one character Within minutes And a coincidence detection unit for detecting coincidence between the count value of the counting unit and the value of the storage unit, and a leading portion of the character code row of the video RAM The head reading position and the end reading position are stored, and the head reading position and the end reading position read from the video RAM prior to the character code reading are set in the counting unit and the storage unit, respectively. For the corresponding row character, only a range corresponding to a predetermined number of horizontal scanning lines in the character storage area is read.
[0014]
When the character code is read from the video RAM and the character is displayed according to the character code, the read range can be specified. For this reason, an arbitrary portion in the vertical direction can be read out from the area for one character. Therefore, by storing a plurality of characters vertically in an area for one character in a character storage area (for example, a character ROM), these can be read out separately, and the character storage area can be used effectively.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments (hereinafter referred to as embodiments) of the invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of the character display control circuit, which is realized by a microcomputer.
[0016]
The video RAM 1 stores the character code corresponding to the display character at the address corresponding to the display portion of the television screen. Further, when storing the modification (attribute) information indicating the character color and the background color, an attribute code designating them is stored instead of the character code. Once this attribute is specified, the same state is maintained thereafter. Therefore, the attribute code is stored at the address immediately before the address of the character whose attribute is to be changed. Therefore, when the display character is continuously displayed with the same attribute on the television screen, it is only necessary to store the attribute code at the address immediately before the address where the first character code is stored.
[0017]
In this embodiment, each address of the video RAM 1 is composed of 9 bits. The most significant bit (MSB) indicates an identification bit indicating whether a character code or an attribute code, and the remaining 8 bits indicate a character code (character code) or an attribute code. MSB “0” indicates a character code, and MSB “1” indicates an attribute code. By reading and determining the MSB, it is possible to identify the character code or the attribute code. The remaining 8 bits, that is, “000” to “0FF” H (H is hexadecimal) indicate the contents of 256 types of character codes or attribute codes.
[0018]
Further, as shown by being divided by broken lines in the figure, a palette data area is provided in the video RAM 1. In the palette data area, modification data for adding a color or background color to the display character is stored. That is, using the attribute code read from the video RAM 1 as address data, the palette data area is accessed, and the character color and background color of the display character are determined.
[0019]
"Configuration of video RAM"
Here, a map configuration example of the video RAM 1 is shown in FIG. Thus, the video RAM 1 is composed of 17 row addresses whose vertical direction is “00 to 10” H and 48 column addresses whose horizontal direction is “00 to 2F” H. In the area indicated by the upward slanting lines designated by the row address “00-0F” H and the column address “00-08” H, the character display start position on the television screen and the first display on the television screen are displayed. Initial setting data indicating attributes (character color and background color) of the character to be performed is written.
[0020]
In particular, the column address “00” of the initial setting data stores data indicating the display start position of the row character (horizontal scanning line number indicating the vertical position on the screen). The column address “01” H includes data “M” indicating the display start position within one character, the column address “02” H includes data “N” indicating the display end position within one character, and the column address “04”. "H" stores data indicating the display start position of the first character in one horizontal line (the number of dot clocks DCLK from the rise of the horizontal synchronization signal Hs to the start of character display).
[0021]
In the area specified by the row address “00-0F” H and the column address “09-2F” H, a character code (or attribute code) is written corresponding to the character display position on the television screen.
[0022]
Further, the above-described modification data is written in an area (pallet data area) indicated by a left-upward oblique line designated by the row address “10” H and the column address “00 to 1F” H. More specifically, in the area specified by the row address “10” H and the column address “00-17”, the modification data indicating the character color is written, and the row address “10” H and the column address “18” are written. ˜2F ”H is written in the area designated by the decoration data indicating the background color.
[0023]
Here, an example of the bit arrangement of the attribute code will be described. The attribute code has a 9-bit configuration, the MSB is the identification code of the attribute code and the character code, the upper 8th bit is the identification bit of the character color and the background color, An on / off bit indicating whether or not the upper 7 bits are for coloring a character color, an on / off bit indicating whether or not the upper 6 bits are for coloring a background color, and the remaining 5 bits are column addresses “00 to 17” of the palette data area Allocated to a bit that designates one of H or "18-2F".
[0024]
Each address of the palette data area has a 9-bit configuration, and all 9 bits can be used as RGB information. In this embodiment, 2 bits are assigned to each of RGB, and 64 types of colors can be designated (the remaining 3 bits are not used).
[0025]
"Access to video RAM by CPU timing"
Here, one machine cycle of the microcomputer is based on the decoding result of the program, the CPU timing for performing the writing / reading operation of the video RAM 1 and the OSD (reading of the video RAM 1 irrespective of the operation of the CPU (not shown)). ON SCREEN DISPLAY) timing. Specifically, one machine cycle consists of six states that alternately repeat CPU timing (low level) for three periods and OSD timing (high level) for three periods (see O / C in FIG. 8). Since the video RAM 1 is independently accessed at the CPU timing and the OSD timing, it is configured by a single port with a simple configuration.
[0026]
As shown in FIG. 1, the video RAM 1 is connected to the data bus 2. The video RAM 1 is switched to a writing mode or a reading mode according to an instruction from the CPU. For example, when the video RAM 1 is in the write mode, a character code, an attribute code, and decoration data are written into the video RAM 1. In the read mode, the character code and attribute code are read and placed on the data bus 2. The addressing of the video RAM 1 at the time of writing and reading is performed by setting desired address data in a row address register 3 and a column address register 4 described later via the data bus 2.
[0027]
That is, when addressing the row address of the video RAM 1 during the CPU timing in each machine cycle, the row address data from the CPU is set in the row address register 3 via the data bus 2.
[0028]
Similarly, column address data from the CPU is set in the column address register 4 via the data bus 2. As a result, the video RAM 1 is addressed.
[0029]
Data writing to the video RAM 1 is performed by data from the CPU at this CPU timing. Further, data is read from the video RAM 1 for screen display by reading OSD timing.
[0030]
"Access to video RAM at OSD timing"
A vertical position control circuit 5 is provided to determine the row address during the OSD timing of each machine cycle.
[0031]
Here, initial setting data indicating the vertical start position of character display on the television screen is written in the areas specified by the row address “00-0F” H and the column address “00”, respectively.
[0032]
The vertical position control circuit 5 operates by applying the timing switching signal O / C, the horizontal synchronization signal Hs, and the vertical synchronization signal Vs. Therefore, the vertical position control circuit 5 has a first counter (not shown) and a second counter (not shown) as a means for detecting the vertical start position of the first display character. A detection circuit (not shown) is provided.
[0033]
The first counter is reset at the rising edge of the horizontal synchronizing signal Hs, and changes the row address from “00” H to “0F” H during the rising edge of Hs of the horizontal synchronizing signal (blanking period). For this reason, the clock signal of the frequency corresponding to this is counted. At this time, the column address is fixed to “00”, and in this state, the vertical position control circuit 5 sequentially reads binary data from the video RAM 1 according to the value of the first counter.
[0034]
The second counter is reset by the vertical synchronization signal Vs and counts the horizontal synchronization signal Hs. The coincidence detection circuit counts binary data written to any one row address (column address is “00”) of “00 to 0F” H accessed by the count value of the first counter and the second counter. The coincidence with the binary data of the horizontal synchronizing signal Hs is detected. Therefore, when data representing the vertical position of the horizontal synchronization signal Hs obtained by the second counter is written in any one of the row addresses “00 to 0F” H, that position is the first display character. This is recognized as the vertical display start position. Therefore, the coincidence detection circuit outputs a coincidence signal (ROWSTART) at this time. In response to this coincidence detection, the data of the corresponding row address is output and the character display is started.
[0035]
The vertical position control circuit 5 has a configuration for recognizing the position of one character currently displayed in the vertical direction in order to control reading of the character ROM 17. That is, it is enabled by the coincidence detection signal (ROWSTART) output from the coincidence detection circuit, and the rising edge of the horizontal synchronization signal Hs is counted in binary to generate the read address of the character ROM 17. This will be described later.
[0036]
A palette row address register 6 is provided for designating the row address of the palette data area in the video RAM 1. In this example, “10” H is preset in the palette row address register 6.
[0037]
A row address switching circuit 7 is provided between the row address register 3, the vertical position control circuit 5, the palette row address register 6 and the video RAM 1 to switch and output any of the row addresses. Specifically, one of the row addresses is switched and output by a combination of the timing switching signal O / C and the high level and low level of the pallet read signal PR. The generation timings of the signals O / C and PR are as shown in the timing chart of FIG.
[0038]
As described above, when the timing switching signal O / C and the palette read signal PR are at the low level, the row address data set in the row address register 3 is selected, and the timing switching signal O / C is at the high level, and the palette read. When the signal PR is at low level, the row address data supplied from the vertical position control circuit 5 is selected. When both the timing switching signal O / C and the palette read signal PR are at high level, they are set in the palette row address register 6. The selected row address data is selected.
[0039]
The horizontal position control circuit 8 detects the start position of the display character in the horizontal direction. During the OSD timing of each machine cycle, the video RAM 1 is addressed based on the output of the horizontal position control circuit 8. When the horizontal position control circuit 8 reaches the horizontal character display start position of the display character read from the row address “00” H and the column address “04” H from the rising edge of the horizontal synchronizing signal Hs, the dot clock DCLK It has a counting means for counting rising edges in binary. In addition, it has the structure which outputs the signal which permits a display only to the horizontal scanning line which displays a character, but this is mentioned later.
[0040]
The counting means generates a pulse PPC when counting is started, starts counting, and generates PPC every time DCLK is counted n times. The horizontal position control circuit 8 also has register means for storing data about the character display start position (count start position). Here, the dot clock DCLK has a frequency at which each dot in the horizontal direction of the character data is one cycle. Therefore, a pulse PPC is generated for each display character break (at the time of change).
[0041]
A pulse PPC from the horizontal position control circuit 8 is applied to the column counter 9 via the OR gate 10. The column counter 9 generates incremented column address data each time the pulse PPC is input.
[0042]
The column address switching circuit 11 selects one of the outputs of the column address register 4, the column counter 9, and a latch circuit 15 described later in accordance with the timing switching signal O / C and the palette read signal PR, and applies the selected output to the video RAM 1. Switch column address data. Specifically, when both the timing switching signal O / C and the palette read signal PR are at the low level, the column address data set in the column address register 4 is selected, and when the timing switching signal O / C is at the high level, the palette read signal is selected. When the PR is at the low level, the column address data counted by the column counter 9 is selected, and when both the timing switching signal O / C and the palette read signal PR are at the high level, the output of the latch circuit 15 is selected.
[0043]
In this manner, the video RAM 1 determines the row address and the column address, and the data (character code, attribute code, modification data) of the address is read out. In the vertical position control circuit 5, in order to detect the character start position in the vertical direction, as described above, data is written at the address specified by the row address “00-0F” H and the column address “00” H. Data capture is required. Therefore, all 9-bit data VDATA of the video RAM 1 read at the falling edge of the timing switching signal O / C is applied to the vertical position control circuit 5.
[0044]
"Processing of video RAM read output VDATA"
The character code latch circuit 12 latches only the character code in VDATA, which is the OSD timing read output of the video RAM 1.
[0045]
The attribute code latch circuit 13 latches only the attribute code among the outputs of the video RAM 1. Therefore, when the most significant bit MSB of the read output VDATA of the video RAM 1 is “1” and the attribute clock ATRCK is generated from the horizontal position control circuit 8, the same output as ATRCK output from the AND gate 14 is generated. In synchronization with the fall, the lower 8 bits (attribute code) of VDATA are latched.
[0046]
The output of the AND gate 14 is also applied to the other input of the OR gate 10 to which the signal PPC is supplied to one input, and the value of the column counter 9 is set to the clock just before the attribute code latch circuit 13 latches the attribute code. It is incremented by +1 in synchronization with the rising edge of ATRCK.
[0047]
The latch circuit 15 decodes the attribute code latched by the attribute code latch circuit 13 into a column address in the palette data area and latches it in synchronization with the rising edge of the pulse PPC. As a result, the latch circuit 15 receives data for identifying the character color or background color (upper 8 bits of the attribute code), character color on / off data (upper 7 bits of the attribute code), and on / off of the background color. Data (upper sixth bit of the attribute code) and column address data in the palette data area are held.
[0048]
The modification data latch circuit 16 has a fixed row address data “10” H output from the palette row address register 6 and a video specified by the column address data “00-2F” output from the latch circuit 15. The modification data (attribute data) read from an arbitrary address in the palette data area of the RAM 1 is latched. This data latch is performed in synchronization with the rising edge of the modified data clock PLDCLK output from the horizontal position control circuit 8.
[0049]
In the character ROM 17, a predetermined dot pattern having a character font of vertical m dots × horizontal n dots is stored at each address. Then, an address is designated by the character code stored in the character code latch circuit 12, and a character to be read (an area where a character font for one character is stored) is determined. The vertical position in the dot data of one character is determined by the address signal indicating the horizontal line supplied from the vertical position control circuit 5. Accordingly, the dot data for n bits in the horizontal direction of one character is read out once.
[0050]
Each time the character code latched by the character code latch circuit 12 is changed, the character to be read is changed. When reading of one horizontal line is completed, reading of the next line is started, and reading of data of the next horizontal line of the same character is repeated.
[0051]
A shift register 18 is connected to the output of the character ROM 17. The shift register 18 is an n-bit shift register, holds n-bit data read from the character ROM 17 in synchronization with the rising edge of the pulse PPC, and stores n-bit dot data in synchronization with the dot clock DCLK. Serial output.
[0052]
On the other hand, a register A 19 and a register B 20 are connected to the qualified data latch circuit 16. When the data latched by the decoration data latch circuit 16 is decoration data for designating the color of the display character itself, the register A19 holds the data in synchronization with the rising edge of the pulse PPC. On the other hand, the register B20 holds the modification data indicating the background color attached to the display character at the same timing.
[0053]
The selection latch circuit 21 is a circuit for selectively inputting the modification data to one of the registers A19 and B20. The selection latch circuit 21 latches the latch circuit 15 in synchronization with the falling edge of the pulse PPC applied through the inverter 22. Latches whether the specified attribute code is text color or background color. For example, the selection latch circuit 21 permits input to the register A19 when “0” is latched, and permits input to the register B20 when “1” is latched.
[0054]
Based on the output from the color output control latch circuit 24, the output processing circuit 23 performs signal processing on the dot data output from the shift register 18 and the modification data output from the registers A19 and B20. A signal for displaying a character that has been subjected to RGB signal processing on the screen is output.
[0055]
The color output control latch circuit 24 latches the character color on / off data and the background color on / off data in the attribute code latched by the latch circuit 15 in synchronization with the rising edge of the pulse PPC. Then, by supplying this latch output to the output processing circuit 23, ON / OFF of the character color and the background color in the output processing circuit is controlled.
[0056]
"Partial read from character ROM"
Here, in the present embodiment, the area for one character, the vertical m bits, and the horizontal n bits of the character ROM (character ROM) 17 can be divided into a plurality of parts in the vertical direction and partially read out. That is, as shown in FIGS. 3A and 3B, when the vertical address is 32 bits from “00000” to “11111”, the addresses from M to N can be read out. . Therefore, a part of the character “A” can be output in FIG. 3A, and only the character “B” or “b” can be output in FIG. 3B. Needless to say, by changing the values of M and N, it is possible to read an arbitrary part of the area for one character.
[0057]
For this purpose, the vertical position control circuit 5 and the horizontal position control circuit 8 are configured as shown in FIG. The counter 30 is preset with the display start position “M” as an initial value, then counts the rising edge of the horizontal synchronization signal, and increments the count value by +1. The register 31 holds the display end position “N”. The comparison circuit 32 determines whether the count value of the counter 30 matches the value held in the register 31. By this circuit, the vertical display permission signal VDSPEN is output only when the position of the horizontal line is between “M” to “N” of the character to be displayed. Therefore, this configuration will be described in detail below.
[0058]
First, HCLK is input to the clock input terminal of the counter 30. This HCLK is a pulse signal generated at the rising edge of the horizontal synchronizing signal. Therefore, the counter 30 can count the rising edge of the horizontal synchronizing signal by counting the HCLK. The HCLK is also input to one end of the latch circuit 33. The other end of the latch circuit 33 is high when the character display start horizontal line stored at the column address “00” H is reached. The coincidence signal ROWSTART that is leveled is input. Therefore, the latch circuit 33 outputs a high level during a period from the high level of the coincidence signal ROWSTART to the next high level of HCLK. Further, the output of the latch circuit 33 is input to one end of the AND gate 34, and the other end of the AND gate 34 is supplied with a signal CLM1RD that becomes high level at the read timing of the column address “01” H. The output is connected to the preset permission terminal of the counter 30 as a signal CLM1ST. Further, the 0th to 5th bits of the read data of the video RAM 1 are input to the preset data terminal of the counter 30.
[0059]
Therefore, the output “M” of the video RAM 1 at the column address “01” H after the coincidence signal ROWSTRAT rises is preset in the counter 30, and the counter 30 subsequently counts up the horizontal sync signal, that is, the horizontal lines sequentially. To do.
[0060]
On the other hand, the signal CLM2RD, which is the read timing of the column address “02” H, is input to the clock input terminal of the register 31 via the AND gate 35 as the signal CLM2ST. The output of the latch circuit 33 is input to the other input terminal of the AND gate 35, and the register 31 receives the “M” from the counter 31 at the next timing when the counter captures “M” in the video RAM 1 having the column address “02” H. Capture output. The output VDATA is “N”, and thus “N” is taken into the register 31.
[0061]
In this state, the counter 30 counts up the horizontal line. Here, the count value of the counter 30 is supplied as a read address of the character ROM 17. Therefore, the character ROM 17 is sequentially read from the vertical position “M” of one character.
[0062]
On the other hand, the output of the counter 30 and the output of the register 31 are input to the comparison circuit 32. The comparison circuit 32 detects whether or not they match, and if they match, outputs a high level output. The output of the comparison circuit 32 is input to a latch circuit 37 via an AND gate 36 that receives a comparison enable signal at the other end. A coincidence signal ROWSTART is input to the other end of the latch circuit 37. Therefore, after the coincidence signal ROWSTART becomes high level, a high level is output from the latch circuit 37 until a high level is output from the comparison circuit 32. The output of the latch circuit 37 is a vertical display permission signal VDSPEN. The comparison enable signal is used to prevent VDSPEN from being output during a period that does not require comparison. The vertical synchronization signal Vs is input to the same input terminal as the output of the comparison circuit 32 of the latch circuit. This is to prevent VDSPEN from being output during an unnecessary period such as a vertical blanking period.
[0063]
On the other hand, the horizontal position control circuit 8 is provided with a counter 40. The counter 40 outputs a high level when it reaches the character display start position. For this purpose, the dot clock DCLK is input to the clock input terminal of the counter 40, the signal CLM4RD defining the reading of the column “04” H is input to the preset permission terminal, and the video RAM 1 is connected to the preset data input terminal. The 0th to 8th bits of VDATA, which is an output of, is input as a complement through the inverter 41.
[0064]
Therefore, the dot clock DCLK is counted after the horizontal synchronizing signal rises, and when the count value reaches the position (value) set by the column address “04” H, a high level output is output.
[0065]
The output of the counter 40 is input to the latch circuit 42, and the signal VDSPEN is input to the other input terminal of the latch circuit 42 via the horizontal synchronization signal Hs and the inverter 43. Therefore, the latch circuit 42 obtains a signal that becomes high level from the horizontal character start position to the rising edge of the horizontal synchronizing signal only when the vertical display permission signal VDEPEN is high level. Therefore, the output of the latch circuit 42 becomes the horizontal display permission signal HDSPEN.
[0066]
Therefore, as shown in FIG. 5, only the section from the vertical position “M” to “N” of the character read from the character ROM 17 is displayed. Since the setting of this section cannot be changed in the horizontal direction, the characters in the horizontal direction are displayed at the same height.
[0067]
However, by such control, a plurality of characters can be written in one character area of the character ROM 17 and read out separately. For example, if one character area and a plurality of characters of different sizes are stored in the vertical direction, the character size can be set by setting “M” and “N” to be written in the column addresses “01” H and “02” H. Can be controlled. Note that the character spacing in the vertical direction can be controlled by the value set in the column address “00”.
[0068]
Next, this operation will be described with reference to FIGS. First, when the horizontal synchronizing signal HS rises, one pulse is output to the signal HCLK. This signal HCLK is always output at the rising edge of the horizontal synchronizing signal HS. The comparison enable also always outputs a pulse at the next timing of the signal HCLK.
[0069]
At the fall of the horizontal synchronization signal, the vertical position control circuit 5 reads the column address “00”, and outputs a coincidence signal ROWSTART when the horizontal scanning position reaches the character display start position. In FIG. 6, it is assumed that this match is obtained in the first comparison. The vertical display permission signal VDSPEN becomes high level by the high level of the coincidence signal ROWSTART. Thereafter, “M” is taken into the counter 30 by the high level of the signal CLM1ST, and “N” is taken into the register 31 by the high level of the signal CLM2ST.
[0070]
Thereafter, each time the signal HCLK is output, the comparison enable becomes high level, the comparison result of the comparison circuit 32 is output, and when the value of the counter 30 becomes “N”, the vertical display permission signal VDSPEN becomes low level. become.
[0071]
The value of the column address “04” is read every time the vertical display permission signal VDSPEN is at a high level, and the counter 40 is preset each time. Therefore, the output HSTART of the counter 40 is output every horizontal line when the display start position is reached. Therefore, the horizontal display permission signal HDSPEN is at the high level during the period from the character display start position of each horizontal line to the rise of the horizontal synchronization signal during the period when the vertical display permission signal VDSPEN is at the high level.
[0072]
"Overall operation"
Next, the overall operation of the circuit shown in FIG. 1 will be described based on the timing chart of FIG. In particular, a case where a code stored in the video RAM 1 is read for display purposes and displayed for one horizontal scan on the television screen (the row address does not change) will be described. FIG. 8 shows an operation after the initial start position of the display character has been recognized. Further, although it is not necessary to synchronize the timing switching signal O / C and the pulse PPC, it will be described in a synchronized state for convenience of explanation.
[0073]
When the pulse PPC rises at time t0, the column counter 9 is incremented in synchronization with the rise of the pulse PPC. Here, it is assumed that the value of the column counter 9 is changed from n−1 to n. At this time, if the character code N-1 corresponding to the column address n-1 is read from the video RAM 1, the character code N-1 is sent to the character code latch circuit 12 in synchronization with the rise of the pulse PPC. Latched.
[0074]
At this time, the timing switching signal O / C rises from the low level to the high level, and the column address data n of the column counter 9 is applied to the video RAM 1 via the column address switching circuit 11 during the subsequent high level period. An address designated by a column address n (row address is fixed at an arbitrary address) of the video RAM 1 is accessed.
[0075]
Next, the code read from the video RAM 1 is changed from N-1 to N in synchronization with the fall of the timing switching signal O / C. Note that the read code of the video RAM 1 corresponding to the column address n is represented by a capital letter N.
[0076]
Here, if the read code N is an attribute code, the MSB is “1”, so that the value of the column counter 9 is changed from n to n + 1 in synchronization with the rising edge of the attribute clock ATRCK. The attribute code N is latched by the attribute code latch circuit 13 in synchronization with the fall of ATRCK.
[0077]
Note that the palette read signal PR is set to a high level during the period when the attribute clock ATRCK is generated. Therefore, the operation of outputting the output of the column counter 9 from the column address switching circuit 11 is prohibited, and instead, the palette address of the previous attribute code already latched in the latch circuit 15 is applied to the video RAM 1. As a result, the pre-qualification data is read from the video RAM 1.
[0078]
At the same time as the rise of the timing switching signal O / C, the modified data clock PLDCK is generated, and the modified data is latched in the modified data latch circuit 16 in synchronization with this rising. It is assumed that the code read from the address specified by the value n + 1 of the column counter 9 is a character code.
[0079]
Here, when the horizontal dot display of the character font for one character is completed and the pulse PPC rises again at time t1, the column counter 9 is incremented in synchronization with the rise of the pulse PPC, and the value of the column counter 9 is increased. Goes from n + 1 to n + 2. At the same time, the character code N + 1 corresponding to the column address data n + 1 is read from the video RAM 1, and the character code N + 1 is latched by the character code latch circuit 12 in synchronization with the rising edge of the pulse PPC. Further, the attribute code N already latched in the attribute code latch circuit 13 is latched in the latch circuit 15 in synchronization with the rising edge of the pulse PPC.
[0080]
Then, the dot data (N−1) accessed by the character code N−1 and read from the character ROM 17 is taken into the shift register 18. In addition, in synchronization with the falling edge of the pulse PPC, the previous modification data latched in the modification data latch circuit 16 is set in either the register A19 or the register B20.
[0081]
At this time, the timing switching signal O / C rises from the low level to the high level, and the column address data n + 2 of the column counter 9 is applied to the video RAM 1 via the column address switching circuit 11 in the subsequent high level period. The address specified by the column address n + 2 of the video RAM 1 (the row address is fixed at an arbitrary address) is accessed.
[0082]
Next, the code read from the video RAM 1 is changed from N + 1 to N + 2 in synchronization with the rise of the timing switching signal O / C. Here, if the read code N + 2 is a character code, the most significant bit MSB of the character code is “0”, so that the value of the column counter 9 is not changed even if the attribute clock ATRCK is generated. It remains n + 2. Further, since the clock for the attribute code latch circuit 13 is not generated from the AND gate 14, the operation of latching the character code N + 2 in the attribute code latch circuit 13 is also prohibited.
[0083]
Since the palette read signal PR is at a high level during the period when the attribute clock ATRCK is generated, the operation of outputting the output of the column counter 9 from the column address switching circuit 11 is prohibited. Instead, the latch circuit The palette address of the attribute code N already latched at 15 is applied to the video RAM 1, and the modification data N is read from the video RAM 1 in synchronization with the fall of the timing switching signal O / C.
[0084]
Next, when the modified data clock PLDCK is generated simultaneously with the rise of the timing switching signal O / C, the modified data N is latched in the modified data latch circuit 16 in synchronization with the rising of the modified data clock PLDCK.
[0085]
Then, when the display of one character is completed and the pulse PPC rises at time t2, the column counter 9 is incremented in synchronization with the rise of the pulse PPC, and the value of the column counter 9 is changed from n + 2 to n + 3. become.
[0086]
As a result, the data read from the video RAM 1 becomes the character code N + 2 corresponding to the column address n + 2, and is latched by the character code latch circuit 12 in synchronization with the rising edge of the pulse PPC. Further, in synchronization with the rise of the pulse PPC, the palette address of the attribute code N latched in the attribute code latch circuit 13 is latched again by the latch circuit 15 and read from the character ROM 17 accessed by the character code N + 1. The output (N + 1) shift register 18 is set.
[0087]
In addition, in accordance with the data specifying the character color or background color of the attribute code already latched in the latch circuit 15 in synchronization with the fall of the pulse PPC, the modification data N latched in the modification data latch circuit 16 Is set in either register A19 or register B20.
[0088]
At this time, the timing switching signal O / C is in a state of rising from the low level to the high level, and the column address data n + 3 of the column counter 9 is applied to the video RAM 1 via the column address switching circuit 11 in the subsequent high level period. Then, an address designated by the column address n + 3 (the row address is fixed at an arbitrary address) of the video RAM 1 is accessed.
[0089]
Next, the code read from the video RAM 1 is changed from N + 2 to N + 3 in synchronization with the fall of the timing switching signal O / C. Here, if the read code N + 3 is an attribute code, the most significant bit MSB of this attribute code is “1”, so that the value of the column counter 9 is incremented from n + 3 to n + 4 in synchronization with the rising edge of the attribute clock ATRCK. Is done. Further, the attribute code N + 3 is latched by the attribute code latch circuit 13 in synchronization with the fall of the attribute clock ATRCK. Further, since the palette read signal PR is at a high level during the period when the attribute clock ATRCK is generated, the operation of outputting the output of the column counter 9 from the column address switching circuit 11 is prohibited, and instead, the latch circuit 15 The attribute code N that has already been latched is applied to the video RAM 1 again, and the modification data N is read in synchronization with the fall of the timing switching signal O / C.
[0090]
Thereafter, when the modified data clock PLDCK is generated simultaneously with the rise of the timing switching signal O / C, the modified data N is latched in the modified data latch circuit 16 in synchronization with the rising of the modified data clock PLDCK.
[0091]
The value of the shift register 18 is (N−1) between the times t1 and t2. On the other hand, the value of the register A19 or the register B20 is rewritten with the pre-modification data. Therefore, during this period, the modification data is applied to the output processing circuit 23, and a predetermined RGB signal is output. Similarly, during the period from time t2 to time t3, the value of the shift register 18 is (N + 1) and the value of the register A19 or B20 is the modification data N, which is applied to the output processing circuit 23, and accordingly A predetermined RGB signal is output.
[0092]
Thus, according to the present embodiment, since the modification data is stored in a part of the address of the video RAM 1, only the attribute code can be stored for one address, so that other types of colors can be specified.
[0093]
In the present embodiment, an arbitrary range in the vertical direction of the character ROM 17 can be read. Therefore, a plurality of characters can be written in the character ROM 17 and read out separately. Therefore, the character ROM 17 can be effectively used.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a character area access control circuit according to the present invention.
FIG. 2 is a diagram showing an area map of a video RAM.
FIG. 3 is a diagram illustrating a configuration of one character in a character ROM.
FIG. 4 is a diagram showing a configuration for partial reading of a character ROM.
FIG. 5 is a diagram illustrating display of one column of characters.
FIG. 6 is a timing chart showing an operation of partial reading of the character ROM.
FIG. 7 is a timing chart showing a partial read operation of the character ROM.
FIG. 8 is a timing chart showing the overall operation.
[Explanation of symbols]
1 video RAM, 17 character ROM, 18 shift register, 19, 20 register, 23 output processing circuit 30 counter, 31 register, 32 comparison circuit.

Claims (1)

A character area access control circuit for accessing an arbitrary portion of an area for one character storing pattern data of the character in order to display the character on the screen,
A display start position of the character on the screen, 1 and the character content head reading position in the vertical direction of the pattern data in any part of the region of the end of the vertical pattern data of an arbitrary portion of the region of one character A video RAM in which a reading position and a character code designating pattern data are stored;
The vertical head reading position is preset, and a counting unit that counts horizontal lines and sequentially increments the reading position;
A storage unit in which the end reading position in the vertical direction is set;
A coincidence detection unit that detects a coincidence between the count value from the counting unit and the value from the storage unit,
Prior to the reading of the character code, the vertical start reading position and the vertical end reading position are set in the counting unit and the storage unit, respectively, so that the pattern data for one character in the vertical direction is set. A character area access control circuit which reads only a range of a vertical end read position from a start read position.

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