JPS6197932A - 圧着型半導体パツケ−ジ - Google Patents

圧着型半導体パツケ−ジ

Info

Publication number
JPS6197932A
JPS6197932A JP59218411A JP21841184A JPS6197932A JP S6197932 A JPS6197932 A JP S6197932A JP 59218411 A JP59218411 A JP 59218411A JP 21841184 A JP21841184 A JP 21841184A JP S6197932 A JPS6197932 A JP S6197932A
Authority
JP
Japan
Prior art keywords
solder
silicon chip
crimp
alumina ceramic
ceramic substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59218411A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0572751B2 (OSRAM
Inventor
Koichi Inoue
井上　広一
Yasutoshi Kurihara
保敏 栗原
Komei Yatsuno
八野　耕明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59218411A priority Critical patent/JPS6197932A/ja
Publication of JPS6197932A publication Critical patent/JPS6197932A/ja
Publication of JPH0572751B2 publication Critical patent/JPH0572751B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10W72/072—
    • H10W72/07236—
    • H10W72/07251—
    • H10W72/20—
    • H10W72/237—
    • H10W72/241—
    • H10W72/251—

Landscapes

  • Wire Bonding (AREA)
JP59218411A 1984-10-19 1984-10-19 圧着型半導体パツケ−ジ Granted JPS6197932A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59218411A JPS6197932A (ja) 1984-10-19 1984-10-19 圧着型半導体パツケ−ジ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59218411A JPS6197932A (ja) 1984-10-19 1984-10-19 圧着型半導体パツケ−ジ

Publications (2)

Publication Number Publication Date
JPS6197932A true JPS6197932A (ja) 1986-05-16
JPH0572751B2 JPH0572751B2 (OSRAM) 1993-10-12

Family

ID=16719489

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59218411A Granted JPS6197932A (ja) 1984-10-19 1984-10-19 圧着型半導体パツケ−ジ

Country Status (1)

Country Link
JP (1) JPS6197932A (OSRAM)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5700715A (en) * 1994-06-14 1997-12-23 Lsi Logic Corporation Process for mounting a semiconductor device to a circuit substrate
WO2014136241A1 (ja) * 2013-03-07 2014-09-12 東北マイクロテック株式会社 積層体及びその製造方法
JP2017028156A (ja) * 2015-07-24 2017-02-02 新光電気工業株式会社 実装構造体及びその製造方法
JP2018195664A (ja) * 2017-05-16 2018-12-06 富士通株式会社 半導体装置及びその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5700715A (en) * 1994-06-14 1997-12-23 Lsi Logic Corporation Process for mounting a semiconductor device to a circuit substrate
WO2014136241A1 (ja) * 2013-03-07 2014-09-12 東北マイクロテック株式会社 積層体及びその製造方法
JP2017028156A (ja) * 2015-07-24 2017-02-02 新光電気工業株式会社 実装構造体及びその製造方法
JP2018195664A (ja) * 2017-05-16 2018-12-06 富士通株式会社 半導体装置及びその製造方法

Also Published As

Publication number Publication date
JPH0572751B2 (OSRAM) 1993-10-12

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