JPS6196765A - Method for forming metal pattern - Google Patents

Abstract

PURPOSE:To form a microstructure metal pattern with its vertical cross section rectangular by a method wherein a very thin, microstructure mask pattern is formed. CONSTITUTION:On the primary surface of a substrate 1, a 0.12mum-thick WN layer 5 and 0.5mum-thick Au layer 2 are formed and the entire surface of the Au layer 2 is covered by a 0.1mum-thick W layer 6 that is the first masking conductive layer. A photoresist film 7 is formed on the entire W layer 6 with the exception of a mask portion 6a. The mask portion 6a is then covered by a second masking conductive layer that is for example, a 0.1mum-thick Ti layer 8. When the photoresist film 7 is removed, the Ti layer 8 is retained only on the mask portion 6a. Etching is accomplished for removal with the Ti layer 8 serving as a mask. The Au layer 2 and the WN layer 5 positioned thereunder are subjected to an ion milling process wherein they are selectively removed with the Ti layer 8 and mask portion 6a serving as a mask, which results in the building of a gate electrode G.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for forming metal turns on a semiconductor substrate, for example, a method for forming an Au gate electrode pattern on a GaAs semiconductor substrate. [Technical background of the invention and its problems] FIG. 2 shows a conventional example of forming an Au electrode pattern on a semiconductor substrate.

First, as shown in FIG. 12(a), an Au layer 2 serving as an electrode pattern and an 11 layer 3 serving as an auxiliary mask are successively deposited on the main surface of a semiconductor substrate 1. Then, a mask of a photoresist layer 4 of an organic compound having a cross-section corresponding to the electrode pattern to be formed is deposited on the Ti layer.Next, as shown in FIG. 2(b), a photoresist layer 4 is formed. Using 4 as a mask, argon (Ar) particles are irradiated from the top of this mask by ion milling.5) First, the Ti layer 3 is selectively removed, and then the photoresist layer 4 and the remaining T
Using the i-layer 3 as a mask, the underlying Au layer 2 is selectively removed by irradiation with similar argon particles to form the Au electrode pattern 2a. A stain electrode pattern is formed by this method. In this case, the following problems arise.

(1) 1t: A fine pattern of a photoresist layer as a mask when forming a polar pattern, for example, a width of 0.
When forming a photoresist pattern of approximately 5 μm, the pattern may be partially removed during photoresist development, and the area of adhesion to the Ti layer may become small, resulting in peeling. It is difficult to form patterns reliably.

(2) When using a photoresist layer as a mask, this photoresist layer has poor etching resistance, so
A film thickness of about m is required. In this way Mayu 2.
When X is thick, the difference (pattern conversion difference) between the width of the yxz pattern and the pattern width of the material to be etched formed by this mask becomes large. For this reason, even if the width of the mask is 0.5 μm, the base of the auxiliary mask (Ti layer) underneath it will widen, and furthermore, the base of the Au electrode pattern will widen, and eventually the Au electrode pattern will expand. The width of the pattern is approximately 1 μm.When forming an electrode pattern, the photoresist that serves as a mask is thick, so the cutting dust of the Ti layer and Au layer adheres to the side surfaces of the photoresist (reattachment effect), changing the shape of the mask. The pattern width of this mask increases. As a result, the width of the electrode pattern increases and desired miniaturization cannot be achieved.

[Purpose of the invention]

The present invention solves the above-mentioned conventional problems and provides a method that can form a thin and fine mask pattern, thereby forming a fine metal pattern with a rectangular vertical cross section. The purpose is to

[Summary of the invention]

In order to achieve the above object, the present invention includes a step of forming a metal layer for patterning on one main surface of a semiconductor substrate, a step of forming a conductor layer for a first mask on this metal layer, and a step of forming a conductor layer for a first mask on the main surface of a semiconductor substrate. A step of forming a photoresist film on a portion of the conductor layer other than the portion that will become the mask pattern, and forming a second mask conductor layer on the portion of the photoresist film and the portion that will become the mask pattern of the first mask conductor layer. The process of
When the photoresist film is peeled off, the second mask conductor layer on the photoresist wheel is removed, and the second mask conductor layer is applied only to the portion of the first mask conductor layer that will become the Yask pattern. The step of forming a layer and this second
etching the first mask conductor layer using the mask conductor layer as a mask to form a mask pattern of the first mask conductor layer;
etching the metal layer to be patterned by anisotropic dry etching using the mask pattern of the first mask conductor layer as a mask, and forming a pattern of the metal layer to be patterned on the semiconductor substrate; A metal pattern forming method is characterized by comprising the following steps.

[Embodiments of the invention]

The metal pattern forming method of the present invention is applied to ME8FET (metal semiconductor FET) on a GaAs semiconductor substrate.
An example used in forming a gate electrode will be described with reference to the drawings.

FIG. 1 shows a sectional view showing the steps of this embodiment.

First step As shown in FIG. 1(a), a layer 5 of a metal such as WN (tungstenite-5), which makes a mechanical bond with the semiconductor substrate 1, is coated on the main surface of a GaAs semiconductor substrate 1 with a thickness of 0. The Au layer 2, which is a metal layer to be patterned, is further formed thereon to have a thickness of 0.5 μm. This WNNb2Au
Layer 2 is a metal layer that will eventually become the gate electrode G,
The u layer 2 is provided to lower the resistance of the gate electrode.

2nd process Figure 1(b) As shown in K, Au layer 2
A conductor layer for the first mask, for example, a W (tungsten) layer 6, is deposited on the entire surface of the substrate to a thickness of o, i .mu.m.

Third step As shown in FIG. 1(C), the entire surface of the W layer 6 excluding the mask portion 6a is photo-photographed so as to form an open lower a above a predetermined portion (mask portion) 6a of the W layer 6. Fourth step of forming a resist film 7 As shown in FIG. 1(d), a second mask conductor layer, for example 11 Layer 8 has a thickness of 0
．． It is deposited to a thickness of 1 μm. At this time, 11 layers 8 are thinly formed on the side wall of the open lower a.

Fifth step As shown in FIG. 1(e), when the photoresist film 7 is removed using a resist stripping agent, the 11 layers 8 are cut on the side wall of the open lower a, and the 11 layers 8 on the photoresist are cut off.
The photoresist 7 is also removed, leaving the 11th layer 8 only on the masked portion 6a of the W layer 6.

6th process As shown in FIG. 1 (0), reactive ion etching is performed using CF4 and 02 gas using the 11th layer 8 as a mask to remove the W layer other than the masked portion 6a of the W layer; 6
Remove by etching.

Seventh Step As shown in FIG. 1(g), using the mask portions 6a of the 11th layer 8 and the W layer as a mask, anisotropic dry etching, such as ion milling using argon ions, is performed to remove the F) Au layer 2 and The WN layer 5 below is selectively removed. As a result, a Sigut electrode G is formed.

Eighth Step As shown in FIG. 1(h), the mask portion 6a of the 11 layer 8 and the W layer used as a mask as necessary.
remove.

Through the above steps, MES on GaAs semiconductor substrate
When forming a gate electrode in a FET, there are effects as described below.

(1) In this example, since the photoresist film has a fine open pattern with the same shape as the gate electrode pattern to be obtained, the photoresist film has a large area, and the underlying metal layer (W layer) It is covered with Therefore, this mask pattern can be easily and reliably miniaturized. This rounded gate electrode pattern can be further miniaturized, and a gate electrode with a short gate length can be formed.

By shortening the gate length, the junction area between the gate electrode and the semiconductor substrate (channel region) becomes smaller.This reduces the input capacitance and feedback capacitance, reduces the noise of this MESFET, and reduces the transconductance. High frequency characteristics are improved, such as increased gain.

In addition, in the case of digital signals, the input capacitance decreases, mutual conductance increases, and the response speed (switching speed) increases.
will improve.

(2) In this example, the first mask conductor layer (W layer)
The patterning is performed by reactive ion etching using the second mask conductor layer (Ti layer) as a mask. According to this reactive ion etching, the difference in pattern conversion between the mask and the pattern of the material to be etched formed by this mask becomes extremely small. Therefore, the first mask conductor layer can be patterned to the same dimensions as the second mask conductor layer.

(3) Furthermore, the Ti layer of the second mask conductor layer in this example is C
Since it is resistant to reactive ion etching of F4+02 gas, the film thickness can be reduced to 0.1 μm.

This is 10 minutes thinner than the film thickness of a conventional photoresist film. Therefore, the pattern conversion difference is smaller when this Ti layer is used as a mask than when the secondary photoresist film is used as a mask. The difference between the pattern width of the mask and the pattern width of the electrode formed using this mask becomes smaller.

As a result, in this embodiment, compared to the conventional example, electrode patterning can be carried out more accurately according to the dimensions determined by the mask. In addition, since the pattern conversion difference is small, the vertical cross section of the gate electrode formed has a rectangular shape in which the upper side of the cross section has approximately the same length as the lower side (gate length). This rectangular gate electrode has a larger vertical cross-section when considering the lower side (gate length) as a reference, compared to a conventional trapezoidal electrode whose upper side is smaller than its lower side. Therefore, the resistance of the gate electrode formed according to this embodiment is reduced.

(4) Since this example uses a Ti layer that is resistant to etching by ion milling using argon particles, the etching time can be longer than the conventional method using a 7-photoresist as a mask. This makes it possible to pattern even thick electrodes.

(5) In addition to the above, in this embodiment, the second
CF4+0 using the Ti layer as a mask conductor layer as a mask
Reactive ion etching is performed using two gases.

This reactive ion etching makes it possible to side-etch the side surface of the mask with good controllability by utilizing the chemical reactivity of the gas. The mask pattern of the W layer, which is the conductor layer for one mask, can be formed with good controllability.

This allows the Sigut electrode to be made of Ti, which is the conductor layer for the second mask.
It can be made even finer than a film mask.

i The present invention is not limited to the above embodiment; for example, the first mask conductor layer may be made of Mo, and the second mask conductor layer may be made of AIK. Further, the first mask conductor layer was formed of Ti, the second mask conductor layer was formed of Au, and C! In other words, the conductor layer for the first mask and the conductor layer for the second mask are conductors with a high selectivity by reactive ion etching, and at least the conductor layer for the first mask The conductor layer may be any material as long as it has good etching resistance as a mask for forming an electrode pattern.

〔Effect of the invention〕

According to the present invention, of the two-layered mask used in metal pattern formation, the upper mask can be made thinner and finer, and the lower mask can be formed to have the same dimensions as the upper mask. It can be made very fine.

A fine metal pattern with a rectangular vertical cross section can be formed using this two-layer mask. Also,
This has the great effect of improving the high frequency characteristics of a semiconductor element formed with this electrode pattern.

[Brief explanation of the drawing]

Fig. 1 is a process cross-sectional view showing one embodiment of the method of the present invention;
The drawings are process cross-sectional views for explaining a conventional example. 6... A conductor layer for a first mask, 7... A photoresist film, 8... A conductor layer for a second mask. Figure 1 (a) (b) Figure 1 Figure 2 (a) (b)

Claims (1)

[Claims] A step of forming a metal layer to be patterned on one main surface of a semiconductor substrate, a step of forming a first conductor layer for a mask on this metal layer, and a step of forming a conductor layer for a first mask on a portion of the conductor layer for a mask other than the mask pattern. a step of forming a photoresist film on a portion, a step of forming a second mask conductor layer on the photoresist film and a portion of the first mask conductor layer that will become a mask pattern, and peeling off the photoresist film. By this, the step of removing the second mask conductor layer on the photoresist top film and forming the second mask conductor layer only in the portion of the first mask conductor layer that will become the mask pattern; etching the first mask conductor layer by reactive ion etching using the second mask conductor layer as a mask to form a mask pattern of the first mask conductor layer; and a mask pattern of the first mask conductor layer. A method for forming a metal pattern, comprising: etching the metal layer to be patterned by anisotropic dry etching using a mask as a mask, and forming a pattern of the metal layer to be patterned on the semiconductor substrate. .