JPS6195545A - Semiconductor ic device - Google Patents

Abstract

PURPOSE:To make it possible to connect electrically MISFETs of a first I/O cell and a second I/O cell for forming a buffer circuit, by providing a wiring region between a bonding pad and the I/O cells. CONSTITUTION:Gate insulating films 21A and 21B are formed, and gate electrodes 22A and 22B are formed. Next, an insulating film 28 is formed, and a connecting hole 29 is formed. Then, after a conductive layer 11 is formed, an insulating film 30 is formed. Then, a connecting hole is formed by removing the gate insulating films 21A and 21B and the insulating films 28 and 30 on semiconductor regions 23A and 23B. Subsequently, conductive layers 35, 36 and 37 are formed, an insulating layer 32 is formed, and the insulating films 30 and 32 on conductive layers 11J and 11I and a conductive layer 11E are removed, so as to form a connecting hole. Moreover, the conductive layer 36 and the insulating film 32 are removed, so as to form a different connecting hole. Next, after a conductive layer 27 and a bonding pad are formed, a protecting film is formed, and the protecting film on the bonding pad is removed to open a hole. By this method, a conductive layer for connecting electrically MISFETs of two I/O cells can be provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor integrated circuit device (IC), and particularly to a technique that is effective when applied to an IC equipped with a gate array.

[Background Art] A gate array is composed of complementary MISFETs (C-MISFETs) that constitute logic circuits such as NAND gates and NOR gates.
5FET) arranged in a row on a semiconductor substrate. An electrical signal from the logic circuit is output to an external IC through a punch ink pad provided on the periphery of the IC, and an electrical signal from the external IC is input to the logic circuit through a bonding pad. . The waveform of an electrical signal input from an external IC is deformed and attenuated due to parasitic capacitance, resistance, etc. of the transmission path. Therefore, in an IC equipped with a gate array, a buffer circuit that performs waveform shaping, amplification, etc. of an electrical signal is provided between the bond ink butt and the logic circuit, and the electrical signal is input to the logic circuit through this buffer circuit. There is. Furthermore, when the electrical operation level of the logic circuit and the external IC are different, it is necessary to convert the internal logic circuit's electricity (No. 3) to the operating level of the external IC and output it. Since the logical configuration of the circuit changes variously depending on customer requests, the output buffer circuit y3 and the human buffer circuit must be configured accordingly.Therefore, in order to respond to changes in the logical configuration, the input and output C-M I with a pounding butt row of l/○ cells equipped with multiple MISFETs that can configure two buffer circuits of the buffer circuit.
There are multiple stages between it and the S column.

As a result of studying the I10 cell, the inventor found the following problem. In order to configure a buffer with a large amplification factor, a large MISFET must be provided in the I10 cell. In addition, 1. In order to cope with changes in the logic configuration of the gate array, each of the large M I S FETs is
Must be provided in 10 cells. Therefore, when providing a buffer γ with a large amplification factor, it is necessary to reduce the number of I10 cells or increase the chip size.

The utilization of the M I S FET in the I10 cell decreases.

Techniques regarding the layout of gate array cells and the periphery of bonding pads are disclosed in, for example, Japanese Patent Application No. 134316/1983.

CObject of the Invention An object of the present invention is to provide a technique that enables electrical connection of MISFETs of a first I10 cell and a second I10 cell for configuring a buffer circuit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, a wiring area is provided between the bonding pad and the I10 cell.

Hereinafter, the configuration of the present invention will be explained along with examples.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiment] FIGS. 1 to 4 are diagrams for explaining an IC according to an embodiment of the present invention. FIG. 1 is a plan view showing the layout of the IC, and FIG. 2 is a plan view showing the layout of the IC. FIG. 3 is a plan view showing the peripheral part of the IC using logical symbols, FIG. 3 is a plan view of the main part of the peripheral part of the IC, and FIG. 4 is a cross-sectional view taken along the line IV-IV in FIG. 3. .

Note that FIG. 3 does not illustrate the insulating film provided between the conductive layers in order to make it easier to see the configuration of the main parts of the IC.

In FIGS. 1 to 4, reference numeral 1 denotes a semiconductor substrate made of P-type silicon single crystal, in the center of which 8 C-MI columns 2 forming a logic circuit are arranged in multiple stages at predetermined intervals. be. The C-MIS column 2 has a NAND gate and a NOR gate by electrically connecting a plurality of C-MISFETs.
Basic cells (
(not shown) are arranged in a row.

3 is an internal wiring region (internal wiring channel) provided on the semiconductor substrate 1 between C-M I 8 rows 2;
M I 8 A plurality of C-MISFETs provided in row 2 or a plurality of conductors that electrically connect between basic cells? l1WI(
(not shown) is provided.

4 is an I10 cell, which is connected to the C-MIS column 2 of the semiconductor substrate 1.
A plurality of rows are provided between the pad and the pad 5. The I10 cell 4 amplifies, waveform shapes, or converts the level of an electrical signal from an external device (not shown) that is input through the bonding pad 5 or the electrical signal of the logic circuit that is output through the bonding pad 5. As shown in FIG. 2, the I10 cell 4 of this embodiment, which performs An inverter is provided in the adjacent I10 cell 4. That is,
A plurality of I10 cells 4 are configured with inverters 7.8 and 9.10 as 111th (unit) cells, and this I10
Cells 4 are arranged in rows around the chip in a repeated manner in the same pattern.

Reference numeral 6 denotes a peripheral wiring region (peripheral wiring channel), which is provided between the I10 cell 4 and the bonding pad 5, as shown in FIG. The peripheral arrangement 4A area 6 is the first I1
Either the inverter 7°8.9 or 10 provided in the 0 cell 4 and the inverter 7.8 provided in the second I10 cell 4
．． This is a region for providing a conductive layer that electrically connects either 9 or 10.

In this embodiment, as shown in FIG. 2, a Schmitt trigger circuit is constructed by inverters 7, 8, 9 provided in the I10 cell 4A and inverter 7 provided in the I10 cell 4B. The inverter 7 of the I10 cell 4A is a P-channel MISFET (P-MISFET) 1 shown in FIG.
2 gate electrode 22A and N-channel MISFET (N
-MISFET) 13 gate electrode 22B and conductive layer 1
It is electrically connected and configured by 1A. Inverter 8 is ;'-gate electrode 22A of MISFET 14
and N-MISFET 15 (7) gate salt t'+22B are electrically connected by a conductive layer 11B. Further, the inverter 9 is configured by electrically connecting the gate salt tifi22A of the P-MISFET 16 and the gate itI pole 22B of the N-MISFET 17 through a conductive layer 11C. Furthermore, the inverter 7 of the I10 cell 4B connects the gate electrode 22A of the P-MISFET 12 with the N
- The gate electrode 22B of the MISFET 19 and the conductive layer 11
They are electrically connected by D. Said P-M
As shown in FIG. 4, the ISFET 18 is composed of a gate insulating film 2IA, a gate electrode 22A, a P" type semiconductor region 23A used as a source region or a train region, and a channel region. −
They are provided in a pair on both sides of the gate electrode 22A on the main surface of the mold well region 20, spaced apart from each other. The channel region is provided on the main surface of the well region 20 under the gate ff electrode 22A. As shown in FIG. 4, the N-MISFET 19 is composed of a gate insulating film 21B, a gate electrode 22B, an n9 type semiconductor region 23B used as a source region or a drain region, and a channel region.

The semiconductor region Vi, 23B is the gate electrode 2 of the semiconductor substrate 1
They are provided in a pair on the main surface of both sides of 2B, spaced apart from each other.

The channel region is provided on the main surface of the semiconductor substrate l below the gate electrode 22B. In addition, P-MISFET12.
14.16 is composed of the same gate electrode 21A, gate T'r1t@22A, semiconductor region 23A, and channel region as the P-MISFET 1B, and
N-M I S FET13.15.17 is N-M
It is composed of a gate insulation film 21B, a gate electrode 22B, and a channel region similar to the ISFET 19. The electrical signal input to the bonding pad 5 passes through the conductive layer 11E shown in FIG. 2 and FIG.
It is input to ET12 and N-MISFET13 (inverter 7). P-MISFET12 and N-MISFE
The output from T13 passes through the conductive layer 11B to P-MISFE.
The outputs of MISFETs 14 and 15 are input to T14 and N-MISFET 15 (inverter 8), and the outputs of MISFETs 14 and 15 are input to P-MISFET 16 and N-MIS through the conductive layer 11C.
It is input to FET 17 (inverter 9). and,
The outputs of the MISFETs 16 and 17 are input to the logic circuit configured in the C-MIS column 2 through the conductive layer 11H. On the other hand, a part of the outputs of the P-MISFET 14 and the N-MISFET 15 (inverter 8) pass through the conductive layer 11C, the gate electrode 22B of the N-MISFET 17, and the conductive layer 11F extending in the peripheral wiring region 6 to the P-MISFET 18. and N-MISFET19
(inverter 7). And those MI
The outputs of the SFETs 18 and 19 pass through the conductive layer 11G extending in the peripheral wiring region 6 to the P-MISFET 16 and the N-
It is fed back to MI S FET17. The conductive layer 11 is provided on an insulating film 28 provided to cover the gate electrode 22, as shown in FIG. The conductive layer 11 is the insulating film 2
8 or a predetermined semiconductor region 23 used as a gate electrode 22 or a train region through a contact hole 29 formed by selectively removing the gate insulating film 21 and the insulating film 2B.
electrically connected to and is.

27 extends to 42 of the insulating film 3o provided to cover the conductive layer 11. The conductive layer 27A is
vS c, connected to a power supply with potential (e.g. O [V]) 11
, the conductive layer 27B has a V CCi level of 1 (for example,
! ]) is connected to the Dennishiki '11. In Figure 3,
The conductive layer 27 is illustrated by a single point tA line.

The predetermined semiconductor region 23A used as the source region of P-~11sFETs 12, 14, 16 and 18 is conductive P! It is electrically connected to the conductive layer 27[3 by I 11.1 and 5. N-MISFET13.1517 and 1
A predetermined semiconductor region 23 used as a source region of 9
B is electrically connected to the conductive layer 27A by the conductive layer 11,1. The conductive layers 11J and 27 are connected through a contact hole 31 formed by selectively removing the insulating film 30. In FIG. 3, the contact holes 29 and 31 are referred to as contact holes 31.

Indicated by a cross, with no code attached. Semiconductor area N2
5A and 23B are not numbered.

32 is a protective film that covers the conductive layer 27 and is an insulating layer 3.
It is provided in the second part of 0.

In Figure 3, 26 is the N-MISFET number),
It should be used with input protection circuit and 15, N-~jls
FET 26, like N-MISFETs 13, 15, 17 and 19, has a gate insulating film 21)A gate 7I! pole 2
In a predetermined semiconductor region 23B of the N-MISFET 26, which is composed of a semiconductor region 23Ba and a channel region 2B, a conductive layer 11E is connected to a gate insulating film 2.
1B, lf! The membrane 28 is selectively removed, and electrical connections are made through the contact holes formed in the . The connection hole is indicated by an X mark, and is not numbered, N-M
The gate electrode 22B of the ISFET 26 and the predetermined semiconductor region 23B separated from the above are electrically connected to the conductive layer 27A through the conductive layer 111.

Note that the I10 cell 4B has the N-MISFET 26
An N-MISFET 26A similar to the above is provided, and a P-MISFET 14.16 or N
15. Similar to 17 P-~1 block S F E T 14
A, 16A or N MISFETs 13A and 17A are provided.

The conductive layer 11 is formed to have a line width of about 3.0 to 3.5 [7×m]. Further, the width of the peripheral wirings Vi, 6 is set so that the conductive layer 11 has five wires between the I10 cell 4 and the punch ink bat. It is used as a sofa circuit 7 to amplify or convert the level of the electrical signal of the logic circuit configured in the C-MIS column 2 and output it to an external device.

According to the present invention, the inverter 10 of the I10 cell 4A and the I
By connecting the inverter 10 of 10 cells 4B in parallel, the IW power output (for example, +f, current amplification) of the output can be increased. I10 cell 4A in - evening 10
To connect in parallel with the inverter 10 of I10 cell 4B, conductive Fv135
．． 36 is provided to connect P-MISFET33 and N-MISFET33.
S F E T 34 and t are electrically connected. The conductive layer 35 connects the output (a) of the logic circuit to P-M I S F
This is for manually connecting ET33 and N MISFET34. The conductive layer 36 is for transmitting the output signals of the P- to jlsFET 33 and the N MISFET 34 to a predetermined punch ink butt 5. Conductive layer 36
In addition, the P-MIS FET 33 has a line width of 10 [μm] to prevent disconnection due to electromigration. Lead 7+, 1 layer 37
It is electrically connected to the conductive layer 27B by. NMISF
The ET 34 electrically connects a predetermined semiconductor region 23B, which is used as a source region, to the conductive layer 27A through a conductive layer 37. The second conductive layer is f)-141S.
FET33 is P-~1 + S F L', T I
Similar to No. 214 and Steps 6 and 18, it is composed of a gate insulating film 21A, a gate I-7 film 22A, a semiconductor region 23A, and a channel region. N-M I S F E
-'V 34 is N-MISFET13.15.17
Similarly to 19, the gate insulating film 21B and the gate voltage (2)
28, semiconductor region 23B and channel GQ11 to somewhere b
consists of and is.

By providing the peripheral wiring area 6 between the I10 cell 4 and the punch ink butt 5 as shown in i'+ii,
Are inverters 7, 8 and 9 of I/○ cell 4A electrically connected to inverter 7 of ■/○ cell 4B? Conductive layers 11F and 11G may be provided for this purpose. As a result, a Schmidt-Dricker circuit can be constructed without adding an inverter 7 to the I10 cell 4A.

On the other hand, by providing the peripheral wiring region 6, it is possible to provide a conductive layer 36 for electrically connecting the inverter 10 of the I10 cell 4A and the inverter 10 of the I10 cell 4B. can be increased.

Exposure: The conductive layer 11 is formed in the step of forming the second conductive layer 1, and the conductive layer 35, 36 is formed in the step of forming the third conductive layer. +
By forming the second layer in the step of forming the first layer, the driving capacity (for example, current amplification factor)
It is possible to increase the output voltage and form a single output cover sofa circuit. In order to configure both the Schmidt Drika circuit and the 11' and cover 9F circuits, first, the gate insulating film 2L
A, 21) (semiconductor ↑, (the main surface of circle 1 is oxidized by thermal oxidation [vanguard 1. 7. And gate electrode 2
Kate Den IJi22A, 22I forming 2A, 22B
3 is formed using, for example, a polycrystalline silicon layer formed by CV[) technology. Next, an insulating film 28 is formed using, for example, a silicon oxide film formed by CVD technology. Membrane 21
A, 21B, insulating film 28, or goo-electrode 22A.

The insulating film 28 on a predetermined portion of 22B is removed and the connection hole 2 is opened.
9 is formed. 5 Next, a conductive layer 11 is formed. The conductive layer 11 is made of, for example, CV
It is formed using a polycrystalline silicon layer. Then, an insulating film 30 is formed. Insulating film 30
is formed using, for example, a CVD technique, using a silicon oxide film.

Next, P-~11SFET3 of I10 cells 4A and 4B
3 and N-MISFET34 gate voltage += 22A, 2
The insulating film on a predetermined portion of 2B is removed to form a contact hole. In addition, the P-M I S F Er 33
or N-MI 5FET34 (71 semiconductor region 23
A, Kate 8 above the predetermined part of 23B! Il! : Membrane 21A
, 21B, the a-diaphragm membranes 28 and 30 are removed to form connection holes.

Then, conductive layers 35, 36 and 37 are formed.

Guide 71! The layers 35 to 37 are formed using, for example, an aluminum layer formed by a vapor deposition technique or an aluminum layer containing silicon (hereinafter simply referred to as an aluminum layer).

Next, six insulation films 32 are formed. The insulating film 32 is (fl
The layer is formed by using a silicate glass film of 100 mL (100 mL) size formed by CVD technology. 5, the conductor 7a layer 11
"2" insulation I+', 130 of a predetermined portion of the conductive layer 11E connected to the punch ink butt 5 and the predetermined portion of the conductive layer 11E
．． 32 is removed to form a connection hole.

Furthermore, a predetermined portion of the conductive layer 36 connected to the honting bat 5 and the -1- insulating film 32 of the conductive layer 37 are removed to form a connection hole different from that in 111f.

Next, a conductive layer 27 and a punch ink butt 5 are formed. The ponting baths 1 to 5 and the conductive layer 27 are
For example, it is formed using an aluminum 911 layer formed by vapor deposition technology. Then, a protective film is formed on the punch ink butt 5 and the conductive layer 27 using IW.

This protective film is formed by, for example, CVD technology.

It is formed using a silicon oxide film.

Next, the retainer pn';r on the punch ink butt 5 is removed to form an opening.

Through the above steps, the Schmidt Drika circuit can be constructed, and furthermore, the inverter 10 of the I10 cell 4A and the inverter 10 of the ■/○ cell 4B can be connected in parallel to construct an output Huff 7 circuit.

[effect] According to the novel technology disclosed by this application.

The following effects can be increased to 11.

(1) By providing a peripheral wiring region (peripheral wiring channel) between the bonding bat and the I10 cell, the M I S F E "" of the first 110 cells and the second I
A conductive layer for electrically connecting the 10 cells of MISFETs can be provided.

(2) According to (1) above, a circuit such as a Schmidt-Dricker circuit can be configured by the MISFET of the first I10 cell and the MISFET of the second I10 cell without adding a semiconductor element to each of the 110 cells. I can do it.

(3) According to (1) above, the MISFET for configuring the output buffer circuit provided in the first I10 cell and the MISFET for configuring the output buffer circuit provided in the second I10 cell are electrically connected. 6 The invention made by the present inventor will be described in detail with reference to embodiments, but the present invention is not limited to the embodiments described above. Of course, various modifications may be made without departing from the spirit of the invention.

[Brief explanation of the drawing]

1 to 4 are diagrams for explaining an IC according to an embodiment of the present invention. FIG. 1 is a plan view showing the layout of the IC, and FIG. 2 is a peripheral portion of the IC. FIG. FIG. 3 is a plan view of essential parts of the peripheral portion of the IC. FIG. 4 is a cross-sectional view of the gland taken along IV-IV in FIG. 3. l...Semiconductor substrate, 2...C-M I S row, 3...
...Internal wiring area, 4.4A, 4B...I10 cell,
5... Bonding pad, 6... Peripheral wiring area,
7,8.9゜10... Inverter, 11, IIA to 11.127.27A, 27B, 35.36.37...
・Conductive layer. 12.13.14.14A, 15.15A, 16°16
A, 17.17A, 18.19.26.26A, 33.
34... MI S FET, 20... Well region, 21A, 21B... Gate insulating film, 22A, 22
B-1-1-i1E pole, 23A, 23B・! 14 Body m region, 24...Field isolation #111.25...Channel stopper region, 28.30...Insulating film, 29.31
...Connection hole, 32...Protective film. Figure I Figure 2 Σ

Claims (1)

[Claims] 1. A plurality of bonding pads are provided in a row on a semiconductor substrate, and a plurality of MISFEs are provided in the vicinity of the bonding pad row.
A semiconductor integrated circuit device in which unit cells having T are arranged in a row, and a MISFET of a first unit cell and a MISFET of a second unit cell are arranged between the bonding pad row and the unit cell row.
A semiconductor integrated circuit device comprising a conductive layer electrically connected to an ISFET. 2. The semiconductor integrated circuit device according to claim 1, wherein the unit cell is for configuring a buffer circuit.