JPS6185158U - - Google Patents

Info

Publication number
JPS6185158U
JPS6185158U JP1984170889U JP17088984U JPS6185158U JP S6185158 U JPS6185158 U JP S6185158U JP 1984170889 U JP1984170889 U JP 1984170889U JP 17088984 U JP17088984 U JP 17088984U JP S6185158 U JPS6185158 U JP S6185158U
Authority
JP
Japan
Prior art keywords
heat sink
flat heat
melting point
low melting
filler metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984170889U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984170889U priority Critical patent/JPS6185158U/ja
Publication of JPS6185158U publication Critical patent/JPS6185158U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Cooling Or The Like Of Electrical Apparatus (AREA)

Description

【図面の簡単な説明】
第1図a,bはこの考案の一実施例を適用した
半導体装置用放熱板を示す側面図および平面図で
あり、第2図a,bおよび第3図は従来の各別例
による放熱板付半導体装置の概要構成を示す断面
図、底面図および斜視図である。 1…半導体素子その他の回路部品をマウントし
たセラミツク厚膜回路基板、2…平板形放熱板、
3…低融点ろう材。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体電子部品のセラミツク厚膜回路基板など
    の放熱面に、低融点ろう材を用いて平板形放熱板
    を接着固定する構成において、前記低融点ろう材
    による接着時に、熱膨張率の差によつて生ずる平
    板形放熱板の反りを補正するため、この平板形放
    熱板に対して、予め意図的に反対方向の反りを賦
    与させたことを特徴とする半導体装置用放熱板構
    造。
JP1984170889U 1984-11-09 1984-11-09 Pending JPS6185158U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984170889U JPS6185158U (ja) 1984-11-09 1984-11-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984170889U JPS6185158U (ja) 1984-11-09 1984-11-09

Publications (1)

Publication Number Publication Date
JPS6185158U true JPS6185158U (ja) 1986-06-04

Family

ID=30728598

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984170889U Pending JPS6185158U (ja) 1984-11-09 1984-11-09

Country Status (1)

Country Link
JP (1) JPS6185158U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE43341E1 (en) 1995-06-07 2012-05-01 Danisco A/S Method of improving the properties of a flour dough, a flour dough improving composition and improved food products

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE43341E1 (en) 1995-06-07 2012-05-01 Danisco A/S Method of improving the properties of a flour dough, a flour dough improving composition and improved food products

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