JPS6179900U - - Google Patents

Info

Publication number
JPS6179900U
JPS6179900U JP16322884U JP16322884U JPS6179900U JP S6179900 U JPS6179900 U JP S6179900U JP 16322884 U JP16322884 U JP 16322884U JP 16322884 U JP16322884 U JP 16322884U JP S6179900 U JPS6179900 U JP S6179900U
Authority
JP
Japan
Prior art keywords
inverter
transfer gate
input terminal
output terminal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16322884U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16322884U priority Critical patent/JPS6179900U/ja
Publication of JPS6179900U publication Critical patent/JPS6179900U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Shift Register Type Memory (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に使用する基本回路の回路図、
第2図は本考案の一実施例のブロツク図、第3図
は従来の双方向シフトレジスタ回路の一例の回路
図である。 1,2,3…D型フリツプフロツプ回路、4,
5,6…選択回路、7…左右方向切換え信号端子
、8…クロツク信号端子、10,10′,10″
…基本回路、11,12,13,14,…インバ
ータ、21,22,23,24,25,26′…
トランスフアゲート、φ,φ…クロツク信号。
Figure 1 is a circuit diagram of the basic circuit used in this invention.
FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a circuit diagram of an example of a conventional bidirectional shift register circuit. 1, 2, 3...D-type flip-flop circuit, 4,
5, 6... Selection circuit, 7... Left/right direction switching signal terminal, 8... Clock signal terminal, 10, 10', 10''
... Basic circuit, 11, 12, 13, 14, ... Inverter, 21, 22, 23, 24, 25, 26'...
Transfer gate, φ, φ...clock signal.

Claims (1)

【実用新案登録請求の範囲】 第1のインバータと該第1のインバータの出力
端に入力端が接続する第1のトランスフアゲート
と、該第1のトランスフアゲートの出力端に入力
端が接続する第2のインバータと該第2のインバ
ータの出力端に入力端が接続し前記第1のインバ
ータの入力端に出力端が接続する第2のトランス
フアゲートとから成る第1の回路と、 第3のインバータと該第3のインバータの出力
端に入力端が接続する第3のトランスフアゲート
と該第3のトランスフアゲートの出力端に入力端
が接続する第4のインバータと該第4のインバー
タの出力端に入力端が接続し前記第3のインバー
タの入力端に出力端が接続する第4のトランスフ
アゲートとから成る第2の回路と、前記第2のイ
ンバータの入力端と第3のインバータの入力端と
の間に接続する第5のトランスフアゲートとから
成る回路を基本回路とし、該基本回路を複数個備
え、前記複数個の基本回路のそれぞれの第1のイ
ンバータの入力端と第4のインバータの入力端と
を接続点として第6のトランスフアゲートで連結
したことを特徴とするシフトレジスタ回路。
[Claims for Utility Model Registration] A first inverter, a first transfer gate whose input terminal is connected to the output terminal of the first inverter, and a first transfer gate whose input terminal is connected to the output terminal of the first transfer gate. a first circuit consisting of a second inverter and a second transfer gate whose input terminal is connected to the output terminal of the second inverter and whose output terminal is connected to the input terminal of the first inverter; and a third transfer gate whose input terminal is connected to the output terminal of the third inverter, a fourth inverter whose input terminal is connected to the output terminal of the third transfer gate, and an output terminal of the fourth inverter. a second circuit comprising a fourth transfer gate whose input terminal is connected and whose output terminal is connected to the input terminal of the third inverter; an input terminal of the second inverter and an input terminal of the third inverter; A circuit consisting of a fifth transfer gate connected between the basic circuits is a basic circuit, and a plurality of the basic circuits are provided, and the input end of the first inverter and the input end of the fourth inverter of each of the plurality of basic circuits are A shift register circuit characterized in that the end of the shift register circuit is connected to the end of the circuit by a sixth transfer gate as a connection point.
JP16322884U 1984-10-29 1984-10-29 Pending JPS6179900U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16322884U JPS6179900U (en) 1984-10-29 1984-10-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16322884U JPS6179900U (en) 1984-10-29 1984-10-29

Publications (1)

Publication Number Publication Date
JPS6179900U true JPS6179900U (en) 1986-05-28

Family

ID=30721087

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16322884U Pending JPS6179900U (en) 1984-10-29 1984-10-29

Country Status (1)

Country Link
JP (1) JPS6179900U (en)

Similar Documents

Publication Publication Date Title
JPS6179900U (en)
JPS5942639U (en) comparator
JPS643329U (en)
JPS6335154U (en)
JPS6181221U (en)
JPS63156124U (en)
JPS5885229U (en) key matrix circuit
JPS59189336U (en) input circuit
JPS5952753U (en) signal transmission circuit
JPS59187225U (en) Delay adjustment circuit
JPS6332398U (en)
JPS593632U (en) time delay circuit
JPS5893046U (en) semiconductor logic circuit
JPS6144903U (en) Non-contact waveguide switch
JPS5927633U (en) Digital IC
JPS61334U (en) Tri-state gate element chip
JPS6427723U (en)
JPS619902U (en) single pole double throw switch
JPS6316713U (en)
JPS6175638U (en)
JPS61103969U (en)
JPS62201532U (en)
JPS5811330U (en) Waveform shaping circuit
JPH0439740U (en)
JPS61103931U (en)