JPS6164133A - 集積回路装置 - Google Patents

集積回路装置

Info

Publication number
JPS6164133A
JPS6164133A JP59186838A JP18683884A JPS6164133A JP S6164133 A JPS6164133 A JP S6164133A JP 59186838 A JP59186838 A JP 59186838A JP 18683884 A JP18683884 A JP 18683884A JP S6164133 A JPS6164133 A JP S6164133A
Authority
JP
Japan
Prior art keywords
chip
wiring
package
terminals
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59186838A
Other languages
English (en)
Other versions
JPH0325013B2 (ja
Inventor
Akihiro Kagami
彰浩 各務
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP59186838A priority Critical patent/JPS6164133A/ja
Publication of JPS6164133A publication Critical patent/JPS6164133A/ja
Publication of JPH0325013B2 publication Critical patent/JPH0325013B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 イ、産業上の利用分野 本発明は、集積回路チップをパッケージ、特にデュアル
インライン型パッケージに収容してなる集積回路装置に
関する。
口、従来の技術 従来、片面プリント基板にデュアルインライン型パッケ
ージの集積回路装置を実装した場合、片方のピン列側か
ら他のピン列側へ配線するには、ビンとビンの間および
集積回路装置の下を通して配扉する。しかし、配線数が
多くなシ、ビンとピ／の間を通せなくなると、迂回して
配録しておった。
ハ０発明が解決しようとする問題点 上記のように、ピン数の多いデュアルインライン型パッ
ケージの集積回路装置をプリント基板に実装した場合、
一方のピン列側から他方のピン列側に配線するとｂｌこ
のパッケージの外側を迂回して配線しなければならず、
配線の長さが長く、かつ複雑になシ、プリント基板面積
の増大２よび配線付加容量およびインダクタンスの増加
など金招くという好゛ましからざる問題が起る。
二１問題点を解決するための技術手段 上記問題点に対し、本発明では、梁槓回路装置パッケー
ジの接続端子のうち、互いに対向関係におる少くとも一
対の非接続端子とそれぞれ接続された、前記パッケージ
に収納固着された集積回路チップ電極パッド同士の間を
、前記チップの内部配線により短絡している。
ホ１作用 上記のように互いに対向関係にある集積回路パッケージ
の非接続端子間は、パッケージ内において、ボンディン
グワイヤおよびチップ内部配線により短絡されているの
で、この短絡線は、前記集積回路装置をプリント基板に
実装し九とき、前記対向非接続端子と接続されているパ
ッケージピンが挿入された前記プリント基板の両ビン受
は端子間のジャンパ線となる。
へ、実施例 つぎに本発明を実施例により説明する。　　゛第１図は
本発明の一実施例の要部平面図である。
第１図において、集積回路パッケージｌのチップ固着部
２に、集積回路チップ３が収納固着されている。チップ
固着部２０周壁上面には、チップ３の電極パッドとそれ
ぞれボンディングワイヤ４により接続された多数の接続
端子５，５．・・・が設けられているが、それらのうち
、上辺の一つの接続端子ＮＣＩと下辺の一つの接続端子
ＮＣ２は共に、本来はどこにも接続されずに遊んでいる
非接続端子であるが、このＮＣ１とＮＣ２は、他の接続
端子と同様に、ボンディングワイヤ４により対応するチ
ップ上の電極パッドｐｌ　、Ｐ２とそれぞれ接続され、
さらに、電極パッドＰ１とＰ２との間は、チップの内部
配線６により短絡されている。
ト１発明の効果 本発明の集積回路装置を、プリント基板に実装すること
により、この集積回路装置実装部を迂回せねばならなか
った配線を直接結ぶことができるので、プリント基板上
の配線の長さを雉＜シ、配線を簡単にする。
【図面の簡単な説明】
第１図は本発明の一実施例の要部平面図である。 ｌ・・・・・・集積回路パッケージ、２・・・・・・チ
ップ固着部、３・・・・・・集積回路チップ、４・・・
・・・ボンディングワイヤ、５・・・・・・接続端子、
６・・・・・・チップ内部配線、ＮＣＩ、ＮＣ２・・・
−・・非接続端子、ＰＩ、Ｐ２・・・・・・短絡用電極
パッド。 ／ＶＣｚ 心　／　図

Claims (1)

    【特許請求の範囲】
  1. 集積回路チップをパッケージのチップ固着部に固着し、
    前記チップの複数の電極パッドと対応する前記パッケー
    ジの接続端子との間をボンディングワイヤで接続してな
    る集積回路装置において、前記パッケージの接続端子の
    うち、互いに対向関係にある少くとも一対の非接続端子
    とそれぞれ接続された前記チップの電極パッド同士の間
    が、このチップの内部配線により短絡されていることを
    特徴とする集積回路装置。
JP59186838A 1984-09-06 1984-09-06 集積回路装置 Granted JPS6164133A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59186838A JPS6164133A (ja) 1984-09-06 1984-09-06 集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59186838A JPS6164133A (ja) 1984-09-06 1984-09-06 集積回路装置

Publications (2)

Publication Number Publication Date
JPS6164133A true JPS6164133A (ja) 1986-04-02
JPH0325013B2 JPH0325013B2 (ja) 1991-04-04

Family

ID=16195512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59186838A Granted JPS6164133A (ja) 1984-09-06 1984-09-06 集積回路装置

Country Status (1)

Country Link
JP (1) JPS6164133A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5473514A (en) * 1990-12-20 1995-12-05 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5561054A (en) * 1978-10-30 1980-05-08 Mitsubishi Electric Corp Large scale integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5561054A (en) * 1978-10-30 1980-05-08 Mitsubishi Electric Corp Large scale integrated circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5473514A (en) * 1990-12-20 1995-12-05 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board
US5613295A (en) * 1990-12-20 1997-03-25 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board and method for manufacturing same
US5646830A (en) * 1990-12-20 1997-07-08 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board
US5715147A (en) * 1990-12-20 1998-02-03 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board

Also Published As

Publication number Publication date
JPH0325013B2 (ja) 1991-04-04

Similar Documents

Publication Publication Date Title
US4772936A (en) Pretestable double-sided tab design
EP0782191A2 (en) Multi-level stacked integrated-circuit-chip assembly
US20020140070A1 (en) Packaging system for die-up connection of a die-down oriented integrated circuit
JPS61101067A (ja) メモリモジユ−ル
KR100328906B1 (ko) 리드프레임의리드온칩내부리드를결합하는방법및장치
JPS63211660A (ja) 集積回路用高端子数パッケージ
JP2004523882A (ja) キャノピー型キャリアを有する電子モジュール
US20050236720A1 (en) Semiconductor chip having pads with plural junctions for different assembly methods
JP2568748B2 (ja) 半導体装置
US5362984A (en) Semiconductor device with jumping wire
US20070120192A1 (en) Method and apparatus that provides differential connections with improved ESD protection and routing
JP2837027B2 (ja) テープキャリアパッケージ
US6483189B1 (en) Semiconductor device
KR950010046B1 (ko) 경사 주변 회로를 가진 집적회로 장치
JPS6164133A (ja) 集積回路装置
JP2001185648A (ja) 半導体装置
JP2533810B2 (ja) 半導体装置
US5691243A (en) Process for manufacturing composite semiconductor device
JPH0482244A (ja) 半導体集積回路装置およびその配線変更方法
JPS6225437A (ja) 多層配線基板
JPH05267459A (ja) Ｌｓｉチップ
JP2643898B2 (ja) 樹脂封止型半導体装置およびその製造方法
JPH1032304A (ja) 半導体集積回路装置の実装におけるバス配線構造
JPH03159797A (ja) Ｉｃカード用分割基板構造
JPH01272492A (ja) Ｉｃ実装装置