JPS6160469B2 - - Google Patents

Info

Publication number
JPS6160469B2
JPS6160469B2 JP55107565A JP10756580A JPS6160469B2 JP S6160469 B2 JPS6160469 B2 JP S6160469B2 JP 55107565 A JP55107565 A JP 55107565A JP 10756580 A JP10756580 A JP 10756580A JP S6160469 B2 JPS6160469 B2 JP S6160469B2
Authority
JP
Japan
Prior art keywords
processing device
processing
bus
communication control
common bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55107565A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5732158A (en
Inventor
Takashi Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP10756580A priority Critical patent/JPS5732158A/ja
Publication of JPS5732158A publication Critical patent/JPS5732158A/ja
Publication of JPS6160469B2 publication Critical patent/JPS6160469B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Between Computers (AREA)
  • Computer And Data Communications (AREA)
  • Small-Scale Networks (AREA)
  • Multi Processors (AREA)
JP10756580A 1980-08-04 1980-08-04 Communication controller Granted JPS5732158A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10756580A JPS5732158A (en) 1980-08-04 1980-08-04 Communication controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10756580A JPS5732158A (en) 1980-08-04 1980-08-04 Communication controller

Publications (2)

Publication Number Publication Date
JPS5732158A JPS5732158A (en) 1982-02-20
JPS6160469B2 true JPS6160469B2 (enrdf_load_html_response) 1986-12-20

Family

ID=14462383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10756580A Granted JPS5732158A (en) 1980-08-04 1980-08-04 Communication controller

Country Status (1)

Country Link
JP (1) JPS5732158A (enrdf_load_html_response)

Also Published As

Publication number Publication date
JPS5732158A (en) 1982-02-20

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