JPS6160469B2 - - Google Patents

Info

Publication number
JPS6160469B2
JPS6160469B2 JP55107565A JP10756580A JPS6160469B2 JP S6160469 B2 JPS6160469 B2 JP S6160469B2 JP 55107565 A JP55107565 A JP 55107565A JP 10756580 A JP10756580 A JP 10756580A JP S6160469 B2 JPS6160469 B2 JP S6160469B2
Authority
JP
Japan
Prior art keywords
processing device
processing
bus
communication control
common bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55107565A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5732158A (en
Inventor
Takashi Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP10756580A priority Critical patent/JPS5732158A/ja
Publication of JPS5732158A publication Critical patent/JPS5732158A/ja
Publication of JPS6160469B2 publication Critical patent/JPS6160469B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Transfer Between Computers (AREA)
  • Computer And Data Communications (AREA)
  • Small-Scale Networks (AREA)
JP10756580A 1980-08-04 1980-08-04 Communication controller Granted JPS5732158A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10756580A JPS5732158A (en) 1980-08-04 1980-08-04 Communication controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10756580A JPS5732158A (en) 1980-08-04 1980-08-04 Communication controller

Publications (2)

Publication Number Publication Date
JPS5732158A JPS5732158A (en) 1982-02-20
JPS6160469B2 true JPS6160469B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1986-12-20

Family

ID=14462383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10756580A Granted JPS5732158A (en) 1980-08-04 1980-08-04 Communication controller

Country Status (1)

Country Link
JP (1) JPS5732158A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Also Published As

Publication number Publication date
JPS5732158A (en) 1982-02-20

Similar Documents

Publication Publication Date Title
US4504906A (en) Multiprocessor system
US4414627A (en) Main memory control system
JPH0256690B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
US4467454A (en) High-speed external memory system
JPS6160469B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP3114870B2 (ja) マイクロプログラムローデイング方法とローデイング制御装置と情報処理装置と情報処理システム
JPH0554009A (ja) プログラムロード方式
JP2710777B2 (ja) 中間制御装置のテスト回路
JPS6146552A (ja) 情報処理装置
JPS61160144A (ja) エミユレ−シヨン方式
SU1185333A1 (ru) Мультипрограммное устройство управления с контролем
JPS644211B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPS6013494B2 (ja) 自己診断方式
JP3324567B2 (ja) 論理シミュレーション装置
JPS59157753A (ja) サブプロセツサ制御方式
JPS59106054A (ja) 情報処理システム
JPS62180443A (ja) 計算機システムの初期設定方式
JPS6238746B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPS6020771B2 (ja) マイクロ診断方式
JPH04107745A (ja) インサーキット・エミュレータ
JPH03182949A (ja) 計算機システムにおける主記憶装置の診断方式
JPH0424733B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPH0242529A (ja) 入出力処理装置
JPS63145562A (ja) 入出力処理装置のチヤネルコマンド語読出し方式
JPH04262443A (ja) 情報処理装置