JPS6159562A - インタフエ−ス制御方式 - Google Patents

インタフエ−ス制御方式

Info

Publication number
JPS6159562A
JPS6159562A JP59181155A JP18115584A JPS6159562A JP S6159562 A JPS6159562 A JP S6159562A JP 59181155 A JP59181155 A JP 59181155A JP 18115584 A JP18115584 A JP 18115584A JP S6159562 A JPS6159562 A JP S6159562A
Authority
JP
Japan
Prior art keywords
activation
flag
request
bus
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59181155A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0364894B2 (OSRAM
Inventor
Haruhiko Tsunoda
治彦 角田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59181155A priority Critical patent/JPS6159562A/ja
Publication of JPS6159562A publication Critical patent/JPS6159562A/ja
Publication of JPH0364894B2 publication Critical patent/JPH0364894B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4063Device-to-bus coupling
    • G06F13/4068Electrical coupling
    • G06F13/4072Drivers or receivers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Information Transfer Systems (AREA)
JP59181155A 1984-08-30 1984-08-30 インタフエ−ス制御方式 Granted JPS6159562A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59181155A JPS6159562A (ja) 1984-08-30 1984-08-30 インタフエ−ス制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59181155A JPS6159562A (ja) 1984-08-30 1984-08-30 インタフエ−ス制御方式

Publications (2)

Publication Number Publication Date
JPS6159562A true JPS6159562A (ja) 1986-03-27
JPH0364894B2 JPH0364894B2 (OSRAM) 1991-10-08

Family

ID=16095848

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59181155A Granted JPS6159562A (ja) 1984-08-30 1984-08-30 インタフエ−ス制御方式

Country Status (1)

Country Link
JP (1) JPS6159562A (OSRAM)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips

Also Published As

Publication number Publication date
JPH0364894B2 (OSRAM) 1991-10-08

Similar Documents

Publication Publication Date Title
US4271466A (en) Direct memory access control system with byte/word control of data bus
CA1152221A (en) Peripheral unit controller
US4253147A (en) Memory unit with pipelined cycle of operations
FI92262C (fi) Joustava väyläjärjestelmä
EP0036172A1 (en) Multi-station processor intercommunication system comprising means for remote processor initialization
US5454081A (en) Expansion bus type determination apparatus
US4218739A (en) Data processing interrupt apparatus having selective suppression control
JPS61500043A (ja) 制御チヤネルインタ−フエイス回路
EP0712078B1 (en) Data processor with transparent operation during a background mode and method therefor
US5313621A (en) Programmable wait states generator for a microprocessor and computer system utilizing it
US4559595A (en) Distributed priority network logic for allowing a low priority unit to reside in a high priority position
JPS6159562A (ja) インタフエ−ス制御方式
US5261083A (en) Floppy disk controller interface for suppressing false verify cycle errors
JPS6242306B2 (OSRAM)
JPH0786865B2 (ja) 多重プロセッサ・レベル変更同期装置
JPH02207364A (ja) データ転送方式
JP3261665B2 (ja) データ転送方法及びデータ処理システム
JPH09167117A (ja) マイクロコンピュータおよびこれを用いたリアルタイムシステム
KR920001594B1 (ko) 컴퓨터용 인터페이스보드
JPS61109154A (ja) 固定デ−タ・レジスタのエラ−検出方式
KR970002399B1 (ko) 안정적인 버스 중재정보 구동을 위한 상태 할당방법(State assignment for stable drive of bus arbirtation information)
JPS58159129A (ja) マイクロコンピユ−タシステムのdma制御装置
JPH0981465A (ja) 主記憶制御装置
KR960015586B1 (ko) 다중프로세서 인터럽트 요청기에서의 전송 실패 인터럽트의 구동방법
JPS63109565A (ja) プロセッサを他のプロセッサのバスに適合させるオートマトン