JPS6159532A - Instruction controller - Google Patents

Abstract

PURPOSE:To discriminate the type quickly and flexibly and to attain desired branch by reading a microinstruction stored in a branched address calculated by an MPC change circuit from a control storage device and controlling it to be processed. CONSTITUTION:A jumped address value stored in a microprogram counter (MPC)2 and a value corresponding to a tag in a general-purpose register 3 are added by an adder 4 and fed to a control storage device (CS)6 via a multiplexer 5. Further, the MPC change circuit 1 applies the microaddress of a jump destination corresponding to the information discriminating the type stored in a data area of the register 3 in a form corresponding to a prescribed microinstruction fed from the CS6. Thus, the address is jumped quickly to a desired address and it is controlled by using less storage area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is directed to an instruction control device, especially when performing control in a manner corresponding to the type of data specified by a tag attached to the data. The present invention relates to an instruction control device configured to calculate a branch destination at high speed using software.

[Problems to be solved by conventional technology and invention] Conventionally,
In a computer system, control is performed by executing multiple branches or the like in a form corresponding to the type of data attached to the data, such as FIX (fixed point number). At this time, when the number of data types increases, there is a problem that a large number of control memory areas are required to perform the branching, and the processing time becomes long.

For example, the multiway jump (multiple branching) shown in Figure 2
Run the program of the method and FIX 5HOPT (
The operation procedure will be explained for the case of executing a fixed-point number with a single-precision length).

The first step is the microinstruction GR-DATA stored at microaddress 100.

Execute. As a result, data in which information +a representing FIX is stored in the tag is stored in the GR register.

The second step is the microinstruction S/BTG stored at microaddress 101.

Execute. This means executing a multi-way jump, which is given in correspondence with a tag consisting of, for example, 4 bits, which stores information about the micro address 102 and the type of data stored in the program counter. value (for example, “0” for FIX)
”) and jump to the micro address of the addition result, for example, micro address 102. Of course, if the tag (tag is “1”) is, for example, FLOAT, 103 Jump to the address.

The third step executes the instruction stored at the microaddress jumped to in the second step. Here, the tag is “0” indicating that it is FIX (fixed point number).
Since the value of is stored, Mano/!・Address 10
Instruction SQ at address 0, 3 TOPIX.

Execute. That is, it jumps to micro address 200 specified by label FIX.

The fourth step is to execute the microinstruction SQ, BNZ(SIIORT) To 5HORT stored at microaddress 200.
.

to practice. This means that if the 5IIORT flag is non-zero (if the SHORT flag is "if"), jump to the microaddress specified by label 5) IORT. Here, 5IIORT
Since the flag is "1", it jumps to micro address 300 specified by label 5IIORT. This means that the first micro address where the processing program for processing the desired FIX 5) IORT is stored has been reached. If the first micro-
In order to reach address 400, the microinstruction stored at microaddress 201 is sent to the fifth microinstruction.
Must be performed as a step.

As explained above, it is possible to execute the processing program that processes FIX 5IIORT stored at micro address 300 in the fourth cycle counting from micro address 101 where the micro instruction to perform a multi-way jump is stored. can. Also, FIX L
To run the processing program that processes ONG,
Five cycles are required.

In this way, as the number of data types increases, many cycles are required for types that cannot be accommodated in a 4-bit tag, such as 5IIORT and LONG, which correspond to the above-mentioned FIX. ,
There is a problem that a large amount of storage area in the C3 (control storage device) is used and the processing speed becomes slow. Furthermore, if the number of bits used as tags is increased, the area occupied by the data for storing the inner world will become narrower across the board, which will narrow the range for data processing, making it difficult to process data efficiently. Do fl[
There are some problems.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention uses hardware to quickly calculate a branch destination when performing control in a form that corresponds to the type of data specified by the tag attached to the data. With this configuration, even if the number of data types increases, the type can be quickly determined and the branch can be made to a predetermined branch destination address. Therefore, in an instruction control device of the present invention, in an instruction control device that controls branching using a tag indicating the type of data attached to data, the value of the address stored in the program counter and the tag are combined. an adder that generates a branch destination address consisting of a value added with the associated value;
The branch destination address generated by Category>Bg is supplied to the control storage device, and the control storage is converted into information representing the type of data stored in the 1iii data in a form corresponding to the microinstruction read from the iQ device. a microprogram counter change circuit that calculates a branch destination address based on the micro program counter change circuit, and reads a microinstruction stored at the branch destination address calculated by the micro program counter change circuit from the control storage device. The feature is that it is controlled so that it is processed according to the

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a configuration diagram of one embodiment of the present invention, and FIG. 2 is a conventional program example for explaining the operation of the configuration of one embodiment of the present invention shown in FIG.

In the figure, l is an MPC change circuit, 2 is a micro program counter (MPC), 3 is a general-purpose register (GR register), 4 is an adder, 5 is a multiplexer, 6 is a control storage device (C3), and 7 is an OP 8 represents an inflator, and 9 represents a decoder.

In FIG. 1, a micro program counter changing circuit 1 (hereinafter referred to as an MPC changing circuit) 1 is related to the present invention, and as described later, it is possible to use hardware to perform high-speed processing, for example, as shown in FIG. Micro in the illustrated program
This is for jumping to address 300 or 400.

In the following sections, the configuration and operation will be briefly explained, and then the operation will be explained in detail using FIG.

Micro program counter (hereinafter referred to as MP) in Figure 1
The micro address stored in C) 2 is supplied to CS 6 via an adder 4 and a multiplexer 5;
The microinstruction read from the Bcs 6 is stored in the oP register 7.

The microinstructions stored in the OP register 7 are decoded by the decoder 9, and predetermined processing is executed. Also, a numerical value corresponding to the type of data specified by the illustrated tag consisting of 4 bits in the GR register 3 is supplied to the adder 4. As a result, the jump destination address of the multiway jump mentioned above is calculated,
That is, the value of the jump destination address stored in the MPC 2 and the value associated with the tag in the GR register 3 are added and supplied to the C 36 via the multiplexer 5. As a result, the microinstruction stored at the jump destination microaddress is stored in the OP register 7, and a predetermined process is executed.

The MPC change circuit 1 also uses iF? for determining the type stored in the data area of the GR register 3 in a form corresponding to a predetermined microinstruction supplied from the C56. Ii
i, for example, ``5HOPT'' in FIX or ``L
II information to determine whether it is “ON” or not “0” or “1°” and the jump destination micro
The address is supplied to C36 via multiplexer 5. As a result, it is possible to quickly jump to the micro address corresponding to FIX 5HORT or FIX LONG by a configuration using hardware, and control can be performed by using a small storage area (the tri area in the CSG). . Hereinafter, using the configuration shown in FIG. 1, a detailed explanation will be given of the operation when performing the same operation as a program written using the conventional multi-way jump instruction shown in FIG. 2. Here, GR register 3
The value "O" indicating the FI statement (fixed point number) is stored in the tag, and the type is FIX 5 next to the tag in the data area.
Assume that "0" indicating IIORT is stored.

The first step is the microinstruction GR-DATA stored at microaddress 100.

Execute. As a result, the data representing FIX etc. will be changed to GR.
Stored in Registrar 3.

The second step is the multi-way jump microinstructions SQ and LITG stored at microaddress 101.

Execute. As a result, the micro address value “+02” stored in MPC2 and OR register 3
The value “0” associated with the tag FIX in adder 4
are respectively supplied and added.

The added micro address value "102" is supplied to C56 via multiplexer 5.

The third step is the microinstruction SQ, 8 To FIX stored at the microaddress 102 jumped in the second step.

is read out from the C36 and supplied to the MPC modification circuit 1 according to the present invention. In a manner corresponding to reading out the label "FIX" included in the supplied microinstruction,
The value “Oo” corresponding to the aforementioned “5HORT” stored in the data area of the GR register 3 is the MPC change circuit l.
supplied to As a result, the MPC change circuit 1 becomes F
A micro address 300 where a processing program corresponding to the IX 5HORT is stored is generated, and the micro address 300 is supplied to the CS 6 via the multiplexer 5. The micro address 300 is supplied to CS6 again within the same step (cycle), and conventionally it was processed in two cycles, but in this embodiment, it is processed in MPC change circuit 1, etc. Processing is performed in l steps (cycles) using hardware consisting of. For this reason, the previously described micro
The programs at addresses 200 and 201 are
It becomes unnecessary and the number of processing steps can be reduced.

The fourth step is to open the processing program for the microinstruction CFIX 5HOPT that has been extracted from the microaddress 300 that was supplied to the C36 in the third step.
Store in register 7. Then, the microinstruction stored in the 3ffQp register 7 is decoded by the decoder 9, and a predetermined process is executed.

As explained above, according to the configuration shown in FIG. 1, a microinstruction to perform a multi-way jump is stored at microaddress 300 in the third cycle (previously the fourth cycle) counting from microaddress 101 where the microinstruction is stored. You can run the FIX 5II ORT processing program. Similarly, the FIX LONG processing program stored at micro address 400 can also be executed in the third cycle (conventionally, the fifth cycle) counting from micro address 101.

It should be noted that all of the above steps can be fully executed during one machine cycle of the computer system.

As is clear from the examples explained above, according to the configuration illustrated in FIG. It is possible to jump to a jump destination where a processing program is stored and execute a processing program etc. corresponding to the type.

〔Effect of the invention〕

As explained above, according to the present invention, when performing processing in a form corresponding to the data type specified by the tag attached to the data, hardware is used to perform calculation processing corresponding to the data type. Since it uses a configuration that executes quickly and calculates the desired branch destination, even when the number of data types increases, the type can be quickly and flexibly determined and the branch can be made to the desired branch destination address. I can do it.

4. Explanation of the front vehicle on the UA side Fig. 1 is a configuration diagram of one embodiment of the present invention, and Fig. 2 shows an example of a conventional program for explaining the operation of the configuration of the I embodiment of the present invention shown in Fig. 1. .

In the figure, l is an MPC change circuit, 2 is an MPC (Physical Program Counter), 3 is a GR register, 4 is an adder, 5 is a multiplexer, 6 is a CS (control storage device), and 7
is an OP register, 8 is an inflator, and 9 is a decoder.

Claims (1)

[Claims] In an instruction control device that controls branching using a tag indicating the type of data attached to data, the value of the address stored in the program counter and the value associated with the tag are added. an adder for generating a branch destination address consisting of a value; and supplying the branch destination address generated by the adder to a control storage device, and in a form corresponding to a microinstruction read from the control storage device. and a micro program counter changing circuit that calculates a branch destination address based on information representing the type of data stored in the data, and the branch destination address calculated by the micro program counter changing circuit. An instruction control device characterized by controlling the microinstructions stored at addresses to be read from the control storage device and processed.