JP2629899B2 - Tag branching device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a tag branching device, in particular, a multi-directional branch by a data type in a computer system aiming at high-speed execution of an Al-oriented programming language represented by Lisp or Prolog. And a tag branching device.

[Conventional technology]

A feature of Al-oriented programming languages such as Lisp and Prolog is that the flow of control is determined at runtime. In these languages, there is no data type declaration, and any data type may be assigned to a variable. as a result,
In exchange for facilitating program creation, it is necessary to dynamically check the data type at the time of execution of the program and determine the processing contents, that is, the execution order. Li
In general, machines that exclusively execute an Al-oriented programming language, such as an sp machine and a Prolog machine, are provided with birdware that speeds up such data type determination in order to improve the execution speed. One example is a tag branching device.

Tag branching is a function that changes the branch destination address in a branch instruction by using a special tag bit provided to express the data type in every word, and allows a processing routine according to the data type to be selected. It is. For this purpose, a conventional tag branching device stores a branch offset corresponding to a data type in a dedicated memory in advance, and gives a tag bit pattern of data to be checked as an address of the memory, thereby obtaining a data type. It is usual to dynamically change the branch destination by reading the branch offset information corresponding to the branch destination and adding or inserting this to the branch destination address.

[Problems to be solved by the invention]

While the above-described conventional tag branching method has been effective when the machine language (or micro) instruction cycle is relatively slow, recent advances in microprocessor technology,
In particular, when the instruction cycle time becomes several tens of nanoseconds due to the emergence of the RISC type processor, there is a problem that the process from reading the tag information in the register to reading the branch offset from the dedicated memory does not fit in one machine cycle. . In general, it is necessary to employ a pipeline control method in order to reduce a machine cycle, and if the conventional method requires an extra cycle to calculate a branch address, the pipeline will be disturbed. .

Further, the branch offset information itself may be usually 2 to 3 bits (corresponding to 4 to 8 direction branches), but a plurality of branch patterns are required. For example, if the tag bit is 6 bits,
Although 64 data types can be expressed, it is necessary to prepare several types, such as a branch pattern that divides these into numerical data and others, and a branch pattern that divides them into integers, floating-points, and others. As a result, the memory for storing the branch offset information stores, for example, eight types of patterns.
A length of 64 × 8 = 512 words is required, the size of the address decoding circuit becomes large, and the data read path becomes long. This also causes the reading of the branch offset to be delayed.

An object of the present invention is to solve such a drawback of the conventional method and to enable a pipeline control type computer system to generate a branch address corresponding to a data type in one machine cycle of an instruction decoding phase.

[Means for solving the problem]

A tag branch device of the present invention includes a tag register for storing tag information indicating a data type, a tag branch memory for storing a plurality of branch address information corresponding to the tag information, and an instruction register for storing a machine language instruction. Means for storing tag information in the tag register in an instruction decoding phase for requesting storage of tag information, and a program counter for holding a machine instruction address to be executed next; Means for reading the tag branch memory according to the tag information stored in the register; means for selecting one of a plurality of pieces of branch address information read from the tag branch memory; stored in the program counter Means for adding the branch offset of the branch instruction to the next instruction address, and the added instruction address Characterized in that the lower bits of the scan and a means for inserting the branch address information selected is read from the tag branch memory.

[Action]

First, prior to the branch instruction, the immediately preceding instruction instructs to store the tag bit field of the word whose data type is to be determined in the tag register. This designation method may be explicitly specified by a programmer, or may be automatically performed by hardware in parallel with data storage in a register or the like.

The branch instruction read into the instruction register is immediately decoded, and the branch offset included in the instruction is added to the program counter. On the other hand, when the tag information is set in the tag register at the end of the immediately preceding instruction decode phase, the tag branch memory is immediately read in the subsequent branch instruction decode phase, and in parallel with the generation of the branch address. A branch offset corresponding to the tag information is obtained. At the same time, a necessary branch offset is selected from the output data of the tag branch memory according to the branch pattern number included in the branch instruction. By the above operation,
The generation of the branch destination address corresponding to the data type is completed in the branch instruction decode phase, and the branch destination machine language instruction can be read in the branch instruction execution phase.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a hardware block diagram of a tag branching device implemented in a dedicated Al-oriented computer system according to one embodiment of the present invention. The system represents the data type for each word 6
This is a computer system with 40 bits per word, which has tag bits. In FIG. 1, 1 is a tag register for storing 6-bit tag information, and 2 is a 24-bit × 64-word tag branch memory capable of storing eight branch offsets (3 bits) corresponding to data types for each data type. 3, an instruction register for holding an instruction in the decode phase; 4, a program counter for holding the address of the next instruction to be executed; and 5, a tag with a branch pattern number specified by a branch instruction stored in the instruction register 3. The selector 6 selects one of the eight branch offsets output from the branch memory 2. The selector 6 adds the contents of the program counter 4 and the branch offset specified by the branch instruction stored in the instruction register 3 to determine the branch destination. The adder 7 calculates an absolute address. The adder 7 calculates the absolute address from the branch address calculated by the branch instruction stored in the instruction register 3. Selector for selecting to read a decree, 8 is a decoder for identifying the instruction stored in the instruction register 3 is tag branch instruction.

 Next, the operation of this embodiment will be described in detail.

FIG. 2 is a timing chart for explaining the operation of the present invention.

The computer system of the present embodiment is a computer of a pipeline control system that executes machine language instructions in three stages of instruction fetch, decode, and execution. Machine cycle
It is controlled by a two-phase clock in 50 nsec. In the decode phase, the instruction is decoded in the first half of the cycle, and in the latter half cycle, the register specified by the instruction operand is read in preparation for the execution phase. The method of directly specifying the tag information in the tag register 1 by a machine language instruction is employed.

First, in the instruction immediately before the branch instruction, the tag register 1
Is set, the 6-bit tag bit pattern is read from the necessary data bus in the latter half of the decode phase of this instruction, and is set in the tag register 1 at the start of the next machine cycle.

On the other hand, the branch instruction adds the program counter 4 and the branch offset included in the branch instruction in the first half of the decode phase to generate the base address of the branch destination. At the same time, the tag register 1 set by the previous instruction
Is supplied as an address to the tag branch memory 2, and branch offset information corresponding to the data type is read out collectively for eight patterns. The selector 5 operates according to the pattern number included in the branch instruction, and the branch offset corresponding to the pattern number is connected to the lower three bits of the branch destination base address generated by the adder 6. The selector 7 operates by decoding the branch instruction by the decoder 8, and
Finally, “value of program counter 4 + branch offset + tag branch offset” is selected as the next instruction fetch address.

The tag branch memory 2 has eight types of branch patterns combined into one word, so the number of words in the memory is the number of data types.
It has been reduced to 64 words.

〔The invention's effect〕

As described above, according to the present invention, the tag register is set by the instruction immediately before flowing in the pipeline, the tag branch memory is accessed in parallel with the calculation of the branch address when the branch instruction is decoded, and the tag branch memory is By storing a plurality of branch patterns in one word, the number of words in the tag branch memory is reduced to the number of data types, thereby increasing the speed of reading and making it possible to create a branch destination address in the machine language instruction decoding phase. At least, in the conventional method, tag branching requiring two machine cycles can be realized in one machine cycle. Multidirectional branching by data type is the most basic processing in an Al-oriented computer system, and the present invention has the effect of increasing execution speed and avoiding disturbance of pipeline control.

Further, the reduction in the number of words in the tag branch memory has the effect of reducing wiring delay when implementing VLSI, and the present invention is also effective in reducing the size of a computer system.

[Brief description of the drawings]

FIG. 1 is a hardware block diagram of a tag branching device according to one embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the present invention. 1 ... tag register, 2 ... tag branch memory, 3 ... instruction register, 4 ... program counter, 5 ... selector, 6 ... adder, 7 ... selector, 8 ... decoder.

Claims (1)

(57) [Claims] A tag register for storing tag information representing a data type; a tag branch memory for storing a plurality of branch address information corresponding to the tag information; an instruction register for storing a machine language instruction; A program counter for holding a machine language instruction address to be executed, means for storing tag information in the tag register in an instruction decode phase for requesting storage of tag information, and storing in the tag register in a branch instruction decode phase Means for reading the tag branch memory in accordance with the tag information being set, means for selecting one of a plurality of pieces of branch address information read from the tag branch memory, and a next instruction stored in the program counter Means for adding a branch offset of the branch instruction to the address, and a lower bit of the added instruction address. Tags drop device is characterized by providing a means for inserting the branch address information selected is read from the tag branch memory bets.