JPH0844563A - Microprocessor - Google Patents

Abstract

PURPOSE:To increase the operation speed of a microprocessor by holding an instruction in an instruction holding part corresponding to the operation part, where this instruction is processed, not to select a slot in the stage of decoding. CONSTITUTION:A flag generation part 4 decodes the instruction inputted from an external memory to discriminate the classification or the instruction. The instruction us read out from an instruction cache 2 into an instruction buffer 5 and is held there. The instruction, which is inputted from the external memory because being absent in the instruction cache 2, is inputted to the instruction buffer 5 after the flag is added by the flag generation part 4, and this instruction is held in the instruction cache 2. In this case, an instruction holding part selection part 6 discriminates the flag; and if the flag is '0', the instruction buffer 5 is selected, and the instruction is held in an instruction buffer A. If the flag is '1', the instruction holding part selection part 6 selects an instruction holding part B8, and the instruction is held in this part B8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor. In particular, the present invention relates to a microprocessor having a plurality of arithmetic units and capable of simultaneously executing a plurality of instructions in one clock cycle.

By simultaneously executing a plurality of instructions in a pipeline, it is possible to perform program processing at a higher speed than in the case where instructions are sequentially executed one by one. In order to execute a plurality of instructions simultaneously by pipeline processing, it is necessary to determine which arithmetic unit should execute the instruction and transfer the instruction to an appropriate pipeline (slot).

The present invention provides a microprocessor capable of efficiently determining to which slot of a pipeline an instruction is issued and efficiently transferring the instruction to the slot.

[0004]

2. Description of the Related Art FIG. 8 shows the structure of a conventional microprocessor for pipeline processing. 200 is a processor.

An input buffer 210 temporarily holds an instruction input from an external memory. 21
Reference numeral 1 is an instruction cache, which is a cache for holding instructions.

Reference numeral 212 is a data cache, which is a cache for holding data. An instruction buffer 213 is a buffer for inputting an instruction into a pipeline processing slot (slot 0, slot 1).

Reference numeral 214 denotes slot 0, which is for pipeline processing. 215 is slot 1,
It is for pipeline processing. 216 is a register file, which is input data (operand) of the arithmetic unit,
It is composed of a plurality of registers for temporarily holding the calculation result of the arithmetic unit.

Denoted at 220 and 221 are decoders for decoding instructions. Reference numeral 230 denotes an arithmetic unit 1 which performs arithmetic processing for slot 0. An arithmetic unit 2 231 performs arithmetic processing of slot 0.

Reference numeral 232 is an arithmetic unit 3 for performing arithmetic processing of slot 1. Numeral 233 is an arithmetic unit 4 for performing arithmetic processing of slot 1. The operation of the configuration of the conventional microprocessor shown in FIG. 8 will be described.

Instructions are supplied from the instruction buffer 213 to the decoders 220 and 221 every two instructions in one cycle.
If there is an instruction in the instruction buffer, the instruction is read from the instruction buffer, and each decoder 220 in slot 0 and slot 1
221. Assuming that the word length of one instruction is 4 bytes, writing and reading of 213 in the instruction buffer are performed in units of 8 bytes. The unit for writing and reading to the instruction cache 211 is also 8 bytes.

When there is no instruction in the instruction buffer 213, the instruction is read from the instruction cache 211 and written in the instruction buffer 213 (instruction fetch). Then, the instruction in the instruction buffer 213 is input to slot 0 or slot 1 and interpreted by the decoders 220 and 221.
In the decode stage, data dependency between instructions and competition of resources such as arithmetic units are checked, and if there is competition, the start of calculation is made to wait until it is resolved. The decoded instructions are processed according to each instruction (operation unit 1, operation unit 2,
It is calculated by the arithmetic unit 3 and the arithmetic unit 4). Input operands for performing operations are read from the register file 216 in parallel with decoding.

When the instruction does not exist in the instruction cache 211, the instruction read from the external memory of the microprocessor 200 is written in the instruction buffer 213 and also in the instruction cache 211. The flow after the instruction moves to the arithmetic stage (the arithmetic unit 1, the arithmetic unit 2, the arithmetic unit 3, the arithmetic unit 4) differs depending on the instruction.
When the operation is an arithmetic operation or a logical operation, the operation ends in one cycle, and the result is the register file 21 after three cycles.
Written in 6. If the instruction is a load instruction, calculate the address to access the memory in the operation execution stage,
The data cache is read in the next cache stage. Exception processing is performed in the next stage (for example, processing for detecting whether an access-prohibited address is not requested, etc.), and the register contents are updated in the next stage.

In FIG. 8, the arithmetic unit 1, the arithmetic unit 2, the arithmetic unit 3, and the arithmetic unit 4 are assumed to perform arithmetic operations of different functions. In other words, the same type of operation cannot be executed simultaneously by two instructions. The instruction in slot 0 cannot use the arithmetic unit on the side of slot 1. Similarly, the instruction in slot 1 cannot be used in slot 0. These are to avoid complicated wiring due to an increase in wirings and multiplexers between slots.

Normally, when the instruction is transferred from the instruction cache 211 to the buffer 213, the fetched 8-byte lower instruction is contained in the slot 0 and the upper instruction is contained in the slot 1. Each computing unit (230,
231, 232, 233) has the above limitation, it is necessary to detect which arithmetic unit the instruction uses and select an appropriate slot. If it is in a different slot than the one you are using, you will need to replace the instruction slot. This replacement must be performed during the time (decoding stage) until the instructions are read from the instruction buffer, decoded, and passed to the arithmetic unit.

[0015]

In the conventional microprocessor for pipeline processing, instruction slots are swapped in the decode stage. Since the decode stage performs instruction decoding, dependency check, register file read, and instruction issue determination, it is a stage that is likely to become a critical path (path with the largest operation delay) of the entire processor. is there. Determining which arithmetic unit an instruction uses in the decode stage and selecting an appropriate slot is a major factor that impedes high-speed operation of the microprocessor.

An object of the present invention is to speed up the microprocessor by not performing slot selection in the decode stage.

[0017]

According to the present invention, when an instruction is stored in the instruction cache from the outside of the chip, a flag indicating which slot the instruction uses is attached and the instruction cache is written together with the flag. Similarly, when writing the instruction read from the external memory to the instruction buffer, a flag is added and the instruction buffer and the instruction cache are written. Then, when writing to the instruction buffer, an appropriate slot is selected by looking at the flag of the instruction cache, and transfer control in the instruction buffer is performed by this slot flag. Enabled choice.

FIG. 1 shows the basic configuration of the present invention. FIG. 1 shows an example in which two slots are provided. In FIG. 1, 1 is a microprocessor.

Reference numeral 2 is an instruction cache. Reference numeral 3 is a flag holding unit of the instruction cache, which holds a flag for identifying a computing unit (slot) that computes an instruction.

A flag generator 4 generates a flag according to the type of instruction. An instruction buffer 5 holds an instruction read from an instruction cache or an external memory.

Reference numeral 6 denotes an instruction holding unit selection unit, which identifies the flag of the instruction and determines which of the instruction holding unit A and the instruction holding unit B should hold the instruction. 7
Is an instruction holding unit A for holding an instruction to be processed by the arithmetic unit A (slot 0).

An instruction holding unit B holds an instruction to be processed on the side of the arithmetic unit B (slot 1). An operation unit A (slot 0) 9 decodes an instruction input from the instruction holding unit A, inputs an operand from the register file 12 according to the decoding result, performs an operation, and outputs the operation result to the register star file 12. It is to be transferred.

Reference numeral 10 denotes an arithmetic unit B (slot 1),
An instruction input from the instruction holding unit B is decoded, an operand is input from the register file 12 according to the decoded result, an operation is performed, and the operation result is transferred to the register file 12.

Reference numeral 12 is a register file, which holds the data input from the data cache 13 or the calculation results of the arithmetic units A and B. A data cache 13 holds data.

[0025]

The operation of the basic configuration of the present invention shown in FIG. 1 will be described. The flag generator 4 decodes the instruction input from the external memory and determines the instruction type. Then, a flag is generated for identifying whether the instruction is to be processed by the arithmetic unit A or the arithmetic unit B. For example, the instruction processed by the arithmetic unit A is "0", the instruction processed by the arithmetic unit B is "1", and the like.

Instructions are read from the instruction cache 2 and held in the instruction buffer 5. Alternatively, if there is no instruction in the instruction cache 2, the instruction input from the external memory is flagged by the flag generation unit 4 and input to the instruction buffer 5, and is also held in the instruction cache 2. At that time, the instruction holding unit selection unit 6 identifies the flag, and, for example,
If the flag is "0", the instruction buffer 5 is selected and the instruction is held in the instruction buffer A. Alternatively, if the flag is "1", the instruction holding unit selection unit 6 selects the instruction holding unit B and holds the instruction in the instruction holding unit B. The register file 12 takes out the data as an operand from the data cache 13 and holds it.

The instruction of the instruction holding unit A is input to the arithmetic unit A, and the input instruction is decoded. And the arithmetic unit A
Takes the necessary operands from the register file 12 and performs an operation, and stores the operation result in the register file 12. Similarly, the instruction of the instruction holding unit B is input to the arithmetic unit B, and the input instruction is decoded. Then, the calculation unit B
Calculates the necessary operands from the register file 12. Then, the calculation result is held in the register file 12. The calculation result held in the register file 12 is transferred to the data cache 13 and output to the external memory.

According to the present invention, slot selection is not performed in the decode stages of the arithmetic units A and B, which greatly affects the processing speed of the microprocessor. Therefore, since the processing is not delayed in the decoding stage, the pipeline processing can be efficiently performed, and the operation of the entire microprocessor is speeded up. Also, the instruction processing of the instruction buffer can be easily controlled by the flag.

[0029]

FIG. 2 shows an embodiment of the present invention. In FIG. 2, reference numeral 51 is a microprocessor.

Reference numeral 52 is an instruction cache. 53 is a flag for identifying a slot. It is assumed that slot 0 is identified by the flag “0” and slot 1 is identified by the flag “1”.

Reference numeral 54 is a predecoder, which decodes an instruction from an external memory to obtain slot 0 or slot 1.
The flag is generated by identifying which of the two is the instruction to be operated (corresponding to the flag generation unit in FIG. 1).

Reference numeral 55 is an instruction buffer (details of the instruction buffer 55 will be described with reference to FIG. 4). Reference numeral 56 is an instruction holding unit selection unit. Reference numeral 57 is an instruction holding unit.

Numeral 59 is a slot 0, which is composed of a decoder, an arithmetic unit 1 and an arithmetic unit 2. A slot 1 is composed of a decoder, an arithmetic unit 3 and an arithmetic unit 4.

Reference numeral 62 is a register file. 63 is a data cache. An input buffer (external input register) 76 is a buffer for temporarily holding an instruction input from an external memory.

In slot 0, a decoder 70 decodes an instruction input to slot 0.

Reference numeral 72 denotes an arithmetic unit 1, which registers the register file 6 in accordance with the content of the instruction decoded by the decoder 70.
The operand is taken out from 2 and arithmetic processing is performed.
Reference numeral 73 denotes an arithmetic unit 2 which extracts an operand from the register file 62 and performs arithmetic processing according to the content of the instruction decoded by the decoder 70.

In slot 1, reference numeral 71 is a decoder which decodes an instruction input to slot 1.

Reference numeral 74 is an arithmetic unit 3, which registers the register file 6 in accordance with the contents of the instruction decoded by the decoder 71.
The operand is taken out from 2 and arithmetic processing is performed.
Reference numeral 75 denotes an arithmetic unit 4 which extracts an operand from the register file 62 and performs arithmetic processing according to the content of the instruction decoded by the decoder 71.

Reference numeral 80 is an example of the data structure of a flagged instruction. Instruction 0 is an instruction processed in slot 0 and has a flag for identifying slot 0. The instruction 1 is an instruction processed in the slot 1 and has a flag for identifying the slot 1.

If one line of the instruction cache 52 has a length of 32 bytes, 8 instructions can be stored. The flag is written when an instruction is fetched from the external memory.
The instruction read from the external memory is stored in the instruction cache 52.
Input buffer 76 (external input register) before writing to
Write once to. The flag is generated by the decoder 54 while the input buffer 76 is read and then written in the instruction cache 52. The timing at which the data to be written in the instruction cache 52 is needed is the latter half of the cycle. Since the flag generation ends faster than this, the decoding by the predecoder 54 does not cause the operation delay (this point will be described in detail in FIG. 3). Reading from the instruction cache 52 to the instruction buffer 55 is performed in the instruction fetch stage. In the instruction fetch stage, the instruction cache 52 is read and written in the instruction buffer 55. In the instruction buffer 55, the instruction flag is identified, and whether the instruction should be processed in the slot 0 or the slot 1 is identified by the instruction holding unit selection unit 56, and the slot 0 If it is an instruction to be operated in step 1, it is held in the slot 0 side of the instruction holding unit 57, or if it is an instruction to be operated in slot 1, it is held in the slot 1 side.

FIG. 3 is a time chart of flag generation of the present invention. The instruction read from the external memory is once held in the external input register (input buffer 76).

In the first cycle, first, an instruction is read from the input register 76 at the rising edge of the clock in the first cycle. Then, it is transferred in the chip (inside the microprocessor 51), predecoded by the predecoder 54, transferred in the chip in the latter half of the first cycle, and transferred to the instruction cache input register (instruction cache 52) at the entrance of the instruction cache 52. Are written to a register (not shown) that holds a temporary instruction for inputting the instruction. Here, it is also written in the instruction buffer 55.

In the second cycle, at the rising edge of the clock in the second cycle, the instruction is read from the input register of the instruction cache and written in the instruction cache 52.

FIG. 4 shows an embodiment of the instruction buffer of the present invention. In FIG. 4, reference numeral 52 is an instruction cache. The instruction cache holds 4-byte instructions in 8-byte units. The 8-byte LSW (lower) side instruction (instruction 0) and the MSW (upper side) instruction (instruction 1) are respectively provided with flags for identifying slots.

An instruction buffer 55 has seven instruction holding units (instruction holding units T, P0, P1, F0, F1, D).
0, D1). A command is a sequence of commands,
It is selectively held in the instruction holding unit according to a selection rule in consideration of flags. The selection rule will be described later.

Reference numeral 85 is an instruction holding unit selecting unit 1 which refers to the flag of the instruction fetched from the instruction cache 52 or the instruction holding unit T and selects the instruction holding unit P0 or P1 according to the selection rule.

Reference numeral 86 is an instruction holding unit selection unit 2, which includes the instruction cache 52, the instruction holding unit P0 or the instruction holding unit P.
The instruction holding unit F0 or F1 is selected according to the selection rule by referring to the flag of the instruction fetched from 1.

Reference numeral 87 is an instruction holding unit selection unit 3, which includes the instruction cache 52, the instruction holding unit F0 or the instruction holding unit F.
The instruction holding unit D0 or D1 is selected according to the selection rule by referring to the flag of the instruction fetched from 1.

Reference numeral 90 designates a selector 0 for selecting an instruction held in P0. Reference numeral 91 is a selector 1 for selecting an instruction held in P1. Reference numeral 92 is a selector 2 for selecting an instruction held in F0.

Reference numeral 93 is a selector 3 for selecting an instruction held in F1. Reference numeral 94 is a selector 4 for selecting an instruction held in D0. Reference numeral 95 denotes a selector 5 for selecting an instruction held in D1.

Reference numeral T denotes an instruction holding unit, which holds the upper 4 bytes of the instruction in the instruction cache 52. P0 is an instruction holding unit, which holds the instruction selected by the selector 0 (90).

P1 is an instruction holding unit, which is a selector 1
It holds the instruction selected in (91). F0
Is an instruction holding unit, which holds the instruction selected by the selector 2 (92).

F1 is an instruction holding unit, which is a selector 3
It holds the instruction selected in (93). D0
Is an instruction holding unit, which holds the instruction selected by the selector 4 (94).

D1 is an instruction holding unit, and the selector 5
It holds the instruction selected in (95). FIG.
In the above configuration, the contents and flags of the instruction holding unit T, the instruction cache LSW (instruction 0), and the MSW (instruction 1) are input to the selector 0 (90), and any of these instructions is selected according to the flag and the selection rule. Or select. Then, the selected instruction 0 is held in P0. Similarly, the selector 1 (91) has an instruction holding unit T and an instruction cache 52.
The contents of the LSW and MSW of the instruction and the flag are input, selected according to the flag and the selection rule, and held in P1.

The selector 2 (92) receives the contents of the instruction holding unit P0, the LSW and MSW of the instruction cache 52 and their flags, and according to the flags and the selection rules.
One of them is selected and held in the instruction holding unit F0. Similarly, the selector 3 (93) receives the contents of the instruction holding unit P1 and the LSW and MSW of the instruction cache 52 and the flags, and the instruction is selected and held in the instruction holding unit F1 according to the flag and the selection rule.

The selector 4 (94) also receives the instruction holding unit F0, the contents of the LSW and MSW of the instruction cache 52 and the flags, selects the instruction according to the flag and the selection rule, and holds it in the instruction holding unit D0. To be done. Similarly, the selector 5 (95) receives the contents of the instruction holding unit F1 and the LSW and MSW of the instruction cache 52 and the flags, selects the instruction according to the flag and the selection rule, and holds it in the instruction holding unit D1.

The contents of D0 are transferred to slot 0 and D1
Is transferred to slot 1. Next, the instruction transfer rule in the configuration of FIG. 4 will be described. In the configuration of FIG. 4, each selection unit selects an instruction according to the following rule and transfers it to the selected holding unit.

(1) Two instructions are read from the cache
Do by instruction. (2) D0, F0, and P0 contain instructions executed by the group of arithmetic units in slot 0.

(3) D1, F1 and P1 contain instructions executed by the group of arithmetic units in slot 1. (4) If the read instruction is a pair of an instruction executed in slot 0 and an instruction executed in slot 1, (4)-
1 If the instruction buffer is empty, write to D0 and D1.

(4) -2 If an instruction exists in D0 and D1, write it in F0 and F1. (4) -3 Write to P0, T when an instruction exists in D0, D1, F0, F1.

(5) If both the read instructions are instructions to be executed in slot 0, (5) −1 If the instruction buffer is empty, write to D0 and F0. (5) -2 If an instruction exists in D0 and D1, write it in F0 and P0.

(5) -3 When an instruction exists in D0, D1, F0, F1, write it in P0, T. (6) If both read instructions are instructions to be executed in slot 1, (6) -1 If the instruction buffer is empty, D1,
Write to F1.

(6) -2 When an instruction exists in D0 and D1, write it in F1 and P1. (6) -3 D0, D1,
When an instruction exists in F0 and F1, write it in P1 and T.

(7) When an instruction is issued from D0, D1, the instruction existing in F0, F1, P0, P1, T is D
Move in the buffer so that it is packed in the direction of 0, D1. (8) Instructions that enter D0 and D1 at the same time must have consecutive addresses.

(9) Instructions that enter F0 and F1 at the same time must have consecutive addresses. (10) Instructions that enter P0 and P1 at the same time must have consecutive addresses.

The operation of the instruction buffer of FIG. 4 will be described based on an operation example (see FIGS. 5, 6 and 7). FIG. 5 is an example of an instruction sequence held in the instruction cache 52. Two instructions having a 4-byte structure are used as a processing unit for one cycle, and the MSW of the upper 4-byte of the 8-byte and the LSW of the lower 4-byte are each one instruction. Each has a flag for identifying the slot. Flag "0" is an instruction processed in slot 0, flag "1" is an instruction processed in slot "1" (add instruction executed in slot 0, load instruction executed in slot 1) From the instruction cache 52, two instructions or an upper byte (M) are provided for each clock cycle (hereinafter abbreviated as cycle).
SW) is read. Instructions written in the buffer (instruction holding unit) in the same cycle can be executed simultaneously. If the cycles written to the buffer are different, instructions whose instruction addresses are consecutive on a 4-byte boundary can be executed at the same time (for example, in the above instructions, load2 and add are added).
3, add4 and load3, etc.). Those that are not (for example, load2 and load4) cannot be executed simultaneously.

FIG. 6 shows an operation example 1. In cycle 1, add1 and load1 are read from the instruction cache 52, selected by the selector 4 (94) and the selector 5 (95), and written in D0 and D1. Here, an instruction for executing two instructions is issued (two instruction issuance).

In cycle 2, according to the issuance of two instructions,
d1 and load1 are output from D0 and D1 to slot 0 and slot 1, respectively. And newly load
2 and add2 are read from the instruction cache 52, selected by the selector 4 (94) and the selector 5 (95), and written in D0 and D1, respectively. Two instruction execution is issued here.

In cycle 3, according to the issuance of two instructions, lo
ad2 and add2 are output to slot 0 and slot 1, respectively. Then, add3 and add4 are newly read from the instruction cache 52. Both slots 0
, The selector 4 (94), the selector 2
It is selected in (92) and written in D0 and F0. Here, execution of one instruction is issued (one instruction issuance).

In cycle 4, add is issued according to the issuance of one instruction.
3 is output from D0 to slot 0, and selector 4 (9
Selected in 4), add4 moves from F0 to D0.
Here, the next instructions load3 and load4 are read from the instruction cache 52. Since the boundaries of load3 and add4 are continuous (the program counter values are continuous), they can be executed simultaneously. Therefore, load3 is selected by the selector 5 (95) and held in D1,
ad4 is selected by the selector 3 (93) and held in F1. Here, two instruction execution is issued.

In cycle 5, two instructions are issued to load
3 and add4 are output to slot 0 and slot 1, respectively. Then, it is selected by the selector 5 (95) and
ad4 moves from F1 to D1, and loads 5 and 5 are newly read from the instruction cache 52. Since load4 and add5 of D1 cannot be executed at the same time, add5 is selected by the selector 2 (92) and F0 is added.
, And load5 is selected by the selector 3 (93) and written in F1. Here, one instruction execution is issued.

In cycle 6, one instruction is issued to load
4 is output from D1 to slot 1, load5, ad
d5 is selector 5 (95) and selector 4 (9
It is selected in 4) and moves to D1 and D0. Load6 and load6 are newly read from the instruction cache 52, and the selector 3 (93) and the selector 2 (92) are respectively read.
Is selected and written in F1 and F0. Here, execution of two instructions is issued and loa is executed in the next cycle (not shown).
d5 and add5 are output.

FIG. 7 shows an operation example 2. The description of the selector selection process is omitted below. In cycle 1, add1 and load1 are read from the instruction cache, and D
It is written to 0 and D1. Here, it is assumed that 0 instruction is issued and no two instructions are executed in the next cycle.

In cycle 2, add1 and load1 are D0
And held at D1. Then, the next instruction (load2 and add2) is read from the instruction cache 52, and F1
And held at F0. It is assumed that 0 instructions are issued and no instructions are executed even in cycle 3.

In cycle 3, add3 and add4 are read from the instruction cache 52, the upper byte add4 is held in T, and the lower byte add3 is held in P0. Two instructions are issued in cycle 3.

In cycle 4, load1 and add1 are output from slot D1 and slot D0 to slot 1 and slot 0, respectively. And load2 and add2 are D1 and D, respectively.
Move to 0. add3 and add4 are F0 and P, respectively
Move to 0. New loa from the instruction cache 52
d3 and load5 are read. load3 is add
Since 4 and the boundary are continuous, it is written in P1, and loa
d4 is written to T. Two commands are issued here.

In cycle 5, according to the issuance of two instructions, lo
ad2 and add2 are output from D1 and D0 to slot 1 and slot 0, respectively. And add3, ad
d4 moves to D0 and P0, respectively. Also, load
3, load4 moves to F1 and P1, respectively. Here, since there is no room to read the next instructions load5 and add5, no new instruction is read. One command is issued here.

In cycle 6, according to the issuance of one instruction,
d3 is output from D0, and add4 moves to D0.
Then, load3 and load4 are D1 and F1, respectively.
Go to A new load from the instruction cache 52
5 and add5 are read and held in P1 and P0, respectively. Two commands are issued here.

In cycle 7, load3 and add4 are output from D0 and D1 to slot 1 and slot 0, respectively. Then, load4 moves to D1 and loads
5 and add5 move to F1 and F0, respectively. Load6 and add6 are read from the instruction cache 52,
It is held at P1 and P0 respectively. Here, one instruction is issued.

[0080]

According to the present invention, slot selection is not performed in the decode stages of the arithmetic units A and B, which greatly affects the processing speed of the microprocessor. Therefore, since the processing is not delayed in the decoding stage, the pipeline processing can be efficiently performed, and the operation of the entire microprocessor is speeded up. Also, the instruction processing of the instruction buffer can be easily controlled by the flag.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is a diagram showing an example of the present invention.

FIG. 3 is a diagram showing a time chart of flag generation of the present invention.

FIG. 4 is a diagram showing an embodiment of an instruction buffer of the present invention.

FIG. 5 is a diagram showing an example of instructions held in an instruction cache of the present invention.

FIG. 6 is a diagram showing an operation example 1 of the present invention.

FIG. 7 is a diagram showing a second operation example of the present invention.

FIG. 8 is a diagram showing a configuration of a conventional microprocessor.

[Explanation of symbols]

 1: Microprocessor 2: Instruction cache 3: Flag holding unit 4: Flag generation unit 5: Instruction buffer 6: Instruction holding unit selection unit 7: Instruction holding unit A 8: Instruction holding unit B 9: Arithmetic unit A 10: Arithmetic unit B 12: Register file 13: Data cache

Claims (1)

[Claims] 1. A microprocessor is provided with an instruction buffer for holding instructions for arithmetic processing and a plurality of arithmetic units for inputting instructions from the instruction buffer and performing arithmetic processing, and the instructions are processed in a microprocessor capable of simultaneously executing a plurality of instructions. The operation unit is defined, the instruction buffer includes an instruction holding unit corresponding to each operation unit, and a flag generation unit that generates a flag specifying the operation unit used by the instruction and adds the flag to the instruction. A command holding unit selecting unit that selects the command holding unit of the command buffer according to the flag, and holds the command in a command holding unit corresponding to an arithmetic unit that processes the command. And a microprocessor.