JP2636136B2 - Arithmetic processing device and arithmetic processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing device and an arithmetic processing method for processing instructions composed of a plurality of operation fields in parallel by using a plurality of arithmetic units to achieve high-speed arithmetic.

[0002]

2. Description of the Related Art As computers become more sophisticated, there is an increasing demand for faster arithmetic processing. For example, VLIW (VeW) is used to speed up the processing of microprograms and other various arithmetic programs.
ry Long Instruction Word). FIG. 2 shows a block diagram of a conventional VLIW arithmetic processing device. The illustrated device processes instruction 1 as shown. This instruction 1 is composed of an arithmetic unit control field 2 and a memory control field 3. The operation unit control field 2 is provided with, for example, four operation fields 4. In each of the operation fields 4, certain calculation operations op1 to op4 are set.

In this apparatus, an instruction register 5 receives this instruction 1 and performs an arithmetic operation. Instruction register 5 contains
Operation field holding units 5-1 to 5-4 and a memory control field holding unit 5-5 are provided. The operation field holding units 5-1 to 5-4 have arithmetic units 6-1 respectively.
To 6-4 are connected. These computing units 6-1 to 6
The output of -4 is sent to the connection network 7. The memory control field holding unit 5-5 is connected to the memory bank 8. This memory bank 8 is connected to the connection network 7. The arithmetic processing device as described above includes an instruction register 5
Are processed in parallel by arithmetic units 6-1 to 6-4 provided correspondingly. The processing result and the data stored in the memory bank 8 are mutually read and written by the connection network 7,
Used for subsequent processing.

The contents of each operation included in the instruction 1 as described above are designated by a programmer or a compiler. In other words, which operations are to be processed in parallel are all determined before the execution of this instruction. About the global behavior of the program,
Instructions are arranged so that the number of operations to be performed in parallel is increased as much as possible, using the knowledge obtained by the programmer or the information obtained by the compiler analyzing the operation of the program globally. For example, as another conventional method, a method has been proposed in which operations to be executed in parallel are determined each time the operation is performed. However, the VLIW method is different from such a method in that a processor such as an arithmetic unit is used. There is an advantage that the utilization efficiency of hardware resources can be improved. Other methods, such as deciding which operations should be processed in parallel at run time, require extracting data dependencies and performing complex controls.
In the VLIW method, such control is not required, and the hardware configuration can be simplified, and there is an advantage that the speed of execution of an instruction is increased.

[0005]

By the way, in the above-described VLIW system, the number of operation fields constituting an instruction is set in advance, and an arithmetic unit corresponding to this number is prepared. Therefore, if these arithmetic units are always fully used and parallel arithmetic is performed, the purpose of the initial high-speed processing can be achieved.
However, when an operation that can be processed in parallel is not found and the degree of parallelism is reduced, there is play in the operation unit control field, and some operation units do not operate, so that the bit usage efficiency of instructions is reduced. The degree of parallelism depends on the ability of the compiler and the like, and it is important to further enhance the ability to speed up the processing. SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and provides an arithmetic processing device and an arithmetic processing method in which the degree of parallelism of operations is increased, and the bit use efficiency of instructions and the use efficiency of hardware resources of a processor are improved. The purpose is to do so.

[0006]

According to a first aspect of the present invention, an instruction composed of a plurality of operation fields is processed in parallel by using a plurality of arithmetic units provided for each of the operation fields. For each field, a control subfield holding unit that stores information for determining the validity of the operation result of a subsequent instruction when a branch is taken by the preceding instruction and when a branch is not taken, and whether the branch is taken or not taken by the preceding instruction A branch flag holding unit for holding a branch flag indicating whether the branch flag and the validity determination information of each control subfield are received, and the operation result is calculated for each operation field of the subsequent instruction. And an invalidation signal generation unit that outputs information for determining whether to be valid or invalid.

A second invention is directed to a case where a series of instructions composed of a plurality of operation fields are processed in parallel by using a plurality of operation units provided for each of the operation fields, and even when a branch is taken. Even when the branch is not taken, if one or more instructions ahead of the instruction that arrives after that include an invalid operation field, the invalid operation field of each of the instructions contains The present invention relates to an arithmetic processing method characterized by incorporating an effective operation field to reduce the number of instructions.

According to a third aspect of the present invention, in a case where a series of instructions composed of a plurality of operation fields are processed in parallel using a plurality of operation units provided for each of the operation fields, a pipeline provided in an operation unit is provided. In the stage, at the time of delayed branch processing of pre-reading an instruction to be processed subsequently, one or two or more instructions after the instruction to be executed in advance regardless of whether the branch is taken or not, The present invention relates to an arithmetic processing method characterized in that when an invalid operation field is included, the number of instructions is reduced by incorporating a valid operation field of another instruction into the invalid operation field of each instruction.

[0009]

The instruction is composed of a plurality of operation fields and a control subfield corresponding to each operation field. When an instruction including a branch operation is executed, the operation to be executed differs depending on whether the branch is taken or not afterwards. In this case, the operation result is
The selection is made based on the information in the control subfield and the contents of the flag indicating whether the branch is taken or not taken. As a result, the operation in the case where the branch is taken and the operation in the case where the branch is not taken can be included in one instruction and processed in parallel, and the number of instructions can be reduced.

The operation to be executed after the branch instruction is different between the case where the branch is taken and the case where the branch is not taken.
In each case, the instruction to be executed is reached. If a plurality of instructions immediately before this instruction include an invalid operation field in both cases where the branch is taken and not taken,
The effective operation field of the other instruction can be incorporated into the invalid operation field of one instruction to achieve parallelization. In the pipeline processing, stages such as instruction fetch, decode, and execution are provided, and delayed branch processing is performed in which a plurality of instructions to be subsequently processed are read in advance. In this case, before the branch is determined to be taken or not taken, there may be a case where an instruction immediately after the previously executed instruction contains an invalid operation field. Even in such a case, by including an invalid operation field of one instruction with a valid operation field of the other instruction, the processing can be parallelized and the number of instructions can be reduced.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the embodiments shown in the drawings. [First Invention] FIG. 1 is a block diagram showing an embodiment of an arithmetic processing unit according to the present invention. This apparatus includes an instruction register 20 for executing an instruction having a configuration as shown in the instruction 10. In the present invention, first, the configuration itself of an instruction employing the VLIW system is different from that of the conventional one. That is,
The instruction 10 is provided with four operation fields op1 to op4 for performing, for example, four types of operations in parallel. Control subfields F1 to F4 are provided for the operation fields op1 to op4, respectively. The control subfields F1 to F4 are, as described later in detail, corresponding operation fields op1 to op1.
Regarding the operation of op4, the validity determination information of the operation result when the branch is taken and when the branch is not taken is set.

The instruction register 20 has a control subfield for storing information for determining validity of the control subfields F1 to F4 in addition to the four operation field holding units 22-1 to 22-4. Holders 21-1 to 21-4
Is provided. Further, this apparatus is provided with a branch flag register 13 for monitoring the operation result of the branch operation of the preceding instruction when the instruction is executed, and holding a branch flag indicating whether the branch is taken or not taken. ing. The outputs of the branch flag register 13 and the outputs of the control subfield holding units 21-1 to 21-4 of the instruction register 20 correspond to the four corresponding invalidation signal generation units 11-1 to 11-4, respectively.
Is configured to be input.

On the other hand, the operation field holding units 22-1 and 22-2
The outputs of 2-4 are configured to be sent to the corresponding computing units 12-1 to 12-4. These computing units 12
Parallel processing of each operation is executed by -1 to 12-4. This parallel processing structure is the same as that of the conventional device. In the present invention, the invalidation signal generators 11-1 to 11-
4 are input to the control terminals of the calculators 12-1 to 12-4, respectively, and the determination information as to whether the calculation result is invalid or valid is supplied.

The above apparatus receives an instruction 10 composed of, for example, a branch operation, two arithmetic operations, and a memory operation in an instruction register 20, and converts each of the operations op1 to op4 to arithmetic units 12-1 to 12-. 4 simultaneously. Here, when the information indicating whether the branch is taken or not is generated by the execution of the branch operation, this is stored in the branch flag register 13. Each operation of the instruction stored thereafter in the instruction register 10 is processed in parallel by the computing units 12-1 to 12-4. At this time, the control subfield holding unit 21-
The validity determination information stored in 1 to 21-4 is supplied to the invalidation signal generators 11-1 to 11-4. Here, the branch flag output from the branch flag register 13 takes a certain logic, and the execution result executed by the corresponding computing units 12-1 to 12-4 determines whether the execution result is valid or invalid. Is supplied to each computing unit.

[0015] Thereby, for example, only the operation result necessary when the branch is taken or only the operation result necessary when the branch is not taken is selectively extracted from the parallel-processed operation as needed. And used for subsequent arithmetic processing. With the device having such a configuration, the number of operations that can be simultaneously included in the instruction 10 increases, and the degree of parallelism of program execution can be increased. The specific configuration of the command and the contents of the control subfield will be described using the second invention and the like.

[Second Invention] FIG. 3 is an explanatory view of the contents of the control subfield according to the second invention. When implementing the present invention, specifically, for example, the contents of the control subfield,
Defined as shown in this figure. For example, in this example, the control subfield is composed of 2-bit data.
If the content is “00”, it is undefined and “0”
In the case of "1", when control is transferred to this instruction by means other than branching, an instruction to execute the operation of this field is issued. Make this content.

The value of the control subfield is "10".
When the control is transferred to this instruction by branching, the operation of this field is executed. In other words, this indicates that when the branch is taken, the operation result of this operation field becomes valid. Finally,
When the value of the control subfield is "11", the operation of this field is always executed when control is transferred to this instruction. That is, the operation result of this operation field is valid regardless of whether the branch is taken or not taken.

The information for determining the validity of the control subfield is supplied to the invalidation signal generators 11-1 to 11-1 shown in FIG.
When input to 1-4, a logical operation is performed together with the branch flag output from the branch flag register 13 to obtain determination information as shown on the right side of FIG. That is, when the information for validity determination is “01”, “1” when the branch is taken, “0” when the branch is not taken, and when the branch is taken when the validity decision information is “10”. Is “0”, “1” when the branch is not taken, and “1” when the validity determination information is “11”.
It is "0" regardless of whether the branch is taken or not taken. If the determination information is “1”, the operation is invalidated,
In the case of “0”, the operation is valid. in this way,
If the judgment information is “1”, the computing units 12-1 to 12-1
The corresponding output of 2-4 is suppressed, and the output to the connection network 7 as shown in FIG. 2 is not performed. In the case of a memory operation, suppression of a memory operation signal and the like are performed.

FIG. 4 is an explanatory diagram of a series of instructions when the second invention is implemented. The second invention is carried out for instructions as shown in this figure, and the method of the present invention reduces the number of instructions as shown in FIG. The effect is enhanced.

FIG. 5 is an explanatory diagram of terms used in the embodiment of the method of the second invention shown in FIG. Each instruction shown in FIG.
The terms are as shown in FIG. That is,
Branch L1 if (cond1) shown in line number (1) of FIG.
An instruction that branches to L1 when the condition cond1 is satisfied, as shown in FIG.
1 and op2 are set as a branch operation of the instruction 10 and two types of operation operations, respectively, as shown in FIG. The “continue” in the line number (2) is an instruction to be executed when no branch is performed, and op3 and op4 are set as the operation.

The branch L2 of the next line number (3) is an instruction that unconditionally branches to L2. For this process,
In the conventional method, only the operation op5 is set, and the operation field of the other arithmetic operation indicated by the symbol in the figure is invalid. This is because there is no branching operation in the line number (1), and no instruction that can be processed in parallel is found in a normal method. Line numbers (4) and (6) represent processing instructions for L1 and L2, respectively. In addition,
As for the row number (5), no operation other than the operation op8 to be performed in parallel is found, so that one operation field is invalid as indicated by a triangle. Note that the execution order of such a series of instructions is A when the branch is taken. If the branch is not taken, the execution order is B. On the right side of FIG. 4, such an execution order is sequentially shown by numerals. The vertical axis indicates execution timing, and the instruction is executed for each line.

In the method according to the second invention, △ shown in FIG.
The operation of another valid operation field is incorporated in the invalid operation field as shown by the mark to reduce the number of instructions. Specifically, in this example, the operation op5 of the row number (3) shown in FIG. 4A and the operation op8 of the row number (5) are parallelized. In this case, regarding each operation, if the branch is taken, the operation op8 is valid, and if the branch is not taken, the operation op5 is valid. That is,
Either one is valid and the other does not require the operation result. Therefore, as shown in (b), the operation op5 and the operation op8 are parallelized in the line number (4), and the control subfield includes validity determination information (b) and (n). (B) is valid when the control subfield is "10" and control is transferred to this instruction by branching, as shown in FIG. Also, (n) indicates that this operation is valid when the control subfield is "01" and the branch is not taken, as shown in FIG.

As described above, when the method shown in FIG. 4A is compared with the method shown in FIG. 4B, after the branch processing, the method is executed immediately before the instruction shown in FIG. (A), the instructions of line numbers (3) and (5) are collectively parallelized to line number (4) as shown in (b) to eliminate invalid operation fields and reduce the processing speed. Improvement can be achieved. In this way, even if there are a plurality of instructions immediately before the instruction that always arrives after the branch processing, by providing the control subfield as long as there is an invalid operation field, it is possible to easily multiplex. Become.

[Third Invention] FIG. 6 is a block diagram of an apparatus for implementing the third invention. Generally, in this type of arithmetic processing device for executing a microprogram or the like, pipeline processing is performed in order to increase the processing speed. In this case, each of the computing units 12-1 to 12-4 as shown in FIG.
Fetches, decodes, and executes instructions, respectively.
It consists of multiple stages such as storing. Each instruction is prefetched, and when it is determined by execution of the branch operation whether the branch is taken or not taken, the next instruction has already been fetched. Therefore, it is not easy to parallelize the instructions as shown in the second invention by using the apparatus shown in FIG. 1 as it is.

FIG. 6 shows an example of an apparatus in which such a delayed branching process is performed. This device does not provide a control subfield in the instruction branch operation op1.
That is, in the delayed branch processing, the processing result is not selected for the branch operation itself. Therefore, a control subfield holding unit corresponding to the instruction register 20 is not provided.
The invalidation signal generator 11-1 is set so that a control signal "01" is always input as a signal for performing a logical operation together with the output of the branch flag register 13. The third invention is realized by making such a change to the device shown in FIG. In the case of the third embodiment, when a branch operation instruction is executed, the branch flag is set in the branch flag register 13 at the time of starting execution of an instruction immediately thereafter. If the branch is not taken, the branch flag is reset at the start of execution of the immediately following instruction.

FIG. 7 is an explanatory view of the contents of the control subfield according to the third invention. This format is made up of 2-bit validity determination information, like the format shown in FIG. However, in the third invention, when the instruction is configured by a branch operation, two arithmetic operations, and a memory operation, no validity determination information is added to the branch operation. If the content of the validity determination information is "01" and the instruction executed immediately before does not branch, the operation of this field is executed. Also, "1
In the case of "0", the operation of this field is executed when the instruction executed immediately before branches. In addition, when the validity determination information is "11", the instruction executed immediately before is executed. Regardless of whether or not the operation has branched, the content of this field is executed, etc. The correspondence with the content of the determination information is the same as that shown in FIG.
When the validity determination information is “01”, if the branch is taken, the operation is invalid, and if the branch is not taken, the operation is valid. The information for validity determination is “10”.
In the case of (1), it becomes valid if the branch is taken, and becomes invalid if the branch is not taken.

FIG. 8 is an explanatory diagram of a series of specific instructions embodying the third invention. These instructions are executed in order from the line numbers (1) to (7) at the timings shown in FIG. FIG. 8A shows a series of instructions executed by the conventional method, and FIG. 8B shows a series of instructions executed by the method of the present invention. In this embodiment, the four invalid operation fields indicated by a triangle in FIG. 7A are replaced with mutually valid operation fields, and two instructions are omitted by parallelization.

FIG. 9 is a diagram for explaining terms in the embodiment of the method of the third invention shown in FIG. Where branch or cont
The inue is the same as that already described with reference to FIG. 5, and a duplicate description will be omitted. However, the sequence of instructions in FIG. The processing shifts to the processing of the number (5). If the processing is not established, the line number (2)
Is executed. as a result,
As shown on the right side of (a), when the branch is taken, the execution order A is line numbers (1), (2), (5), (6),
This is the process (7). The execution order B when the branch is not taken is line numbers (1), (2), (3),
(4) and (7).

In the third aspect of the invention, invalid operation fields indicated by the triangles generated in the line numbers (2), (3) and (5) shown in FIG. In the case of the delayed branch processing, such an invalid operation field indicates whether an instruction to be executed in advance, that is, a line immediately following the instruction indicated by the line number (1), regardless of whether the branch is taken or not taken. An invalid operation field is likely to occur in an instruction such as a number (2), a line number (3), or a line number (5). Therefore, as shown in FIG. 2B, the operation op3 of the row number (3) and the row number (5)
Is parallelized with the operation op6. Further, the processing of the line number (2) is omitted by utilizing the control subfield. As a result, as shown in FIG. 8B, a series of instructions without an invalid operation field is completed.

Here, (n), (r), and (e) of row numbers (2) and (3) shown in (b) have control subfields of "01", "10", and "11", respectively. Is shown. When there is no designation, it is assumed that the control subfield is “01”. As a result, for example, in the operation op3 of the row number (2) shown in (b), when control is transferred to this instruction by means other than branching, the operation result of the operation becomes valid. Conversely, operation op6 of line number (2) is
When control is transferred to this instruction by branching, the operation result becomes valid. Therefore, the operations op3 and op3 of the row number (2)
6 means that one of them becomes valid depending on the control subfield and is used for the subsequent processing. Line number (3)
The same applies to the instruction shown in FIG. As a result of such selection being performed automatically, operations that have been processed by being included in separate instructions can now be collectively parallelized.

Incidentally, by such a delayed branch processing,
Instructions executed together in the case of execution order A, B, that is, FIG.
The instruction of line number (3) following the instruction of (2) shown in (a) has been multiplexed in the manner described above, but following this instruction of (3), there are several instructions, Even when there are invalid operation fields, parallelization can be performed in a similar manner.

FIG. 10 is a diagram illustrating a modification of the present invention.
According to the second and third inventions described above, for an instruction in which an invalid operation field has been present, the operation in the valid operation field of another instruction can be included in the invalid operation field. Here, the second invention and the third invention
The present invention differs from the present invention in the instruction to be subjected to the parallel processing. Therefore, if both inventions are implemented at the same time, the number of instructions in a more complicated program is reduced, and the speed of the arithmetic processing is increased by parallelization. The validity determination information in this case can have, for example, the contents shown in FIG.

That is, when the second invention and the third invention are implemented at the same time, the validity determination information is composed of 3 bits. For example, in the case of "001", control is transferred to this instruction by a method other than branching, and when the immediately preceding instruction does not branch, the operation of this field is executed. Similarly, the information for validity determination is “010”,
In the case of “011”, “100”, “101”, and “110”, the validity / invalidity of the operation of the corresponding field can be controlled by combining the conditions set in the second invention and the third invention, respectively.

The present invention is not limited to the above embodiment. In the above embodiment, the configuration of the instruction is configured by the branch operation, the two types of arithmetic operations, and the memory operation. However, the configuration of such an instruction may be freely changed, and a larger number of operation fields may be used. It is also possible to provide highly parallel operation processing. The hardware for processing the validity determination information provided in the control subfield and validating or invalidating the output of the arithmetic unit is not limited to the above-described configuration, but may be freely replaced with one having the same function. I don't mind.

[0035]

According to the arithmetic processing device and the arithmetic processing method of the present invention described above, when an instruction composed of a plurality of operation fields is processed in parallel by using a plurality of arithmetic units, each operation field is processed. Each time, the validity determination information indicating the validity of the operation result when the branch is taken and not taken by the instruction at the preceding stage is set, and the operation is performed based on the branch flag indicating whether the branch is taken or not taken. Since the device configuration is provided with an invalidation signal generation unit that validates or invalidates the operation result for each field, it is possible to parallelize operations that were previously processed separately and could not be parallelized, The processing speed is increased.

Also, in this case, both before the instruction that arrives when the branch is taken and when the branch is not taken,
By replacing an invalid operation field existing in one or more instructions with a valid operation field of another instruction, the number of effective instructions can be reduced. In addition, when the delayed branch processing is performed, both when the branch is taken and when it is not taken, 1
Alternatively, for two or more instructions, the operation field can be replaced with a valid operation field of another instruction to reduce the number of instructions. According to these methods, a programmer logically analyzes a program in advance, sets respective operation fields, and can also automatically generate validity determination information by a compiler.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an arithmetic processing unit according to the present invention.

FIG. 2 is a block diagram of a conventional VLIW arithmetic processing device.

FIG. 3 is an explanatory view of the contents of a control subfield according to the second invention.

FIG. 4 is an explanatory diagram of a series of instructions for implementing the method of the second invention.

FIG. 5 is an explanatory diagram of terms in an embodiment of the method of the second invention.

FIG. 6 is an apparatus block diagram for implementing a third invention.

FIG. 7 is an explanatory diagram of the contents of a control subfield according to the third invention.

FIG. 8 is an explanatory diagram of a series of instructions for implementing the method of the third invention.

FIG. 9 is an explanatory diagram of terms in an embodiment of the method of the third invention.

FIG. 10 is an explanatory view of a modification of the present invention.

[Explanation of symbols]

 Reference Signs List 10 Instructions 11-1 to 11-4 Invalidation signal generator 12-1 to 12-4 Operation unit 13 Branch flag register F1 to F4 Control subfield op1 to op4 Operation field 21-1 to 21-4 Control subfield holding unit 22-1 to 22-4 Operation field holding unit

Claims (3)

(57) [Claims] 1. An apparatus comprising: a plurality of operation units provided for each of the operation fields for processing instructions constituted by a plurality of operation fields in parallel; A control subfield holding unit that stores information for determining the validity of the operation result of the subsequent instruction when the branch is taken and when the branch is not taken, and a branch that holds a branch flag that indicates whether the branch is taken or not taken by the preceding instruction A flag holding unit, the branch flag, and the information for determining the validity of each control subfield are received, and for each operation field of the subsequent instruction, whether the operation result is valid or invalid is determined. An arithmetic processing device comprising: an invalidation signal generating unit that outputs determination information. 2. In a case where a series of instructions composed of a plurality of operation fields are processed in parallel using a plurality of operation units provided for each of the operation fields, the branch is not taken even if the branch is taken. In this case, if one or more instructions that can be executed before the instruction that is always executed include an invalid field, the invalid operation field is replaced with the valid operation field of another instruction. Performs batch parallelization of embedded instructions, and places the batch-parallelized instruction at the position of an instruction that is always executed even if the branch is taken or the branch is not taken,
In the instruction, an operation field that is executed only when the branch is taken, an operation field that is executed only when the branch is not taken, and an operation field that is always executed both when the branch is taken and the branch is not taken And
An arithmetic processing method, wherein control is performed using the branch flag and the control subfield according to claim 1 to reduce the number of instructions. 3. In a case where a series of instructions composed of a plurality of operation fields are processed in parallel using a plurality of operation units provided for each of the operation fields, a pipeline stage provided in an operation unit includes: At the time of delayed branch processing in which an instruction to be processed is read in advance, an invalid field is included in one or more instructions that can be executed after an instruction executed in advance regardless of whether a branch is taken or not taken. If they are included, the effective operation fields of other instructions are embedded in these invalid operation fields, and the instructions are batch-parallelized. In the instruction, the operation field executed only when the branch is taken and the operation field executed only when the branch is not taken, and the branch is not taken when the branch is taken An operation field which is always executed even when the operation is turned on is controlled by using the branch flag and the control subfield according to claim 1, so that the number of instructions is reduced and a delay due to branching is not substantially generated. Arithmetic processing method.