JPH04124728A - Register index constitution system - Google Patents

Abstract

PURPOSE:To process the complicated address calculation at high speed by adding together the numerical values supplied from a register part and a numerical value generating part regardless of the instruction to be carried out and using the result of addition obtained from the analysis of an instruction code. CONSTITUTION:The numerical values supplied from a register part 1 and a numerical value generating part 2 are added together regardless of the instruction to be carried out for acquisition of the result of addition. This result of addition is used based on the analysis of an instruction code. That is, an address is previously calculated by supposing that a specific register is designated against a fact that an address is calculated with designation of a register included in the part 1 after the analysis of the instruction code. The result of this address calculation is used according to the analysis result of the instruction code. When the address is previously calculated, a specific register that is always working in the part 1 is used or the register undergone an access in the precedent time is selected. As a result, the complicated address calculation can be processed at high speed.

Description

[Detailed Description of the Invention] [Summary] Regarding a register index configuration method that uses register indexes to perform address calculations in a microcomputer chip, the present invention aims to process complex address calculations at high speed. This is a register index configuration method that performs address calculation using a register section,
An instruction to be executed, comprising a numerical value generating section, an adder for adding the outputs of the register section and the numerical value generating section, and a controller for using the output of the adder as an address calculation result according to an analysis result of an instruction code. Regardless of the above, the numerical values supplied from the register section and the numerical value generation section are added to calculate the result, and the calculated addition result is used according to the analysis of the instruction code.

[Industrial application field]

The present invention relates to a register index configuration method, and more particularly to a register index configuration method for performing address calculation using register indexes in a microcomputer chip.

In recent years, as computer systems have become more sophisticated and faster, there has been a demand for systems that can process complex address calculations at high speed.

[Conventional technology]

Conventionally, when calculating an address using a register index, a decoder analyzes the instruction code and adds the target register and offset according to that information.
After that, a memory read, etc. for this address was performed.

[Problem to be solved by the invention]

As mentioned above, address calculation using conventional register indexes is constrained by the time for address calculation in addition to the actual instruction processing time, resulting in a delay in operating speed. .

In other words, in the conventional register index configuration method, the address calculation unit is executed at the time when the instruction decode is finalized, so the address calculation included in one instruction code unit is one address calculation per one deco code unit. This is the limit. Further, even when a plurality of address calculation instructions are included in one decode unit in order to improve the processing speed of a microcomputer, there is no substantial advantage due to the above-mentioned limitations.

The present invention aims to process complex address calculations at high speed in view of the problems of the conventional register index configuration technology described above.

[Means to solve the problem]

FIG. 1 is a block diagram showing the principle of a register index configuration method according to the present invention.

According to the present invention, there is a register index configuration method that performs address calculation using a register index, and the register section l, the numerical value generating section 2, and the outputs of the register section 1 and the numerical value generating section 2 are added together. It is equipped with an adder 3 and a controller 4 that uses the output of the adder 3 as an address calculation result according to the analysis result of the instruction code, and is supplied from the register section 1 and the numerical value generation section 2 regardless of the instruction to be executed. There is provided a register index configuration method characterized in that a result is calculated by adding up numerical values, and the calculated addition result is used according to analysis of the instruction code.

[For production]

According to the register index configuration method of the present invention, regardless of the instruction to be executed, the register section 1 and the numerical value generation section 2
The result is calculated by adding the numbers supplied by . Then, the calculated addition result is used according to the analysis of the instruction code. In other words, instead of specifying a register in register section 1 and calculating the address after analyzing the instruction code, address calculation is performed in advance assuming that a specific register is specified, and then the instruction code is It is used as the address calculation result according to the analysis result. Here, when performing address calculation in advance, a specific register that is always operating in the register section 1 is used, or a register that was accessed last time is selected and used. .

This allows complex address calculations to be processed at high speed.

〔Example〕

Hereinafter, a register index configuration method according to the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the principle of a register index configuration method according to the present invention. In the figure, reference numeral 1 is a register section having a plurality of registers, which is also used to store an index for address calculation and normal address data. Further, reference numeral 2 is a numerical value generator, which outputs a constant or a set number in an instruction code depending on the situation, and reference numeral 3 is an adder, which generates a value in a register. It is used to add the calculated values. Reference numeral 4 is a controller that determines whether or not the addition result output from the adder 3 is applied to address calculation according to the result from the decoder.

According to the register index configuration method shown in FIG.
Normally, it is assumed that one specific register among the plurality of registers that a microcomputer chip has is always used for index reference in address calculation. For this index reference register, address calculation is always performed in advance, and when the instruction decoding by the instruction decoder is confirmed, the already calculated address (address calculation result of the index reference register) is used. It is supposed to be done.

Here, in the register index configuration method shown in FIG. 1, address calculation can be performed at high speed only when specific registers are used. By the way, in the conventional method in which the address calculation unit is executed when the instruction decode is finalized, as mentioned above, the address calculation included in one instruction code unit is limited to the ratio of one address calculation per one deco code unit. It is. Moreover, even when a plurality of address calculation instructions are included in one decode unit in order to increase the processing speed of a microcomputer, there is no real advantage due to this limitation. The configuration system of the present invention shown in FIG. It seems like the benefit is small because only the speed is increased. However, in actual programming, multiple registers do not appear on average in these address calculations, and there are cases in which one or two specific registers are used intensively, especially in register index address calculations etc. Since there are a large number of cases, it can be said that the effectiveness of speed improvement is extremely high. Furthermore, since this mechanism can be incorporated independently of the chip architecture, it can be said to be highly adaptable as a configuration method.

In this way, according to the register index configuration method shown in FIG. 1, complex address calculations can be processed at high speed.

FIG. 2 is a block diagram showing an example of the register section in FIG. 1. In the figure, a register section 1 is provided with a register selection circuit 5 in addition to a plurality of registers 10 to 1n. This register selection circuit 5 includes a register section 1
The register selection circuit selects the last accessed register from among the plurality of registers 10 to 1n that the register has, and the register selection circuit is provided with a previously used register storage means 51 for storing the last accessed register. That is, the previously used register storage means 51 stores accesses for instruction execution, address calculation, etc. to a plurality of registers 10 to 1n included in the register section 1, and selects a register to be used for address calculation according to the contents. It has become.

The register index configuration method shown in FIG. 2 takes into account the selection of a specific register in the configuration method shown in FIG. In other words, when calculating an address using a register index, there is usually a bias in how instructions are used. For example, the same register may be used intensively, or writing to a register used for register index may be There are some things that are done more frequently than registers. Therefore, the effect of the register index configuration method shown in FIG. 1 is increased by memorizing register accesses and changing the target specific register according to this memorization. According to the register index configuration method, address calculations, especially address calculations using registers as indexes, can be performed at high speed, and this greatly contributes to improving the functionality of microcomputers.

〔Effect of the invention〕

As described in detail above, according to the present invention, the result is calculated by adding the numerical values supplied from the register section and the numerical value generating section regardless of the instruction to be executed, and the calculated addition is performed according to the analysis of the instruction code. By using the results, complex address calculations can be processed quickly.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the principle of a register index configuration method according to the present invention, and FIG. 2 is a block diagram showing an example of the register section in FIG. 1. (Explanation of symbols) 1...Register section, 2...Numeric value generation section, 3...Adder, 4...Controller, 5...Register selection circuit, 10-1n...Register, 5I: Previously used register storage means.

Claims (1)

[Claims] 1. A register index configuration method for performing address calculation using a register index, which comprises a register section (1), a numerical value generating section (2), and a register section (1), a numerical value generating section (2), and a register section (1), a numerical value generating section (2), and An adder (3) that adds the outputs, and a controller (4) that uses the output of the adder as an address calculation result according to the analysis result of the instruction code,
A result is calculated by adding the numerical values supplied from the register section and the numerical value generating section regardless of the instruction to be executed, and the calculated addition result is used according to the analysis of the instruction code. register index configuration method. 2. The register index configuration method according to claim 1, wherein the register unit (1) includes a specific register that is always in operation, and the register is used exclusively. 3. The register section (1) includes a register selection circuit (5) that selects a previously accessed register from among a plurality of registers (10 to 1n) included in the register section. The register index configuration scheme described. 4. The register selection circuit (5) includes a previously used register storage means (51) for storing the last accessed register.
) The register index configuration method according to claim 3, comprising: 5. A microcomputer chip, characterized in that address calculation is performed by applying the register index configuration method according to any one of claims 1 to 4.