JPS6156597B2 - - Google Patents
Info
- Publication number
- JPS6156597B2 JPS6156597B2 JP55150623A JP15062380A JPS6156597B2 JP S6156597 B2 JPS6156597 B2 JP S6156597B2 JP 55150623 A JP55150623 A JP 55150623A JP 15062380 A JP15062380 A JP 15062380A JP S6156597 B2 JPS6156597 B2 JP S6156597B2
- Authority
- JP
- Japan
- Prior art keywords
- node
- mos transistor
- potential
- state
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Integrated Circuits (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55150623A JPS5774886A (en) | 1980-10-29 | 1980-10-29 | Semiconductor integrated circuit device |
| US06/313,994 US4490628A (en) | 1980-10-29 | 1981-10-22 | MOS Decoder selection circuit having a barrier transistor whose non-conduction period is unaffected by substrate potential disturbances |
| DE3142557A DE3142557C2 (de) | 1980-10-29 | 1981-10-27 | Integrierte Halbleiterschaltung |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55150623A JPS5774886A (en) | 1980-10-29 | 1980-10-29 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5774886A JPS5774886A (en) | 1982-05-11 |
| JPS6156597B2 true JPS6156597B2 (enExample) | 1986-12-03 |
Family
ID=15500904
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55150623A Granted JPS5774886A (en) | 1980-10-29 | 1980-10-29 | Semiconductor integrated circuit device |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US4490628A (enExample) |
| JP (1) | JPS5774886A (enExample) |
| DE (1) | DE3142557C2 (enExample) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61294695A (ja) * | 1985-06-20 | 1986-12-25 | Mitsubishi Electric Corp | 半導体集積回路装置 |
| JP4533821B2 (ja) * | 2005-08-16 | 2010-09-01 | パナソニック株式会社 | Mos型固体撮像装置 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3644904A (en) * | 1969-11-12 | 1972-02-22 | Gen Instrument Corp | Chip select circuit for multichip random access memory |
| US3795898A (en) * | 1972-11-03 | 1974-03-05 | Advanced Memory Syst | Random access read/write semiconductor memory |
| DE2557165C3 (de) * | 1975-12-18 | 1979-01-18 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Decoderschaltung und ihre Anordnung zur Integrierung auf einem Halbleiterbaustein |
| US4156938A (en) * | 1975-12-29 | 1979-05-29 | Mostek Corporation | MOSFET Memory chip with single decoder and bi-level interconnect lines |
| US4074237A (en) * | 1976-03-08 | 1978-02-14 | International Business Machines Corporation | Word line clamping circuit and decoder |
| US4042915A (en) * | 1976-04-15 | 1977-08-16 | National Semiconductor Corporation | MOS dynamic random access memory having an improved address decoder circuit |
| US4081699A (en) * | 1976-09-14 | 1978-03-28 | Mos Technology, Inc. | Depletion mode coupling device for a memory line driving circuit |
| DE2641693C2 (de) * | 1976-09-16 | 1978-11-16 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Decodierschaltung mit MOS-Transistoren |
| JPS5493335A (en) * | 1977-12-30 | 1979-07-24 | Fujitsu Ltd | Decoder circuit |
| JPS54122939A (en) * | 1978-03-16 | 1979-09-22 | Nec Corp | Decoder circuit |
| JPS55150623A (en) * | 1979-05-14 | 1980-11-22 | Sharp Corp | Receiving unit |
-
1980
- 1980-10-29 JP JP55150623A patent/JPS5774886A/ja active Granted
-
1981
- 1981-10-22 US US06/313,994 patent/US4490628A/en not_active Expired - Lifetime
- 1981-10-27 DE DE3142557A patent/DE3142557C2/de not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4490628A (en) | 1984-12-25 |
| DE3142557A1 (de) | 1982-08-12 |
| JPS5774886A (en) | 1982-05-11 |
| DE3142557C2 (de) | 1986-02-27 |
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