JPS6156594B2 - - Google Patents
Info
- Publication number
- JPS6156594B2 JPS6156594B2 JP56151702A JP15170281A JPS6156594B2 JP S6156594 B2 JPS6156594 B2 JP S6156594B2 JP 56151702 A JP56151702 A JP 56151702A JP 15170281 A JP15170281 A JP 15170281A JP S6156594 B2 JPS6156594 B2 JP S6156594B2
- Authority
- JP
- Japan
- Prior art keywords
- transfer gate
- circuit
- read
- mos
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
- G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Static Random-Access Memory (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56151702A JPS5853087A (ja) | 1981-09-25 | 1981-09-25 | レジスタの読出制御方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56151702A JPS5853087A (ja) | 1981-09-25 | 1981-09-25 | レジスタの読出制御方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5853087A JPS5853087A (ja) | 1983-03-29 |
| JPS6156594B2 true JPS6156594B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1986-12-03 |
Family
ID=15524393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56151702A Granted JPS5853087A (ja) | 1981-09-25 | 1981-09-25 | レジスタの読出制御方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5853087A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63197088A (ja) * | 1987-02-12 | 1988-08-15 | Matsushita Electric Ind Co Ltd | マルチポ−トメモリセル |
| US4833648A (en) * | 1987-07-02 | 1989-05-23 | Texas Instruments Incorporated | Multiport ram hybrid memory cell with fast write |
| JPH06290584A (ja) * | 1993-04-01 | 1994-10-18 | Nec Corp | 半導体記憶装置 |
-
1981
- 1981-09-25 JP JP56151702A patent/JPS5853087A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5853087A (ja) | 1983-03-29 |