JPS6153864B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a bipolar transistor, J-
This invention relates to a method for manufacturing a semiconductor device that constitutes a semiconductor element such as an FET transistor.

The present inventors have proposed the following method for manufacturing a semiconductor device including a bipolar transistor.

That is, as shown in FIG. 1A, an N-type single crystal semiconductor layer 11 made of, for example, N-type single crystal silicon is prepared in advance, and on the main surface of this layer 11, for example, SiO ₂ is deposited as shown in FIG. 1B. An insulating layer 12 consisting of, for example
An insulating layer 13 made of Si ₃ N ₄ and a polycrystalline semiconductor layer 14 made of polycrystalline silicon containing P-type impurities, for example.
are formed in that order.

Layer 14 is then etched to locally create a window 15 in layer 14, as shown in FIG. 1C, thereby exposing layer 13 through window 15.

Next, an etching process is performed on the layer 13 using the layer 14 with the window 15 as a mask.
3 and then an etching process to layer 12 to create windows in layer 12, in this case layer 1.
So-called side etching is applied to layer 2, and then layer 1
By the etching process for layer 3, layer 1 of layer 13
The etching process for layers 12 and 1 removes the areas facing into the side-etched windows drilled in layer 12, as shown in FIG. 1D.
Window 1 with side etching on the layer seen through 3
6 is formed and layer 11 is exposed through this window 16 and through window 15 of layer 14.

Next, a polycrystalline semiconductor layer 18 made of polycrystalline silicon containing a high concentration of P-type impurities is formed to continuously extend into the layer 14 and the windows 16 and 15, as shown in FIG. A layer 19 consisting of the covering layer 14 is formed.

Next, layer 19 is partially removed from its outer surface side by ion milling from vertically above layer 19, and layer 19 is formed on the inner circumferential surface of window 16 and layer 13 as shown in FIG. 1F. However, the layer 19 is not left on the bottom of the window 16 surrounded by the layer 19 left on the inner circumferential surface of the window 16, so that the layer 19 can be extended from the outside part inside the window 16 onto the insulating layer 13. , a polycrystalline semiconductor layer 20 is formed by the layer 19.

Next, layer 20 is etched to remove unwanted areas of layer 20 opposite window 16 in areas that extend over insulating layer 13, as shown in FIG. 1G.

Next, layer 20 is thermally oxidized to oxidize the outer surface of layer 20, that is, to insulate it, thereby forming insulating layer 21 as shown in FIG. 1H. In this case layer 11
The exposed region not covered by the layer 20 is also oxidized, that is, insulated, and an insulating layer 22 made of SiO ₂ is formed. On the other hand, since the insulating layer 21 is formed by insulating the surface side of the polycrystalline semiconductor layer, it is formed much thinner than the insulating layer 21. Furthermore, the P-type impurity contained in the layer 20 is introduced into the region where the layer 20 in the layer 11 is connected to the layer 11, resulting in P ⁺
A mold region 23 is formed.

Next, by etching the insulating layers 21 and 22, it was found that the insulating layer 22 is much thinner than the insulating layer 21, and that the insulating layer 21 contains impurities at a high concentration, whereas the insulating layer 22 does not contain such impurities. Therefore, by taking advantage of the fact that the insulating layer 22 is etched at a faster rate than the insulating layer 21, a part of the surface side of the insulating layer 21 is removed as shown in FIG. Remove.

Next, P-type impurity ions are added to the insulating layer 21 in the layer 11.
The insulation in layer 11 can be grown by ion implantation in the uncovered areas and followed by heat treatment, or by vapor deposition or solid phase diffusion, as shown in FIG. A P-type semiconductor region 2 extends slightly laterally on the main surface side of the region not covered by the layer 21 and is connected to the above-mentioned region 23.
4, its region 24 and the above-mentioned region 23
A region 25 consisting of the above-mentioned structure is formed with its outer edge portion extending under the above-mentioned insulating layer 12 in a continuous manner.

Next, a polycrystalline semiconductor layer made of polycrystalline silicon, for example, containing N-type impurities with high precision is formed in a continuous manner over the region 25 and the insulating layer 21, and then an N-type semiconductor layer is formed using this polycrystalline semiconductor layer as an impurity source. The insulating layer 2 is formed by diffusion treatment of type impurities to form an N-type semiconductor region 27 within the region 25 and its outer edge as shown in FIG. 1J.
The polycrystalline semiconductor layer is then formed under the polycrystalline semiconductor layer by etching the polycrystalline semiconductor layer to connect to the region 27 as shown in FIG.
A layer 28 made of a polycrystalline semiconductor layer that does not extend unnecessarily is formed on the side opposite to the upper region 27 side.

Next, a window 29 is formed in a region of the insulating layer 21 not facing the regions 25 and 27 by, for example, photoetching, as shown in FIG. 1K, and the polycrystalline semiconductor layer 2
0 is exposed through this window 29.

Next, a conductive layer is formed in a continuous manner on the layer 28, on the area of the layer 21 not covered by the layer 28, in the window 29, etc. by, for example, a vapor deposition method, and then by, for example, photo etching. Window 2 as shown in Figure 1L
electrode 30 and region 2 connected to layer 20 through 9;
An electrode 31 is formed on 7 to be connected via layer 28.

The above is an example of a method for manufacturing a semiconductor device proposed by the present inventors, and the semiconductor device shown in FIG. and 27, respectively, as collectors,
The base and emitter regions form an NPN bipolar transistor, and the layer 25
It is thus clear that the base region is led out via the layer 20 to the electrode 30 and thus the base electrode, and that the layer 27 and thus the emitter region is led out via the layer 28 to the electrode 31 and thus the emitter electrode. Further, according to such a semiconductor device, the area of the region 25 can be reduced because the electrode 30 serving as the base electrode of the bipolar transistor is connected to the polycrystalline semiconductor layer 20 which can extend beyond the region 25 serving as the base region. Therefore, the capacitance of the junction between the collector and base of the bipolar transistor can be reduced.
Therefore, a bipolar transistor can be made to exhibit good high frequency characteristics.

Further, since the insulating layer 21 is formed by insulating on the outer surface side of the polycrystalline semiconductor layer 20 obtained as described above in FIG. 1G, the region 25 of the insulating layer 21
It occupies a small area on the top.

Further, according to the manufacturing method described above, only one etching process using a long mask is required when forming the window 15 in the polycrystalline semiconductor layer 14 as described above in FIG. The structure of the transistor can be obtained easily and with high precision, and the structure of the transistor can be easily obtained with desired characteristics at a high yield. It has the following.

However, in the case of the above-described semiconductor device manufacturing method, the region 23 constituting the base region 25 is formed or must be formed with a higher concentration than the region 24; Thus, the region 27 forming the emitter region is formed in the layer 20 through only the thickness of the insulating layer 21.
Since this is obtained by introducing impurities into the layer 28 facing the region 28, the region 27 is unnecessarily connected to the region 24, resulting in a transistor having a low breakdown voltage between its emitter and base. Further, the insulating layer 21 has free ends in regions 25 and 27.
The insulating layer 21 protects the emitter-base junction by extending over the emitter-base junction formed between the layers, but impurities from the layer 20 are introduced into the insulating layer 21 when it is formed, so that the layer 21 absorbs moisture. This was not desirable in terms of the reliability of the protection of the bond mentioned above. Furthermore, the region 27 serving as the emitter region cannot be formed deeply considering that it also expands in the lateral direction when it is formed. Therefore, it is necessary to provide a layer 28, and the layer 28 is Since it is formed with a large area in the region 27, the overall structure becomes larger accordingly.

Therefore, the present invention aims to propose a new method for manufacturing a semiconductor device that constitutes a semiconductor element, which does not have the drawbacks of the method for manufacturing a semiconductor device described above in FIG. Probably.

First, an example of a method for manufacturing a semiconductor device in which a bipolar transistor is constructed will be described.As shown in FIG. 2A, for example, an N
A polycrystalline semiconductor layer 41 is prepared in advance, and a polycrystalline semiconductor layer 42 made of polycrystalline silicon, for example, is formed on this main surface as shown in FIG. As shown in FIG. C, a mask layer 43 made of Si ₃ N ₄ , for example, a mask layer 44 made of SiO ₂ , and a mask layer 45 made of Si ₃ N ₄ are formed in this order. In this case, assuming that the layer 43 contains an impurity such as boron, the layer 43 is made to have an impurity concentration distribution in the thickness direction, and the etching rate of the layer 43 during the etching process following the step shown in FIG. Place the upper side so that it is greater than the lower side.

Layer 45 is then etched as shown in FIG. 2D by a selective etching process known per se.
Then, by etching the layer 44 using the layer 46 as a mask, as shown in FIG. A mask layer 47 is formed by a region under the layer 46 which is to be sloped.

Next, an impurity introduction process is performed by, for example, boron ion implantation into the layers 43 and 46 from above.
As shown in FIG. 2F, the layer 46 has an impurity introduced thereinto, and the layer 48 seen from above the layer 43.
A layer 49 into which impurities are introduced by the shaded region and a mask layer 50 into which impurities are not introduced by the other regions of the layer 43 are formed, and then layers 48 and 49 are etched. Accordingly, the equal layers 48 and 4 are formed as shown in FIG. 2G.
Remove 9. In this case, the upper surface side of the unmasked area of layer 47 of layer 50 may be etched so that the thickness of that area is smaller than that of other areas.

Next, by thermal oxidation treatment using layer 50 as a mask for layers 42 and 41, layer 42 and 41 are heated as shown in FIG.
Areas not masked in layer 50 and layer 41
An insulating layer 51 is formed by thermal oxidation of the region under that region of the layer 42, and a layer 52 is formed by the region under the layer 50 of the layer 42.

Next, by etching layer 50 using layer 47 as a mask, a mask layer 53 is formed in the region of layer 50 below layer 47, as shown in FIG.

Next, as shown in FIG. 2J, layer 51, layer 52, etc.
3, a polycrystalline semiconductor layer 54 of, for example, polycrystalline silicon is formed which extends continuously over the unmasked regions, the outer surface of layer 53, and the outer surface of layer 47.

Next, the layers 54 and 52 are doped with P-type impurities, for example, by implanting boron ions from above, as shown in FIG. 2K.
2. Form layers 55 and 56 into which impurities are introduced in the region not shaded on the layer 47 when viewed from the side opposite to the layer 41 side, and layer 54 on the layer 47. In addition to forming a layer 57 into which impurities are introduced by a region of
and a layer 59 formed of a region other than 57, and then heat-treated as necessary to polycrystallize the layers 55 to 57 or further increase the polycrystallinity of the equal layers 55 to 57, and The impurities in layers 55 to 57 are re-diffused to form layers 55 to 57 as shown in FIG. 2L.
57 to form layers 55' to 57'.

Next, layers 58 and 59 are etched using layers 55' to 57' as masks, and as shown in FIG. and layer 5
A layer 60 is formed in the area under the layer 53 of 8. However, in this case layer 60 may be etched so that its outer surface is located slightly inward than the outer surface of layer 53.

Layer 47 is then removed, as shown in FIG. 2N, together with the overlying layer 57', and then the outer portion of layer 55' extends over layer 51, if desired, as shown in FIG. 2O. remove.

Next, the layers 55', 60, and 41 are thermally oxidized using the layer 53 as a mask, and as shown in FIG. an insulating layer having a portion 65b insulated by thermal oxidation of the outer surface and extending between the outer surface of the layer 55' and the outer surface of the layer 60 to a region between the layers 55' and 60 on the main surface of the layer 41; 65
At the same time, a P-type region 66 to be connected to the layer 55' is formed from a position on the outer edge of the layer 41 by introducing P-type impurities contained in the layer 55' from the main surface side of the layer 41. The insulating layer 51 is formed so as to be able to extend.

Next, by ion implantation processing through the layer 65 and the P-type impurity layer 65 from above the layer 53, and the layer 53 and the layer 60, as shown in FIG. A P-type region 67 that is shallower than the region 66 and connected to the inner surface of the region 60 and the region 66 is formed.

Next, as shown in FIG. 2R, the layer 53 is removed, and then a layer 68 into which the N-type impurity is introduced by the layer 60 is formed by an N-type impurity introduction treatment using the layer 65 as a mask, and then a heat treatment is performed. Then, as shown in FIG. 2S, an N-type region 69 is formed in a region of layer 67 below layer 68.

Next, as shown in FIG. An extendable metal wiring layer 72 is formed, so that layer 41 is a collector, layer 67 is a base region, layer 66 is a base extraction region, layer 69 is an emitter region,
A bipolar transistor is provided in which the layer 55' is a base electrode layer or wiring layer, the layer 68 is an emitter electrode layer or wiring layer, the layer 71 is a base metal wiring layer, and the layer 72 is an emitter metal wiring layer. obtain.

The embodiments of the method for manufacturing a semiconductor device according to the present invention have been clarified above, and as is clear from the above, according to the method for manufacturing a semiconductor device according to the present invention, multiple layers connected to the layer 69 as an emitter region can be formed. Since the crystalline semiconductor layer 68 is formed by so-called self-alignment, it can be easily obtained and formed in a sufficiently smaller area than the layer 28 described above in FIG. 1 corresponding to this layer 68. It is something that can be obtained. Furthermore, since the layer 68 does not extend over the insulating layer 65, it is possible to obtain a semiconductor device that can be flattened as a whole. Also, the N-type region 69
The semiconductor device described above in FIG. 1 can be formed without being connected to the P ⁺ type region 66, and the withstand voltage between the emitter and the base of the transistor is significantly improved compared to the case of FIG. 1. It does not have the disadvantages of the method of manufacturing the same, but has significant advantages and advantages.

Although the above description describes an example of the manufacturing method of a semiconductor device in which a bipolar transistor is configured, detailed explanation thereof is omitted, but the manufacturing method described above is shown in FIG. After the process in Figure 2 Q, the second
After the step of FIG. 3A, layer 53 is removed as shown in FIG. After forming the highly conductive region 69' of the mold, and at this time forming the region 68, as shown in FIG. 3C,
Metal wiring layers 71 and 72 are formed as described above with reference to FIG. It is also possible to construct a J-FET type transistor in which the region is used as a drain region, and in this case as well, the same characteristics as described above with reference to FIG. 2 can be obtained.

Furthermore, the above description is merely a small example of the present invention; for example, in the case described above in FIG. 2, layers 58 and 59 may be separated from each other as shown in FIG. layers 55' and 5
Although the case of forming layer 6' and layer 60 has been described,
By the same etching process, as shown in FIG. 4A,
forming a groove 80 in the side of the layer 58 on the layer 56'side;
After that, as shown in Figure 4 B and C, Figure 2 N and O
After that, the same bipolar transistor as shown in FIG. 2 or the same J-type transistor as shown in FIG.
It is also possible to form a FET type transistor.

Further, as shown in FIG. 2F, after obtaining layer 50, prior to thermal oxidation to obtain layer 51, layer 42 is
By etching the upper side of the unmasked areas of layer 50, layer 51 shown in FIG. 2H can be obtained with its top surface level reduced. The area 66 shown in FIG. 2P can also be obtained by forming the layer 65 and then performing a heat treatment.

Furthermore, the region 67 shown in FIG. 2Q can be obtained not only by a single impurity ion implantation process but also by a plurality of impurity ion implantation processes.

Further, although a detailed explanation will be omitted, a layer 68' corresponding to the layer 68 and a metal wiring layer 72' corresponding to the metal wiring layer 72 are formed as shown in FIG. However, the layer 68' is connected to the N ⁺ region 81 for the collector previously formed in the layer 41, and thus the layer 68' is used as the collector electrode or wiring layer, as described above in FIG. It is also possible to obtain a bipolar transistor of this type, and various other modifications may be made without departing from the spirit of the invention.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of the process of manufacturing a conventional semiconductor device, and FIG. 2 is a schematic cross-sectional view of successive steps of the process of manufacturing a semiconductor device according to the present invention. , FIG. 3, FIG. 4, and FIG. 5 are schematic cross-sectional views showing other examples of the present invention. In the figure, 41 is a semiconductor layer, 42, 52, 54, 5
8, 60, 68 are polycrystalline semiconductor layers, 43, 44,
45, 46, 47, 50, 53, 55', 56',
59 is a mask layer, 51 and 65 are insulating layers, 66 and 6
7 and 69 indicate areas, respectively.

Claims (1)

[Claims] 1. A step of forming a first polycrystalline semiconductor layer, a first mask layer, and a second mask layer in that order on the main surface of a semiconductor layer having a first conductivity type. , forming a third mask layer locally on the second mask layer, and performing a first etching process on the second mask layer using the third mask layer as a mask. forming a fourth mask layer by a region below the third mask layer of the second mask layer, the second mask layer having an outer surface inside the outer surface of the mask layer and the outer surface sloping upward and outward; and a second etching process on the first and third mask layers to remove areas of the first mask layer other than the area under the third mask layer, thereby etching the outer surface of the third mask layer. forming a fifth mask layer by a region under the third mask layer of the first mask layer having an outer surface at a position relative to the third mask layer and removing the third mask layer; The crystalline semiconductor layer and the semiconductor layer are subjected to a first thermal oxidation treatment using the fifth mask layer as a mask, so that the first A first insulating layer is formed by thermal oxidation of an area not masked by the polycrystalline semiconductor layer and the fifth mask layer of the semiconductor layer.
forming a second polycrystalline semiconductor layer using a region under the fifth mask layer of the polycrystalline semiconductor layer; and a third etching of the fifth mask layer using the fourth mask layer as a mask. forming a sixth mask layer by a region under the fourth mask layer of the fifth mask layer; A region not masked by the mask layer, an outer surface of the sixth mask layer, and the fourth mask layer.
forming a third polycrystalline semiconductor layer that can be connected and extended on the outer surface of the mask layer; The above-mentioned second
The fourth polycrystalline semiconductor layer in which the first impurity is not introduced by the region under the sixth mask layer
When the polycrystalline semiconductor layer and the second polycrystalline semiconductor layer are viewed from the side opposite to the semiconductor layer, there is a shadow in the region of the third polycrystalline semiconductor layer on the fourth mask layer. Areas that are not designated as
When this polycrystalline semiconductor layer is viewed from the side opposite to the semiconductor layer side, the first polycrystalline semiconductor layer is formed by the region of the third polycrystalline semiconductor layer that is not shaded on the fourth mask layer. a step of forming a fifth polycrystalline semiconductor layer into which impurities have been introduced; a step of removing the fourth mask layer from above the sixth mask layer; and a step of forming the fourth and fifth polycrystalline semiconductor layers. The second thermal oxidation treatment using the sixth mask layer as a mask insulates the insulated portion of the outer surface of the fifth polycrystalline semiconductor layer and the outer surface of the fourth polycrystalline semiconductor layer. the fourth and fifth polycrystalline semiconductor layers on the main surface of the semiconductor layer between the outer surface of the fifth polycrystalline semiconductor layer and the outer surface of the fourth polycrystalline semiconductor layer; The fifth polycrystal is formed by forming a second insulating layer extending in the region between the semiconductor layers and introducing the first impurity from the fifth polycrystalline semiconductor layer into the semiconductor layer from the main surface side thereof. forming a first semiconductor region having a first conductivity type to be connected to the semiconductor layer such that the first insulating layer extends from a position on the outer edge thereof; and the sixth mask layer. from above the fourth polycrystalline semiconductor layer;
The above fourth impurity introduction treatment using the impurity
forming a sixth polycrystalline semiconductor layer into which the second impurity is introduced by the polycrystalline semiconductor layer; a second semiconductor region having a second conductivity type to be connected to the sixth polycrystalline semiconductor layer by introducing a second impurity into the sixth polycrystalline semiconductor layer. 2 forming a first polycrystalline semiconductor layer, a first mask layer, and a second mask layer in that order on the main surface of a semiconductor layer having a first conductivity type; and the second mask. from the outer surface of the third mask layer by a step of locally forming a third mask layer on the second mask layer, and a first etching process using the third mask layer as a mask for the second mask layer. forming a fourth mask layer by a region under the third mask layer of the second mask layer having an outer surface on the inside and the outer surface slopes upwardly and outwardly; A second etching process is performed on the third mask layer to remove a region of the first mask layer other than the region under the third mask layer, and to remove an area corresponding to the outer surface of the third mask layer. forming a fifth mask layer by a region under the third mask layer of the first mask layer having side surfaces and removing the third mask layer; A first thermal oxidation treatment using the semiconductor layer and the fifth mask layer as a mask is performed to apply the first forming a first insulating layer by thermally oxidizing a region not masked by the polycrystalline semiconductor layer and the fifth mask layer of the semiconductor layer, and the fifth mask of the first polycrystalline semiconductor layer; a step of forming a second polycrystalline semiconductor layer according to a region of the layer; and a third etching process using the fourth mask layer as a mask for the fifth mask layer. a step of forming a sixth mask layer by a region under the mask layer of the first insulating layer, a region of the second polycrystalline semiconductor layer that is not masked by the sixth mask layer; The outer surface of the mask layer No. 6 and the fourth mask layer
forming a third polycrystalline semiconductor layer that can be connected and extended on the outer surface of the mask layer; By the impurity introduction treatment using the first impurity that gives a shape and the subsequent fourth etching treatment, the second polycrystalline semiconductor layer becomes the third polycrystalline semiconductor layer when viewed from the side opposite to the semiconductor layer side. The first impurity in which a groove having an inner inner surface is formed at a position corresponding to an outer edge of the sixth mask layer by a shadowed region of the polycrystalline semiconductor layer on the fourth mask layer. The fourth polycrystalline semiconductor layer in which no The fourth mask layer of the third polycrystalline semiconductor layer when viewed from the side opposite to the semiconductor layer side of the region on the layer that is not shaded and the third polycrystalline semiconductor layer. forming a fifth polycrystalline semiconductor layer into which the first impurity is introduced in an area that is not shaded in the upper region; and forming the fourth mask layer from above the sixth mask layer. The outer surface of the fifth polycrystalline semiconductor layer is insulated by the removing step and the second thermal oxidation treatment using the sixth mask layer as a mask for the fourth and fifth polycrystalline semiconductor layers. and an insulated part of the inner surface of the groove formed in the fourth polycrystalline semiconductor layer, and the outer surface of the fifth polycrystalline semiconductor layer and the fourth polycrystalline semiconductor layer. A second insulating layer extending to a region between the fourth and fifth polycrystalline semiconductor layers on the main surface of the semiconductor layer is formed between the outer surfaces, and the fifth insulating layer is formed in the semiconductor layer from the main surface side. A first semiconductor region having a first conductivity type to be connected to the fifth polycrystalline semiconductor layer by introducing the first impurity from the polycrystalline semiconductor layer is introduced into the first semiconductor region from a position on the outer edge thereof. a step of forming the insulating layer so as to extend it; a step of removing the sixth mask layer from above the fourth polycrystalline semiconductor layer; and a step of removing the sixth mask layer from above the fourth polycrystalline semiconductor layer; A second layer providing a second conductivity type using the insulating layer as a mask.
The above fourth impurity introduction treatment using the impurity
forming a sixth polycrystalline semiconductor layer into which the second impurity is introduced by the polycrystalline semiconductor layer; a second semiconductor region having a second conductivity type to be connected to the sixth polycrystalline semiconductor layer by introducing a second impurity into the sixth polycrystalline semiconductor layer.