JPS6151467B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory erase malfunction prevention device that can securely erase data.

Conventionally, display devices such as teletext receivers store received data once in a reading and writing device.
After that, the necessary portion of data is read out and displayed.

In this case, in order to change the displayed content, the content written in the read/write device is erased, and then data for new display is written.

However, when erasing data, data may remain unerased due to the influence of noise and the like.
If the data has been completely erased, nothing will be displayed on the display device, but if some data is left behind,
The remaining data is displayed on the display device, which is very annoying to the eyes.

An object of the present invention is to provide a memory erase malfunction prevention device that can completely erase data.

In order to achieve such an object, the present invention cyclically selects storage elements stored in a pattern memory, erases data stored in the storage elements sequentially over an address signal circulation period,
If unerased data occurs at this time, data erasing is continued for a period longer than the address signal circulation period from the time when the last unerased data occurs. The present invention will be described in detail below using drawings showing examples.

The figure is a block diagram showing one embodiment of the present invention. In the figure, reference numeral 1 denotes a pattern memory which houses a plurality of storage elements inside. When an address signal is supplied from an address counter 2 to an address signal input terminal 1a, this storage element receives the address signal. Only those corresponding to the indicated address are selected. The address signal supplied from the address counter 2 cyclically selects a storage element while changing every predetermined period, that is, every storage element designation period. The memory element selected by the address signal writes the data input signal supplied to the data input terminal 1c when the read/write signal is supplied to the read/write control terminal 1b. , when no signal is supplied to the read/write control terminal 1b, the data stored in the storage element is read out as a data output signal and sent out from the data output terminal 1d.

Reference numeral 3 denotes an output signal detector, which is composed of, for example, a mono-multivibrator, and detects a significant signal,
That is, when a "1" level signal is supplied, it sends out a detection signal that lasts longer than the address signal circulation period,
The start of the signal duration is updated each time a signal is applied to the input terminal.

Reference numeral 4 denotes an erase signal generator that generates an erase pulse that continues for approximately half the storage element designation cycle in synchronization with changes in the address signal.

Reference numeral 5 denotes a control circuit which, when the erase control signal is supplied to the erase control terminal 5a, outputs the erase signal supplied from the erase signal generator 4 to the input terminal 5b during the period in which the address signal circulates from that point onward. 5c
Output to. The control circuit 5 also has an erase control terminal 5.
The erasing pulse is also sent from the output terminal 5c while a signal is being supplied to the output terminal 5c and a detection signal from the output signal detector 3 is being supplied to the input terminal 5d.

Note that the erasure control terminal 5a of the control circuit 5 is continuously supplied with a "1" level signal during the erasure period of the pattern memory 1.

The operation of the device configured in this way is as follows. When a "1" level signal is supplied to the erase control terminal 5a of the control circuit 5, the timer ₅₁ generates an output for a period of the address signal circulation cycle, and the AND circuit ₅₂ outputs the erase signal for this period to the OR circuit 5. Send to ₃ . As a result, the erase signal is output from the OR circuit ₅₃ and supplied to the read/write control terminal 1b of the pattern memory 1 via the output terminal 5c.

At this time, since the address signal is being supplied to the address signal input terminal 1a of the pattern memory 1,
Data supplied from the data input terminal 1c is written into the memory element selected by the address signal among the memory elements housed inside the pattern memory 1. If the data at this time is erased data in which all bits are at the "0" level, the erased data will be written into the memory element selected by the address signal, and erasure will be performed. Since the erase signal from the erase signal generator 4 is generated in synchronization with the change in the address signal, the memory elements housed inside the pattern memory 1 are stored in the same manner as the address signal sequentially selects the memory elements. It is deleted each time.

In this case, as described above, the duration of the erase signal is approximately half of the storage element designation period, so after the duration of the erase signal has elapsed, no signal is supplied to the read/write control terminal 1b of the pattern memory 1. . Therefore, the pattern memory 1 reads data stored in the memory element, but since the address signal at this time still selects the erased memory element, the data is read from the erased memory element. The resulting data is sent to the data output terminal 1d. If the pattern memory 1 has been completely erased, all bits of the read data will be at the "0" level, but if the data in the memory element remains erased, the remaining data will be sent to the data output terminal 1d. Therefore, some bits of the signal supplied to the input terminal of the output signal detector 3 are in a significant state of "1" level. Therefore, the output signal detector 3 supplies an output signal that continues for a period longer than the address signal circulation period to the input terminal 5d of the control circuit 5.

The signal supplied to the input terminal 5d of the control circuit 5 is supplied to one input terminal of the AND gate ₅₄ , but during the erasing period, the "1" level signal is supplied to the erasing control terminal 5a. , and the other input terminal of AND gate ₅₄ is supplied with an erase signal via AND gate ₅₅ . As a result, the erase signal is output from the AND gate ₅₄ , and the erase signal is output from the AND gate 54.
₃ and the pattern memory 1 via the output terminal 5c.
is supplied to the read/write control terminal 1b of.

Therefore, when a signal is generated in the output signal detector 3, the AND gate ₅₄ of the control circuit 5 sends an erase signal to the OR gate ₅₃ , but while the timer ₅₁ is generating the signal, the AND gate 54 ₂ also sends an erase signal to the OR gate ₅₃ . These erase pulses are both supplied from the erase signal generator 4 and have the same phase, so the pattern memory 1
The effect is the same as if only one of the erasing signals were supplied. Therefore, the memory element selected by the address signal is erased during the period when the erase signal is supplied to the read/write control terminal 1b, and the memory element selected by the address signal is erased during the period when the erase signal is not supplied. The memory contents are read out. If there is data remaining in the storage element, the output signal detector 3 detects the remaining data and is reset, and from this point on, output is generated for a period longer than the address signal circulation cycle.

In this way, the memory elements selected by the address signal are sequentially erased, and when the erasure of the last selected memory element is completed, the timer ₅₁ of the control circuit 5
will no longer produce any output. However, if there is data remaining in the memory element, the AND gate ₅₄ is supplied with the signal from the output signal detector 3, so even after the AND gate ₅₂ no longer sends out the erase signal, the AND gate 54 receives the erase signal. Send out. This erase signal is supplied as long as the output signal detector 3 is generating the output signal, and erases the remaining data in the memory element selected by the address signal. At this time, if unerased data occurs again, the output signal detector 3 is reset from this point, and this operation is repeated until there is no unerased data in the storage element.

The output signal detector 3 stops generating an output signal when a period longer than the address signal circulation period has passed after detecting the last generated data remaining in the memory element, so the pattern memory 1 is supplied with an erase signal. It will no longer be done. As a result, the erasing operation of the pattern memory 1 is completed at this point, and the data stored in the storage element is completely erased.

Note that since the present invention relates to a malfunction prevention circuit, a description of write and read operations has been omitted, but when a signal is supplied to the erase control terminal 5a of the pulse switch 5, the output detector 3 After blocking the operation so as not to generate an output signal even if there is an output signal, if write data is supplied to the data input terminal 1c of the pattern memory 1, writing to the pattern memory 1 is performed, and the erasure control of the control circuit 5 is also performed. When the signal supplied to the terminal 5a is stopped, reading of the pattern memory 1 is performed.

As explained above, the memory erase malfunction prevention circuit according to the present invention cyclically selects the memory elements housed in the pattern memory, and sequentially erases data stored in the memory elements over the address signal circulation cycle. At this time, if data remains unerased, the erasing period is extended beyond the address signal circulation cycle from the last time when data remained unerased, so that the erased data is stored inside the pattern memory. The data stored in the stored memory element can be reliably erased.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of the present invention. 1...Pattern memory, 1a...Address signal input terminal, 1b...Read/write control terminal, 1c...
...Data input terminal, 1d...Data output terminal, 2
...Address counter, 3...Output signal detector,
4... Erasing signal generator, 5... Control circuit, 5a...
...Erase control terminal, 5b, 5d...Input terminal, 5c
...Output terminal.

Claims (1)

[Claims] 1 An address counter that generates an address signal, and when the address signal is supplied, the memory element at the address indicated by the address signal is selected, and when a read/write signal is supplied, a data input signal is sent to the memory element. a pattern memory that outputs the data stored in the storage element as a data output signal when a write, read/write signal is not supplied; and a detection that continues for a predetermined time or longer when the data output signal includes a significant signal. an output signal detector that generates a signal; and an erase signal generator that generates an erase signal that is generated synchronously with changes in the address signal and that lasts for half or approximately half the period during which one of the storage elements is selected. Then, the erase signal is supplied to the pattern memory as a read/write signal either when the erase control signal and the detection signal are being supplied, or during a period in which the address signal circulates from the time when the erase control signal is supplied. A memory erase malfunction prevention device equipped with a control circuit for controlling.