JPH0474240A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To effectively prevent the illicit copy of data by outputting another pieces of data in place of the normal data in accordance with a fact whether an input address is coincident with a specific one or not. CONSTITUTION:A specific address detection circuit 31 receives an address signal from an address buffer 13 and compares this signal with a specific address. The circuit 31 keeps a control signal T at 'O' before the coincidence secured between the address signal and the specific address and then at '1' after the coincidence secured between both. A data switching circuit 33 selects one of both data signals DS and AS inputted from a data detection circuit 20 and a pseudo random circuit 32 respectively based on the signal T sent from the circuit 31. In other words, the normal signal DS received from the circuit 20 is selected with the signal T equal to 'O'. Meanwhile the signal AS received from the circuit 32 is selected with the signal T equal to '1'. These selected signals DS and AS are sent to an output circuit 22. Therefore the data are never illicitly copied unless the specific address is recognized. So that the data can be protected.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a non-volatile semiconductor memory in which data can be written electrically, and in particular has a function to prevent unauthorized copying of data, etc. The present invention relates to a nonvolatile semiconductor memory provided with a nonvolatile semiconductor memory.

(Prior Art) Generally, a semiconductor memory is composed of a large number of memory cells, an address decoder for specifying the memory cells, and peripheral circuits such as an output circuit for outputting read data. In order to read data stored in a memory cell from such a semiconductor memory, an address is input, address specification is performed, and a memory cell is selected. Data rlJ and rOJ of the memory cell selected by the decoder are discriminated by a sense amplifier and output to the outside through an output circuit.

FIG. 6 is a block diagram showing the configuration of a conventional semiconductor memory device using nonvolatile memory elements as memory cells.

The chip enable control circuit 11 outputs internal chip enable signals CE* and CE* in response to a chip enable signal CE input from the outside.

The output enable/program control circuit 12 receives an output enable signal OE and a program signal P input from the outside.
Internal output enable signals OE*, OE* based on GM
and internal program signal PGM*, respectively.

The address buffer 13 receives the external address signal Add and the internal chip enable signal CE*.

CE* is input and signal CE* is "1".

When the CE bit is "0", an internal address signal corresponding to the external address signal Add is output.

The internal address signal output from address buffer 13 is input to row decoder 14 and column decoder 15. 20 The above internal chip enable signals CE* and CE* are also applied to the row decoder 14 and column decoder 15.
is input to the row decoder 14, and the signal CE* is "1".

When CE* is "0", the row line 17 of the memory cell array 16 is selectively driven in accordance with the internal address signal. Data is read from a plurality of memory cells (not shown) connected to the driven row line 17 in the memory cell array 16. This data is input to the column gate circuit 19 via the column line 18.

The column decoder 15 controls the operation of the column gate circuit 19 in accordance with the internal address signal when the signal CE* is "1" and CE* is "0". With this control,
The column gate circuit 19 selects n bits (m>n
).

The n-bit data selected by the column gate circuit 19 is input to the data detection circuit 20. Internal chip enable signals CE*, CE* and a reference potential vref from a reference potential generation circuit 21 are input to this data detection circuit 20. Then, the data detection circuit 20 receives the signal CE*,
It operates when CE* is activated, and detects data by comparing the data from the column gate circuit 19 with the base ill level Vrer. The data DS detected here is manually input to the output circuit 22.

On the other hand, internal output enable signals OE*, OE* output from the output enable/program control circuit 12, internal program signal PGM4=, and signals CE*, CE* from the chip enable control circuit 11 are input to the output control circuit 23. Ru.

This output control circuit 23 uses an internal output enable signal OE*
, OE* is detected and outputs pulse signals P and ρ having a predetermined pulse width. These pulse signals P and ρ are internal output enable signals OE*.

It is input to the output circuit 22 together with TiTN. The output circuit 22 is controlled by these pulse signals P, ρ and internal output enable signals OE*, OE*, and outputs multiple pins corresponding to the detection data DS from the data detection circuit 20.
The data D is output to the off-chip uL section.

By the way, the operating modes in a semiconductor memory consist of a program mode for writing data and a read mode for reading data.Furthermore, in the read mode, data is read from the memory cell array in response to an address signal, but it is not output to the outside. There are three types: an output disable mode, an active mode in which read data is output, and a standby mode in which no data is read.

FIG. 7 is an example of a flowchart of a high-speed program mode of an 8-bit CMO3EFROM, which is used for writing data.

First, in the state of V -6V, turn on the 12.5V pro cc
Applying the pp Durham voltage sets the high speed program mode. Set the address as the start address, and after inputting the address data, apply a 1ms single pulse to the chip enable input to program, and then read out the address data to see if programming is successful. If the program is not correctly programmed, a 1 ms program pulse is further applied, the program is confirmed, and this operation is repeated (up to 25 times) until the program is executed correctly.

If the set address is programmed correctly, add a program pulse with a pulse width three times the pulse width required for programming. When programming of data at the start address is completed, 1 is added to the address and programming of data at the next address is executed in the same manner, and the operations are sequentially executed up to the final address. After finishing the final address program, set to V, V-5V and read all addresses c
Issue cpp.

By the way, in conventional nonvolatile semiconductor devices, when copying data from one chip to data from another chip,
A widely used method is to sequentially read and copy all data from address 0 to the final address. For example, in the case of many commercially available writers, all the data of the chip that is to be copied is sequentially read from address 0, and it is sequentially stored in the memory device inside the writer. A method is used in which data is sequentially written to the chip on the copying side starting from address 0.

(Problems to be Solved by the Invention) In conventional electrically writable nonvolatile semiconductor memory, all data can be easily read by inputting a signal from the outside, so data cannot be easily copied. Therefore, problems such as unauthorized duplication of data and unauthorized logon to the host computer have become a problem.

Therefore, an object of the present invention is to effectively prevent such unauthorized copying of data.

[Structure of the invention]

(Means for Solving the Problems) The present invention includes a storage means for storing regular data, a reading means for reading regular data corresponding to an input address signal from the storage means, and a readout means for reading the regular data corresponding to an input address signal. data generation means for generating different data; specific address detection means for detecting whether the input address signal matches a predetermined specific address; data switching means for selecting one of the regular data read by the reading means and the data created by the data generation means; and an output for outputting the one data selected by the data switching means to the outside. It is characterized by having a means.

(Function) In the memory of the present invention, there may be cases where different data is output in place of the regular data, depending on whether the input address signal matches a predetermined specific address. For example, in the preferred embodiment, normal data is output before the input address matches a specific address;
After a match, different data that is not regular data is output.

Therefore, unless reading is performed without specifying a specific address, it is not possible to reliably read regular data.

(Embodiment) FIG. 1 shows the configuration of a semiconductor memory device according to an embodiment of the present invention. The difference between the device shown in FIG. 1 and the conventional device shown in FIG. 6 lies in the portion between the data detection circuit 20 and the output circuit 22. That is, in FIG. 1, the data detection circuit 2
0 and the output circuit 22 is a specific address detection circuit 3.
1. A pseudorandom circuit 32 and a data switching circuit 33 are provided.

The specific address detection circuit 31 receives the internal address signal output from the address buffer 13, compares it with a predetermined specific address, and holds the control signal T at "0" until the two match, and detects a match. After that, it is held at "1".

A pseudorandom circuit 32 generates a pseudorandom signal AS as a data signal. The data switching circuit 33 selects one of the data signals DS and AS input from the data detection circuit 20 and the pseudorandom circuit 32 according to the logical value of the control signal T from the specific address circuit 31, and selects one of the data signals DS and AS input from the data detection circuit 20 and the pseudorandom circuit 32, send to That is, when the control signal T is "0", that is, before a specific address is specified, the regular data signal DS from the data detection circuit 20 is selected, and the control signal T is "0".
1'', that is, after a specific address is specified, the pseudorandom signal AS from the pseudorandom circuit 32 is selected and sent to the output circuit 22.

FIG. 2 shows a specific circuit configuration of the data switching circuit 33. First, the N-channel MOS transistor NMO5I
The normal data signal DS from the data detection circuit 20 is input to the source of the N-channel MO3) transistor N.
A pseudo-random signal AS, which is a data signal from the pseudo-random circuit 32, is input to the source of the MO 52. The drains of these two transistors NMO3I and NMOS2 are commonly connected and input to the output circuit 22. The control signal T from the specific address detection circuit 31 specifies a specific address. Previously, it was ``0'', and when specified, it switches to ``1'' and remains at ``1'' thereafter. This control signal T enters the gate of the transistor NMOS2, and the signal T is inverted by the inverter I, and this inverted signal T enters the other transistor NMO3I. Control signal T
When is "0", that is, before a specific address is designated, the transistor NMO32 is turned off, the transistor NMO5I is turned on because the logic "1" is supplied to its gate, and the output circuit 22 receives the regular data signal DS. enters.

On the other hand, when the control signal T is "1", that is, after a specific address is designated, the transistor NMOS1 is turned off because the signal "0" is supplied to its gate, and conversely, the transistor NMO82 is turned on, and the output circuit 22 The pseudo-random signal AS generated by the pseudo-random circuit 32 is input into the .

The specific address detection circuit 31 is configured as shown in FIG. 3, for example. A specific address is set in the register RG in advance, and the input address signal and the set specific address are compared with the comparator CMP. If the input address is the same as the specific address, the NOR circuit A1 is All input signals are set to "0". Then, NOR
The output signal H of circuit A1 changes from "0" to "1", and N
Channel MO5) Transistor NMO54 turns on. When the transistor NMOS4 turns on, it remains "0" until then.
The control signal T of the inverter 11 . !
, , the control signal T is latched in the "1" state. As a result, before a specific address is specified, the signal T is "0".
”, and henceforth becomes rIJ. The specific address is 1
There is no need to set one, and more than one may be set.

FIG. 4 shows a specific example of the pseudo-random circuit 32.

This example is a composite of an address transition detection circuit (ATD circuit) 41, a pulse generation circuit (ring oscillator) 40, and a delay circuit 42, which are well known in semiconductor memory circuits.First, the output signal R of the ring oscillator 40 is and A
A NAND signal AR is generated with the output signal ATD of the TD circuit 41, and this is delayed by the delay circuit 42 to generate a pseudo-random signal AS as shown in FIG.

-EFRO is a popular non-volatile semiconductor memory
In M, the output is 8 bits or 16 bits. For example, in the case of an 8-bit configuration, if eight delay circuits shown in Fig. 4 are connected in parallel, each output is given to an 8-bit output circuit, and each delay time is set to be different, the 8-bit Pseudo-random data can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, there are cases in which reading of normal data becomes impossible depending on whether or not a predetermined specific address is specified. , the program must be set so as not to select a specific address. Therefore, unless a specific address is recognized, data cannot be illegally copied, contributing to data protection.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of a nonvolatile semiconductor memory according to the present invention, FIG. 2 is a circuit diagram of the data switching circuit shown in FIG. 1, and FIG. 3 is a specific data detection circuit shown in FIG. 1. A circuit diagram of the circuit, Fig. 4 is a circuit diagram of the pseudo-random circuit of Fig. 1, Fig. 5 is a timing chart showing the operation of the pseudo-random circuit of Fig. 4, and Fig. 6 is a configuration of a conventional nonvolatile semiconductor memory. FIG. 7 is a flowchart showing the general procedure of the high-speed program mode. 20... Data detection circuit, 22... Output circuit, 31
. . . Specific address detection circuit, 32 . . . Pseudo-random circuit, 33 . . . Data switching circuit.

Claims (1)

[Claims] 1. Storage means for storing regular data; reading means for reading regular data corresponding to an input address signal from the storage means; and creating data different from the regular data. data generation means; specific address detection means for detecting whether or not the input address signal matches a predetermined specific address; and data readout by the reading means in relation to the detection result of the specific address detection means. a semiconductor memory comprising: data switching means for selecting one of the normal data obtained by the data generation means and data produced by the data generation means; and output means for outputting the one data selected by the data switching means to the outside. . 2. The device according to claim 1, wherein the data switching means selects the read regular data before a match between the input address signal and a predetermined specific address is detected; A semiconductor memory characterized in that after a match is detected, data generated by the data generation means is selected.