JPS5854793A - Preventing device for memory erase malfunction - Google Patents

Abstract

PURPOSE:To surely erase data stored in a storage element, by prolonging the erase period over an address signal circulating period from the point of time when the non-erase data takes place finally. CONSTITUTION:When a signal is generated to an output signal detector 3, an AND gate 54 of a control circuit 5 transmits an erase signal to an OR gate 53 and when a timer 51 generates a signal, an AND gate 52 given an erase signal to the OR gate 53. Since this pulse is applied from an erase signal generator 4, it is equal to apply one erase signal to a memory 1. Thus, a storage element selected at an address signal is erased while the erase signal is applied to a readout/write control terminal. If there is data not erased in this storage element, the detector 3 detects the data and generates an output over a period more than the address signal circulating period. When the final erase is finished, the circuit stops the output.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory erase malfunction prevention device that can securely erase data.

Conventionally, display devices such as teletext receivers have stored received data once in a reading and writing device, and then read and display the necessary portion of the data.

In this case, in order to change the display contents, read and
- After erasing the contents written in the writing device, new data for display is written.

However, when erasing data, data may remain unerased 9 due to the influence of noise and the like.

If the erasure is complete, nothing will be displayed on the display device, but if some data is left behind, the remaining data will be displayed on the display device, causing a serious eyesore.

An object of the present invention is to provide a memory erase malfunction prevention device that can completely erase data.

In order to achieve these objectives, the present invention cyclically selects storage elements stored in a pattern memory, erases data stored in the storage elements sequentially over an address signal circulation period, and When unerased data occurs, erasing of data is continued for more than an address signal circulation cycle from the time when data remained unerased. The present invention will be described in detail below using drawings showing embodiments.

The figure is a block diagram showing one embodiment of the present invention.

In the figure, reference numeral 1 denotes a pattern memory, which houses a plurality of memory elements therein. When an address signal is supplied from an address counter 2 to an address signal input terminal 1a, this memory element receives the address signal. Only those who reside at the address represented by are selected. Then, the address signal supplied from the address counter 2 is transmitted for a predetermined period.
That is, the memory elements are cyclically selected while changing every memory element designation period. Of these memory elements, the one selected by the address signal writes the data input signal supplied to the data input terminal 1C when the read/write 1a-4+ is supplied to the read/write control terminal 1b. , when no signal is supplied to the read/write control terminal 1b, the data stored in the storage element is output as a data output signal n'jl) and sent from the data output terminal 1d.

Reference numeral 3 denotes an output signal detector, which is configured, for example, by a mono-multi-by-break, and when a significant signal, that is, an 11" level signal is supplied to the bits of the data output signal supplied to the input 91M, the address signal is circulated. Sends out a detection signal that lasts for a period or longer (-1) The start of the duration of that signal is updated each time (M) is supplied to the input terminal.

Reference numeral 4 denotes an erase signal generator that generates an erase pulse that continues for approximately half of the storage element designation cycle in synchronization with changes in the address signal.

Reference numeral 5 denotes a control circuit which, when the erase control signal is supplied to the erase control terminal 5a, controls the erase signal supplied from the erase signal generator 4 to the input terminal 5b during the period in which the address signal circulates from that point onwards. is output to output terminal 5C.

Further, the control circuit 5 sends out an erase pulse from the output terminal 5C even when a signal is being supplied to the erase control terminal 5a and during a period when the detection signal from the output signal detector 3 is being supplied to the input terminal 5d. .

Note that the erase control terminal 5a of the control circuit 5 is continuously supplied with a signal of level 11 during the erasing period of the pattern memory 1.

The operation of the device configured in this way is as follows. When a K'1 level signal is supplied to the erase control terminal 5a of the control circuit 5, the timer 51 generates an output for the period of the address signal circulation cycle, and the AND circuit 52 sends the erase signal for this period to the OR circuit 5s. As a result, the erase signal is output from the OR circuit 5s and supplied to the read/write control terminal 1b of the pattern memory 1 via the output terminal 5C.

At this time, address signal input terminal 1a of pattern memory 1
Since the address signal is supplied to 4-, the data supplied from the data input terminal 1C is written into the memory element selected by the address signal among the memory elements housed inside the pattern memory 1. .

If the data at this time is erased data in which all bits are at the "0" level, the erased data will be written into the memory element selected by the address signal, and erasure will be performed. Since the erase signal from the erase signal generator 4 is generated in synchronization with the change in the address signal, the memory elements housed inside the pattern memory 1 are stored in the same manner as the address signal sequentially selects the memory elements. It is deleted each time.

In this case, as described above, the duration of the erase signal is approximately half of the storage element designation period, so after the duration of the erase signal has elapsed, no signal is supplied to the read/write control terminal 1b of the pattern memory 1. .

Therefore, the pattern memory 1 reads data stored in the memory element, but since the address signal at this time still selects the erased memory element, the data is read from the erased memory element. The exposed data is sent to the data output terminal 1d.

If pattern memory 1 has been completely erased, all bits of the read data will be at the 10'' level, but if data in the storage element remains erased, the data output terminal 1d
Since the remaining data is output, there are ゝゝ1〃 in the bits of the signal supplied to the input terminal of the output signal detector 30.
There are various levels of significance. Therefore, the output signal detector 3 supplies the input terminal 5d of the control circuit 5 with an output signal that continues for a period longer than the address cycle period.

The signal supplied to the input terminal 5d of the control circuit 5 is supplied to one input terminal of the AND gate 54, but during the erasing period, since the signal at the level of the erasing control terminal 5aK'1 is supplied, the AND gate is An erase signal is supplied to the other input terminal of gate 54 via AND gate 56 . As a result, the erase signal is applied to the AND gate 5. Output from Fang Agate 5. and is supplied to the read/write control terminal 1b of the pattern memory 1 via the output terminal 5c.

Therefore, when a signal is generated in the output signal detector 3, the AND gate 54 of the control circuit 5 sends the erase signal to the OR gate 53.
However, while the timer 51 is generating the signal, the AND gate Ss is also sent to the OR gate 5. The erase signal is sent to Since both of these erase pulses are supplied from the erase signal generator 4 and have the same phase, they have the same effect on the pattern memory 1 as if only one erase signal had been supplied. Therefore, the memory element selected by the address signal is connected to the read/write control terminal 1 of the erase signal.
During the period when the erase signal b is supplied, erasure is performed, and during the period when the erase signal is not supplied, the storage contents of the same memory element are read. If there is data remaining in the storage element, the output signal detector 3 detects the remaining data and is reset, and from this point on output is generated for a period longer than the address signal circulation cycle.

In this way, the memory elements selected by the address signal are sequentially erased, and when the erasure of the last selected memory element is completed, the timer 51 of the control circuit 5 stops generating an output. However, if the memory element remains erased overnight, the AND gate 54 is supplied with the signal from the output signal detector 3, so the data is erased even after the AND gate 5m no longer sends out the erase signal. Send a signal. Then, this cancellation signal is sent to the output signal detector 3.
The address signal is supplied as long as the output signal is generated, and the remaining data of the memory element selected by the address signal is erased. At this time, the process is repeated until there is no remaining data.

The output signal detector 3 stops generating an output signal after a period longer than the cycle cycle of the address signal has elapsed after detecting the last generated unerased data of the memory element, so the pattern memory 1 is supplied with an erase signal. It will no longer be done. As a result, the erasing operation of pattern memory 1 is completed at this point,
The data stored in the memory element is completely erased.

Note that since the present invention relates to a malfunction prevention circuit, a description of write and read operations has been omitted. However, when a signal is supplied to the erase control terminal 5a of the pulse switch 5, the output detector 3 After blocking the operation so as not to generate an output signal even if there is a signal, if write data is supplied to the data input terminal 1C of the pattern memory 1, writing to the pattern memory 1 is performed, and the control circuit 5
If the signal being supplied to the erasure control terminal 5a of the pattern memory 1 is stopped, the pattern memory 1 is continuously read out.

As explained above, the memory erase malfunction prevention circuit according to the present invention cyclically selects the memory elements accommodated in the pattern memory, and sequentially selects the memory elements accommodated in the pattern memory, sequentially over the address signal circulation period.
The data stored in the memory element is erased, and if any data remains unerased at this time, the erasure period is extended beyond the address signal circulation cycle from the last time when the unerased data occurs. Therefore, the data stored in the storage element housed inside the pattern memory can be reliably erased.

[Brief explanation of drawings]

The figure is a block diagram showing one embodiment of the present invention. 1 fist..., pattern memory, l ILIIIIII11
Address signal input terminal, 1b--read/write control terminal, 1C--data input terminal, 1d/φ/Φ data output terminal, 2--fist address counter, 3--output signal Detector, 4... Erasing signal generator, 5...
Control circuit, 5a... Erase control terminal, 5b, 5d.
...Input terminal, 5C11@...Output terminal. Patent applicant Agent: ShinNippon Electric Co., Ltd.
Person Masaki Yamakawa (and 1 other person) 11-

Claims (1)

[Claims] an address counter that generates an address signal; when the address signal is supplied, a memory element at an address indicated by the address signal is selected; and when a read/write signal is supplied, a data input signal is sent to the memory element. Include, read/
a pattern memory that outputs the data stored in the storage element as a data output signal when a write signal is supplied; and a detection signal that continues for a predetermined time or more when the data output signal includes a significant signal. an output signal detector that generates an output signal detector; and an erase No. 18 generator that generates an erase signal that is generated synchronously with a change in the address signal and that lasts for half or approximately a tenth of the period during which one of the storage elements is selected. , when the erase control signal and detection signal are supplied,
Or, in any case during the period when the address signal circulates from the time when the erase control signal is supplied, the erase signal is supplied to the pattern memory as a read/write signal Mll1j
A memory erase malfunction prevention device having an il path.