JPH06236695A - Non-volatile memory device with exchange display function - Google Patents

Non-volatile memory device with exchange display function

Info

Publication number
JPH06236695A
JPH06236695A JP2125793A JP2125793A JPH06236695A JP H06236695 A JPH06236695 A JP H06236695A JP 2125793 A JP2125793 A JP 2125793A JP 2125793 A JP2125793 A JP 2125793A JP H06236695 A JPH06236695 A JP H06236695A
Authority
JP
Japan
Prior art keywords
circuit
rewriting
output signal
limit value
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2125793A
Other languages
Japanese (ja)
Inventor
Sachiko Nakayama
祥子 中山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP2125793A priority Critical patent/JPH06236695A/en
Publication of JPH06236695A publication Critical patent/JPH06236695A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To enable the sure exchange of a memory device before the rewriting of data can no longer be made by providing an exchange time display circuit making display in such a manner that the conversion of the device is executed in accordance with the output signal above the limit value of the number of rewriting times from a comparator circuit. CONSTITUTION:The writing effective command signal inputted to the memory device 10 is detected by a rewriting operation detecting circuit 21 and a rewriting operation detection signal B is outputted. A number of rewriting times memory circuit 23 acids the number of rewriting times of a counter output signal C to the previously held number of rewriting times and stores the accumulated number of times. A non-volatile memory element having the limit value of the number of rewriting times equal to or higher than the limit value of the number of rewriting times of the memory element within the device 10 is used for the memory element to be used in this circuit 23. The accumulated number in the number of rewriting times memory circuit 23 and the limit value of the number of rewriting times are then transmitted to a comparator 24. The number of rewriting times output signal D of the circuit 23 and the output signal E of the limit value of the number of rewriting times are received and compared in the circuit 24. The circuit 24 displays 25 the signal F when the signal D rises to E or above.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、EEPROMやフラッ
シュメモリ等書き込み回数に制限を持つ不揮発性メモリ
素子を用いたメモリ装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device using a nonvolatile memory element such as an EEPROM or a flash memory which has a limited number of times of writing.

【0002】[0002]

【従来の技術】従来、この種の装置は、装置を制御する
ための制御部とデータを記憶するためのメモリ部で構成
され、メモリ部にある不揮発性メモリ素子にデータのリ
ード・ライトを行うものである。図3はかかる従来の不
揮発性メモリ装置の一構成例を示すブロック図である。
2. Description of the Related Art Conventionally, a device of this kind is composed of a control unit for controlling the device and a memory unit for storing data, and reads / writes data from / to a nonvolatile memory element in the memory unit. It is a thing. FIG. 3 is a block diagram showing a configuration example of such a conventional nonvolatile memory device.

【0003】この図において、1は各メモリ素子を選択
するためのアドレスデコーダ、2はデータのリード・ラ
イトの制御を行うための制御回路、3は保持するメモリ
部である。また、Aはデータの入出力のためのデータバ
ス、Bはアドレスを入力するためのアドレスバス、Cは
搭載されている各メモリ素子を選択するためのチップセ
レクト信号、Dはアドレスデコーダ1を制御するための
デコーダ制御信号、Eはデータ出力を有効にするための
アウトプットイネーブル信号、Fはデータ書き込みを有
効にするためのライトイネーブル信号、Gは外部からの
データ書き込みを制御するためのデータ書き込み信号
で、Hは外部からのデータ読み出しを制御するためのデ
ータ読み出し信号である。
In this figure, 1 is an address decoder for selecting each memory element, 2 is a control circuit for controlling the read / write of data, and 3 is a memory section for holding it. A is a data bus for inputting / outputting data, B is an address bus for inputting an address, C is a chip select signal for selecting each mounted memory element, and D is for controlling the address decoder 1. Decoder control signal for enabling, E is an output enable signal for enabling data output, F is a write enable signal for enabling data writing, G is data writing for controlling external data writing In the signal, H is a data read signal for controlling the data read from the outside.

【0004】そこで、データの書き込みを行う場合、ア
ドレスバスBより記憶領域の指定のアドレスが入力さ
れ、外部からのデータ書き込み信号Gがイネーブルにな
ると、リードライト制御回路2はアドレスデコーダ1へ
デコーダ制御信号Dを出力し、メモリ部3へライトイネ
ーブル信号Fを出力する。アドレスバスBより入力され
る指定のアドレスとデコーダ制御信号Dを受けたアドレ
スデコーダ1は、アドレスで指定されたメモリ素子を選
択するためのチップセレクト信号Cをメモリ部3へ出力
する。チップセレクト信号Cとライトイネーブル信号F
を受けたメモリ部3内のメモリ素子は、データバスAよ
り入力されたデータを書き込み記憶する。
Therefore, when data is written, when a specified address of the storage area is input from the address bus B and the external data write signal G is enabled, the read / write control circuit 2 controls the address decoder 1 to perform decoder control. The signal D is output, and the write enable signal F is output to the memory unit 3. The address decoder 1 receiving the specified address and the decoder control signal D input from the address bus B outputs the chip select signal C for selecting the memory element specified by the address to the memory unit 3. Chip select signal C and write enable signal F
The memory element in the memory unit 3 that receives the data writes and stores the data input from the data bus A.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、以上述
べた従来のメモリ装置において、図3に示すメモリ部3
のメモリ素子は、データの書換え回数に制限があり、こ
の制限を越えるとメモリ装置が使用できなくなるため、
装置の交換を行っていた。しかし、現状のメモリ装置で
は、正確に交換の時期が分からなかったため、メモリ装
置の交換は、メモリ装置を使用するシステムのメモリ装
置へのデータ書き込み回数が限界にならない期間を事前
に見積もり、その期間でメモリ装置の交換を行ってい
た。
However, in the conventional memory device described above, the memory section 3 shown in FIG. 3 is used.
The memory device has a limit to the number of times data can be rewritten. If this limit is exceeded, the memory device cannot be used.
I was replacing the device. However, in the current memory device, it is not possible to know exactly when to replace the memory device. Therefore, when replacing the memory device, the period during which the number of data writes to the memory device of the system using the memory device does not reach the limit is estimated in advance. I was replacing the memory device.

【0006】しかしながら、この方法では、システムの
動作状況により限界となる期間が変化するため、システ
ムの稼働率が事前の見積もりよりも高い場合には、装置
の交換までに限界を越えてシステムがダウンすることが
あった。本発明は、上記問題点を除去し、メモリのデー
タ書込み回数に適合して、メモリ装置の交換時期を的確
に表示できる交換表示機能付不揮発性メモリ装置を提供
することを目的とする。
However, according to this method, the limit period changes depending on the operating condition of the system. Therefore, if the operating rate of the system is higher than the estimate in advance, the system will be exceeded until the device is replaced and the system is down. There was something to do. SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned problems and provide a nonvolatile memory device with a replacement display function that can accurately display the replacement time of a memory device in accordance with the number of times data is written to the memory.

【0007】[0007]

【課題を解決するための手段】本発明は、上記目的を達
成するために、不揮発性メモリ素子を用いた不揮発性メ
モリ装置において、メモリ素子へのデータ書込み毎の書
換え動作を検出する書換え動作検出回路と、該書換え動
作検出回路からの出力信号に基づいてメモリ素子への書
換えを行った回数をカウントする書換え回数カウンタ
と、該書換え回数カウンタからの出力信号に基づいて、
前にカウントした回数との累積数を記憶する書換え回数
記憶回路と、該書換え回数記憶回路からの書換え回数
と、前記メモリ素子の書換え回数制限値とを比較する比
較回路と、該比較回路からの書換え回数制限値以上の出
力信号に基づいて装置の交換を行うように表示する交換
時期表示回路を設けるようにしたものである。
In order to achieve the above object, the present invention provides a non-volatile memory device using a non-volatile memory element, which detects a rewriting operation every time data is written to the memory element. A circuit, a rewrite frequency counter that counts the number of rewrites to the memory element based on an output signal from the rewrite operation detection circuit, and an output signal from the rewrite frequency counter,
A rewrite frequency storage circuit that stores the cumulative number of times counted before, a comparison circuit that compares the rewrite frequency from the rewrite frequency storage circuit with a rewrite frequency limit value of the memory element, and a comparison circuit from the comparison circuit. A replacement time display circuit is provided to indicate that the device is to be replaced based on an output signal that is equal to or greater than the rewrite count limit value.

【0008】[0008]

【作用】本発明によれば、上記のように、メモリ素子へ
のデータ書込み毎に、書き換えた回数をカウントし、書
き換えた回数を累積して記憶し、該書き換えた回数と、
書換え回数制限値とを比較して、書換え回数が制限値以
上になった場合に、装置の交換を行うように表示するよ
うにしたので、データの書換えができなくなる前に確実
にメモリ装置を交換することができる。
According to the present invention, as described above, the number of times of rewriting is counted every time data is written to the memory element, the number of times of rewriting is accumulated and stored, and the number of times of rewriting is
The number of rewrites is compared with the limit value, and when the number of rewrites exceeds the limit value, it is displayed so that the device can be replaced.Therefore, the memory device must be replaced before the data cannot be rewritten. can do.

【0009】これによって、データの書換えを制限値以
上行って装置内のデータを破壊し、装置が使用できなく
なることを確実に防ぐことができる。
As a result, it is possible to surely prevent the device from becoming unusable by rewriting the data more than the limit value and destroying the data in the device.

【0010】[0010]

【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図1は本発明の実施例を示す交
換表示機能付不揮発性メモリ装置のブロック図である。
図において、10はメモリ装置であり、このメモリ装置
10はメモリ部11と制御部12からなる。21は書換
え動作検出回路、22は書換え回数カウンタ、23は書
換え回数記憶回路、24は比較回路、25は交換時期表
示回路である。
Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of a nonvolatile memory device with an exchange display function showing an embodiment of the present invention.
In the figure, 10 is a memory device, and this memory device 10 comprises a memory unit 11 and a control unit 12. Reference numeral 21 is a rewrite operation detection circuit, 22 is a rewrite number counter, 23 is a rewrite number storage circuit, 24 is a comparison circuit, and 25 is a replacement time display circuit.

【0011】また、Aはライトイネーブル信号、Bは書
換え動作検出信号、Cはカウンタ出力信号、Dは書換え
回数出力信号、Eは書換え回数制限値出力信号、Fは比
較回路出力信号である。そこで、書換え動作検出回路2
1はライトイネーブル信号Aが送られるライトイネーブ
ル信号線によりメモリ装置10と接続されるとともに、
書換え動作検出信号Bが送られる書換え動作検出信号線
により書換え回数カウンタ22と接続される。この書換
え回数カウンタ22はカウンタ出力信号Cが送られるカ
ウンタ出力信号線により書換え回数記憶回路23と接続
される。この書換え回数記憶回路23は書換え回数出力
信号Dが送られる書換え回数出力信号線により比較回路
24と接続される。
A is a write enable signal, B is a rewrite operation detection signal, C is a counter output signal, D is a rewrite count output signal, E is a rewrite count limit value output signal, and F is a comparison circuit output signal. Therefore, the rewrite operation detection circuit 2
1 is connected to the memory device 10 by a write enable signal line to which the write enable signal A is sent,
The rewrite operation detection signal line to which the rewrite operation detection signal B is sent is connected to the rewrite number counter 22. The rewrite number counter 22 is connected to the rewrite number storage circuit 23 by a counter output signal line to which the counter output signal C is sent. The rewrite frequency storage circuit 23 is connected to the comparison circuit 24 by a rewrite frequency output signal line to which the rewrite frequency output signal D is sent.

【0012】一方、比較回路24には書換え回数制限値
出力信号Eが入力される書換え回数制限値出力信号線が
接続される。また、比較回路24の出力信号線は交換時
期表示回路25に接続され、比較回路出力信号Fは交換
時期表示回路25に送られる。次に、本発明の実施例を
示す交換表示機能付不揮発性メモリ装置の動作を図2を
用いて説明する。
On the other hand, the comparison circuit 24 is connected to a rewrite number limit value output signal line to which the rewrite number limit value output signal E is input. The output signal line of the comparison circuit 24 is connected to the replacement time display circuit 25, and the comparison circuit output signal F is sent to the replacement time display circuit 25. Next, the operation of the nonvolatile memory device with the exchange display function showing the embodiment of the present invention will be described with reference to FIG.

【0013】まず、メモリ素子へデータ書込みを行う
(ステップS1)際は、メモリ装置10にライトイネー
ブル信号Aが入力される。すると、書換え動作検出回路
21はメモリ装置10に入力されるライトイネーブル信
号Aの動作を監視し、メモリ素子にデータが書き込まれ
ていることを検出する(ステップS2)。メモリ装置1
0内のメモリ素子がEEPROMの場合、ライトイネー
ブル信号Aがアサートして、また次にアサートするまで
の間隔が十数nsec(ナノ秒)以上空いた時にデータ
の書込みが行われるため、書換え動作検出回路21はそ
の間隔を検出し(ステップS2)、データの書換えが行
われたものとして書換え動作検出信号Bを出力する(ス
テップS3)。
First, when data is written to the memory device (step S1), the write enable signal A is input to the memory device 10. Then, the rewrite operation detection circuit 21 monitors the operation of the write enable signal A input to the memory device 10 and detects that data is written in the memory element (step S2). Memory device 1
When the memory element in 0 is an EEPROM, data is written when the write enable signal A is asserted and the interval until it is asserted is more than ten nanoseconds (nanoseconds). The circuit 21 detects the interval (step S2) and outputs the rewrite operation detection signal B (step S3) assuming that the data has been rewritten.

【0014】メモリ装置10内のメモリ素子がフラッシ
ュメモリの場合、メモリ装置10に入力される書込み実
行コマンド信号を、書換え動作検出回路21で検出し
(ステップS2)、書換え動作検出信号Bを出力する
(ステップS3)。書換え回数カウンタ22は、書換え
動作検出信号Bをカウントして、書換え回数をカウンタ
出力信号Cとして出力する(ステップS4)。書換え回
数記憶回路23は、カウンタ出力信号Cの書換え回数を
前に保持していたものに加算器で加え、その累積結果を
記憶する(ステップS5)。この書換え回数記憶回路2
3に用いる記憶素子は、メモリ装置10内のメモリ素子
と同等、又はそれ以上の書換え回数制限値を持つ不揮発
性メモリ素子を使用する。
When the memory device in the memory device 10 is a flash memory, the write execution command signal input to the memory device 10 is detected by the rewrite operation detection circuit 21 (step S2), and the rewrite operation detection signal B is output. (Step S3). The rewrite number counter 22 counts the rewrite operation detection signal B and outputs the rewrite number as a counter output signal C (step S4). The rewrite number storage circuit 23 adds the number of rewrites of the counter output signal C to what was previously held by an adder and stores the cumulative result (step S5). This rewrite frequency storage circuit 2
As the memory element used in No. 3, a non-volatile memory element having a rewrite count limit value equal to or greater than the memory element in the memory device 10 is used.

【0015】次に、比較回路24に、書換え回数記憶回
路23での累積数と、書換え回数制限値を送信し(ステ
ップ6)、比較回路24では書換え回数記憶回路23の
書換え回数出力信号Dと、書換え回数制限値出力信号E
を受信し(ステップS7)、両者を比較する。書換え回
数出力信号Dが書換え回数制限値出力信号E以上となっ
た場合(ステップS8)、書換え回数比較回路24は比
較回路出力信号Fを交換時期表示回路25へ出力する。
比較回路出力信号Fを受信した交換時期表示回路25
は、LEDを点灯させる等メモリ装置の交換を促す表示
を行う(ステップS9)。
Next, the cumulative number in the rewrite frequency storage circuit 23 and the rewrite frequency limit value are transmitted to the comparison circuit 24 (step 6), and the comparison circuit 24 outputs the rewrite frequency output signal D of the rewrite frequency storage circuit 23. , Rewrite count limit value output signal E
Is received (step S7), and both are compared. When the rewrite number output signal D becomes equal to or more than the rewrite number limit value output signal E (step S8), the rewrite number comparison circuit 24 outputs the comparison circuit output signal F to the replacement time display circuit 25.
Replacement time display circuit 25 receiving the comparison circuit output signal F
Displays a message prompting the replacement of the memory device such as turning on the LED (step S9).

【0016】なお、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づいて種々の変形が可能
であり、これらを本発明の範囲から排除するものではな
い。
The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the present invention, and these modifications are not excluded from the scope of the present invention.

【0017】[0017]

【発明の効果】以上、詳細に説明したように、本発明に
よれば、メモリ素子へのデータ書込み毎の書換え動作を
検出する書換え動作検出回路と、この書換え動作検出回
路からの出力信号に基づいてメモリ素子への書換えを行
った回数をカウントする書換え回数カウンタと、この書
換え回数カウンタからの出力信号に基づいて、前にカウ
ントした回数との累積数を記憶する書換え回数記憶回路
と、この書換え回数記憶回路からの書換え回数と、前記
メモリ素子の書換え回数制限値とを比較する比較回路
と、この比較回路からの書換え回数制限値以上の出力信
号に基づいて装置の交換を行うように表示する交換時期
表示回路を設けるようにしたので、データの書換えがで
きなくなる前に確実にメモリ装置を交換することができ
る。
As described above in detail, according to the present invention, a rewrite operation detecting circuit for detecting a rewrite operation every time data is written to a memory element, and an output signal from the rewrite operation detecting circuit are used. A rewrite frequency counter that counts the number of rewrites to the memory element, and a rewrite frequency storage circuit that stores the cumulative number of the recount frequency based on the output signal from the rewrite frequency counter. A comparison circuit that compares the number of times of rewriting from the number of times memory circuit with a limit value of the number of times of rewriting of the memory element, and a message indicating that the device should be replaced based on an output signal from the comparison circuit that is equal to or greater than the limit number of times of rewriting Since the replacement time display circuit is provided, the memory device can be reliably replaced before the data cannot be rewritten.

【0018】これによって、データの書換えを制限値以
上行って装置内のデータを破壊し、装置が使用できなく
なることを防ぐことができる。
As a result, it is possible to prevent the device from becoming unusable by rewriting the data over the limit value and destroying the data in the device.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例を示す交換表示機能付不揮発性
メモリ装置のブロック図である。
FIG. 1 is a block diagram of a nonvolatile memory device with an exchange display function according to an embodiment of the present invention.

【図2】本発明の実施例を示す交換表示機能付不揮発性
メモリ装置の動作フローチャートである。
FIG. 2 is an operation flowchart of the nonvolatile memory device with a replacement display function according to the embodiment of the present invention.

【図3】従来の不揮発性メモリ装置の一構成例を示すブ
ロック図である。
FIG. 3 is a block diagram showing a configuration example of a conventional nonvolatile memory device.

【符号の説明】[Explanation of symbols]

10 メモリ装置 11 メモリ部 12 制御部 21 書換え動作検出回路 22 書換え回数カウンタ 23 書換え回数記憶回路 24 比較回路 25 交換時期表示回路 A ライトイネーブル信号 B 書換え動作検出信号 C カウンタ出力信号 D 書換え回数出力信号 E 書換え回数制限値出力信号 F 比較回路出力信号 10 memory device 11 memory unit 12 control unit 21 rewriting operation detection circuit 22 rewriting frequency counter 23 rewriting frequency storage circuit 24 comparison circuit 25 replacement time display circuit A write enable signal B rewriting operation detection signal C counter output signal D rewriting frequency output signal E Rewrite count limit value output signal F comparison circuit output signal

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 不揮発性メモリ素子を用いた不揮発性メ
モリ装置において、(a)メモリ素子へのデータ書込み
毎の書換え動作を検出する書換え動作検出回路と、
(b)該書換え動作検出回路からの出力信号に基づいて
メモリ素子への書換えを行った回数をカウントする書換
え回数カウンタと、(c)該書換え回数カウンタからの
出力信号に基づいて、前にカウントした回数との累積数
を記憶する書換え回数記憶回路と、(d)該書換え回数
記憶回路からの書換え回数と、前記メモリ素子の書換え
回数制限値とを比較する比較回路と、(e)該比較回路
からの書換え回数制限値以上の出力信号に基づいて装置
の交換を行うように表示する交換時期表示回路を備えた
ことを特徴とする交換表示機能付不揮発性メモリ装置。
1. A non-volatile memory device using a non-volatile memory element, comprising: (a) a rewriting operation detection circuit for detecting a rewriting operation every time data is written to the memory element;
(B) A rewrite frequency counter that counts the number of rewrites to the memory element based on the output signal from the rewrite operation detection circuit; and (c) counts forward based on the output signal from the rewrite frequency counter. And (e) a comparison circuit for comparing the number of rewritings from the rewriting number storage circuit with a rewriting number limit value of the memory element, and (e) the comparison. A non-volatile memory device with a replacement display function, comprising a replacement timing display circuit for displaying that the device is to be replaced based on an output signal from the circuit that is equal to or greater than a limit value of the number of times of rewriting.
JP2125793A 1993-02-09 1993-02-09 Non-volatile memory device with exchange display function Withdrawn JPH06236695A (en)

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Application Number Priority Date Filing Date Title
JP2125793A JPH06236695A (en) 1993-02-09 1993-02-09 Non-volatile memory device with exchange display function

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JPH06236695A true JPH06236695A (en) 1994-08-23

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1044527A (en) * 1996-08-01 1998-02-17 Fuji Xerox Co Ltd Method for storing print data and printer
JP2006023815A (en) * 2004-07-06 2006-01-26 Nec Infrontia Corp Memory life warning device and information processing method
US6993690B1 (en) 1998-12-16 2006-01-31 Hagiwara Sys-Com Co., Ltd. Memory unit having memory status indicator
JP2008186295A (en) * 2007-01-30 2008-08-14 Fujitsu Ltd Data recording system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1044527A (en) * 1996-08-01 1998-02-17 Fuji Xerox Co Ltd Method for storing print data and printer
US6993690B1 (en) 1998-12-16 2006-01-31 Hagiwara Sys-Com Co., Ltd. Memory unit having memory status indicator
JP2006023815A (en) * 2004-07-06 2006-01-26 Nec Infrontia Corp Memory life warning device and information processing method
JP4527456B2 (en) * 2004-07-06 2010-08-18 Necインフロンティア株式会社 Memory life warning device and information processing method
JP2008186295A (en) * 2007-01-30 2008-08-14 Fujitsu Ltd Data recording system

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