JPH11282766A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To continue the operation immediately before a hold even after the hold irrespective of a drop in a power source voltage. SOLUTION: When hold state is entered by a drop in a power voltage VDD, data of a program counter 3, a RAM 4 and a stack pointer 5 are saved into an area, which is has not been used, of a nonvolatile memory 2 that is electrically simultaneously erasable. When the hold is released, data are read out of the nonvolatile memory 2, are set in the program counter 3, the RAM 4 and the stack pointer 5 and, a microcomputer continues to be operated from the state immediately before the hold.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer whose operation is held in response to a decrease in power supply voltage.

[0002]

2. Description of the Related Art Generally, as shown in FIG. 3, a microcomputer stores a mask ROM in which at least an operation control program is stored, a program counter PC for performing address control for reading a ROM program, and data. A built-in RAM and a stack pointer for holding the address of the main routine when shifting from the main routine of the program to the subroutine. On the other hand, the microcomputer has a hold function. The hold function suspends the main operation of the microcomputer when the power supply voltage VDD decreases, and restarts the main operation of the microcomputer when the power supply voltage VDD returns. As shown in FIG. 3, a capacitor is connected to the power supply terminal VDD in the microcomputer, and when the power supply voltage drops, only the terminal voltage of the capacitor performs only a minimum operation such as a clock operation so that the microcomputer is not completely stopped. When the power supply voltage is restored, the main operation of the microcomputer is continued.

[0003]

By the way, conventionally,
When the power supply voltage VDD decreases, the operation changes according to the amount of decrease in the power supply voltage VDD. As shown in FIG. 4A, when the drop in the power supply voltage VDD is small, for example, higher than a voltage at which data can be held, the microcomputer holds the operation before the hold because the data is held when the power supply voltage VDD returns. Can be restarted.

However, when the power supply voltage VDD becomes lower than the voltage at which data can be held as shown in FIG. 4A, the data stored in the RAM, the program counter PC and the stack pointer are in an undefined state (period a in FIG. 4A). Therefore, the data before the hold cannot be held accurately. Therefore, even when the power supply voltage is restored, the operation of the microcomputer cannot be continued.

[0005]

According to the present invention, there is provided a microcomputer which holds an operation when a power supply voltage drops, a power supply voltage detecting means for outputting an output signal in a predetermined state in accordance with the power supply voltage drop, A save memory for temporarily saving data to be saved in accordance with an output signal of the power supply voltage detection means.

[0006] Further, when the hold is released, there is provided means for reading the data saved in the memory and setting the read data in a circuit corresponding to the data. In particular, the memory is a nonvolatile memory that can be electrically erased in a batch.

[0007] Further, there is provided an address counter for specifying an address of the nonvolatile memory, and a selector for selecting each circuit corresponding to data to be saved,
Data writing and reading to a designated address are performed. The nonvolatile memory includes a flag for holding a state as to whether data is saved.

According to the present invention, the data to be saved is written to the memory when the hold state is entered, and when the hold is released, the data is read from the memory and the data is set in each circuit. The operation is continued from the state of.

[0009]

FIG. 1 is a diagram showing an embodiment of the present invention. 1 is a CPU for controlling the operation of the microcomputer, 2 is a non-volatile memory that includes data input / output units 2a and 2b, an address control unit 2c, and a flag FRF and stores an operation program of the microcomputer and is electrically erasable collectively. (Flash memory) 3, a program counter PC for controlling an address of the nonvolatile memory 2,
4 is a RAM for storing data, 5 is a stack pointer for holding the count value of the program counter PC of the main routine when shifting from the main routine of the program to a subroutine, and 6 is for decoding the program data of the nonvolatile memory 2 into program instructions. An instruction decoder, 7 a power supply voltage detection circuit for detecting whether the power supply voltage VDD is higher or lower than a predetermined level Vr, 8 an inverter for binarizing the level of the power supply voltage VDD, 9 a power supply voltage detection of the output of the inverter 8 A register 10 that holds a signal in accordance with an output pulse of the circuit 7 includes an address control unit 10a and a data output unit 10b, and a mask ROM in which a program for rewriting program data in the nonvolatile memory 2 is stored. The output ro is made conductive, and the A conduction circuit that conducts data to the flag FRF, 13 is a selector that selects the program counter 3, the RAM 4 or the stack pointer 5 according to the address signal ad2 from the CPU 1, and 14 is a data input / output unit 2a according to the output ro of the register 9. Or 2b, a selector for selecting 2b, and 15 a selector signal S from the CPU 2.
A selector for selecting the address signal ad1 in the nonvolatile memory 2 or the ROM 10 in accordance with L1.
2 in accordance with the selector signal SL1 from the nonvolatile memory 2
Alternatively, a selector for selecting output data to the ROM 10, a selector 17 for selecting the address signal ad1 or ad2 according to the select signal SL2 from the CPU 2, and a selector 18 for transmission to the selector 14 or 16 according to the select signal SL2 from the CPU 2. A selector 19 for selecting the selector selects the input data IN and the output data of the selector 14. Note that the circuits of the programmable counter 3 to the register 9 and all selectors are configured as a part of the CPU 1, and in FIG.

In a microcomputer having a built-in nonvolatile memory, a mask RO for rewriting the program is used.
The address numbers of M1 and the nonvolatile memory 2 are assigned consecutive address numbers. For example, assuming that addresses of 0000H to 0100H are assigned to the mask ROM 1, 0101H to FFFFH are assigned to the nonvolatile memory 2.

Since the programs written in the mask ROM 1 and the nonvolatile memory 2 are used for operation control, it is desirable to control the addresses of the two memories by the same addressing signal. Since the computer uses the address control of a microcomputer having a built-in ROM or RAM as it is, the nonvolatile memory 2 and the mask ROM
1 is assigned a continuous address. Then, an area specified by addresses 0000H to 0100H also exists in the non-volatile memory 2, which has conventionally been an unused area.

FIG. 2 shows the operation of the microcomputer shown in FIG.
A description will be given based on the flowchart of FIG. When the power supply VDD is applied to the microcomputer, first, the CPU 1 checks the state of the flag FRF provided in the nonvolatile memory 2 (S1). Different states are written in the flag FRF depending on whether various data are saved in the nonvolatile memory 2, data is saved when “0” is written, and saved when “1” is written. Not indicate. When the power is turned on, the flag FRF is set to an initial state of “1”. Therefore, when the power is turned on and the state “1” of the flag FRF is first checked, the operation shifts to the initial setting operation. At the time of the initial setting operation, the same initial setting operation as in the related art is performed, for example, by clearing the data of the program counter 3, the RAM 4, and the stack pointer 5 (S2).

After the completion of the initial setting, it is confirmed whether or not the microcomputer is in the hold state (S3). That is, it is determined whether the power supply voltage VDD has decreased. When the power supply voltage VDD falls below the predetermined level Vr and crosses the predetermined level Vr, the power supply voltage detection circuit 7 outputs a pulse having a predetermined width. When the power supply voltage VDD drops, an L-level output is output from the inverter 8, and the output of the inverter 8 is stored in the register 9 at the timing of the pulse.
Is held. Conversely, when the power supply voltage VDD rises again and crosses the predetermined level Vr, a pulse of a predetermined width is output from the power supply voltage detection circuit 7 and the output of the inverter 8 becomes H level and is held in the register 9.

If the power supply voltage VDD does not decrease, the register 9
Keeps the H level, the CPU 1 is determined not to be in the hold state, and the CPU 1 starts the normal operation. In the normal operation, first, the CPU 1 outputs select signals SL1 and SL2 at H level, the selector 15 outputs the address signal ad1 to the selector 17, and the selector 16 selects the output data of the nonvolatile memory 2 and , The selector 17 selects the address signal ad1, and the selector 18 outputs the output data of the nonvolatile memory 2 to the selector 16. In such a state, the operation is performed according to the program written in the nonvolatile memory 2.

The count value of the program counter 3 of the CPU 1 is incremented, and an address signal ad1 is output according to the count value. In this case, the address signal ad1 is the address 0101H-F of the nonvolatile memory 2.
One of FFFH is designated. The address signal ad1 is input to the address control unit 2c of the nonvolatile memory 2 via the selectors 15 and 17. The address of the nonvolatile memory 2 is specified by the address signal ad1,
The program data is read. The program data is output from the data output unit 2b, and the selectors 18 and 16
And is decoded into a program instruction by the instruction decoder 6, and various operations are executed. Thereafter, the count value of the program counter 3 is incremented, the next address is designated in the nonvolatile memory 2, and various instructions are executed in accordance with the program data at that address (S4). In normal operation, the microcomputer repeats the above operation,
Since the steps S3 and S4 are repeated, the microcomputer performs a normal operation while monitoring the decrease of the power supply voltage VDD.

Here, rewriting of data by an external interrupt during normal operation will be described. First, the select signal SL1 from the CPU 1 becomes L level, the selector 15 outputs the address signal ad1 to the mask ROM 10, and the selector 16 selects the output data of the mask ROM 10. Thereafter, after the current count value of the program counter 3 is stored in a register (not shown), the count value of the program counter 3 is set to a predetermined value. Thereby, the addresses 0000H to 010 for the mask ROM 10 are set.
An address signal ad1 designating any one of 0H is output. The address signal ad1 is input to the address control unit 10a of the mask ROM 10 via the selector 15.
Then, the address of the ROM 10 is designated and the ROM 1
0 is read out. The program data is input to the instruction decoder 6 via the selector 16 and is decoded into a program instruction. Further, the program counter PC is incremented and R
The next address in the OM 10 is specified.

A program for rewriting data in the nonvolatile memory 2 is written in the mask ROM 10, and the CPU 1 operates according to the program. First, RA
The address of M4 is specified, and the data to be rewritten is read. The read data is held in a register (not shown) of the CPU 1 and then transferred to the data input unit 2a of the nonvolatile memory 2. The data in the data input section 2a is written into the nonvolatile memory 2, and the data rewriting is completed. When the rewriting is completed, the count value immediately before the external interrupt stored in the register (not shown) is set to the program count 3 and the operation returns to the normal operation. In addition, RAM4
Is transferred to the nonvolatile memory 2 by the CPU.
The select signal SL3 from 1 goes high, the selector 19 selects the input data IN14 and transfers it to the nonvolatile memory 2.

In step S3, when the power supply voltage VDD decreases, data saving starts. The output ro of the register 9 changes from the H level to the L level according to the power supply voltage VDD. When the output ro becomes L level, the selector 14 selects the selector 19 side, and the output ro is input to the conduction circuit 12. Further, the select signals SL2 and SL3 from the CPU 1 become L level, and the selector 17
The address signal ad2 from the PU 12 is selected, the selector 18 selects the selector 14 side, and the selector 19 selects the output data of the selector 14.

When the power supply voltage VDD decreases, the address counter 1a in the CPU 1 starts counting, and when it does, an address signal ad2 is output and input to the address control section 2c via the selector 17. The address signal ad2 specifies addresses 0000H to 0100H. First address signal 00 from address counter 1a
00H is output and the address 000 of the nonvolatile memory 2 is output.
0H is designated. Incidentally, the address 0000H is formed as an area of the flag FRF, and the conduction circuit 14 inputs data "0" only when the address 0000H is designated. Therefore, the flag FRF is set to “0” by the first address signal (S
5).

When the address counter 1a is incremented, the address of the nonvolatile memory 2 changes. At the same time, the selection state of the selector 13 is also switched according to the address signal ad2. That is, in the nonvolatile memory 2, a save data area is assigned to each circuit for saving data. For example, the program counter 3 stores address 0001 and the RAM 4 stores addresses 0002 to 0.
Assume that address 0FF is assigned to the stack pointer 5 and address 0100 is assigned to the stack pointer 5. Then, the address signal ad2 becomes 000
When it becomes 1H, the selector 13 selects the data of the program counter 3 and writes the data to the address 0001 of the nonvolatile memory 2. Address signal ad2 changes from 0002H to 00F
When FH is reached, the data in RAM 4 is
The data is written to addresses 001 to 00FF, and when the address signal ad2 becomes 0100H, 010 of the nonvolatile memory 2 is read.
It is written to address 0. The selector 13 is configured to select a circuit corresponding to the address assigned according to the address signal ad2. By the above operation, the data of the program counter 3, the RAM 4, and the stack pointer 5 are saved in the area of the nonvolatile memory 9 which has not been used in the past (S6). By evacuating data to the nonvolatile memory 2 as in the present invention, data in the nonvolatile memory is not erased even when the power is turned off, so that data is lost no matter how the power supply voltage VDD changes during the hold. I will not be told.

After that, when the data saving is completed, the microcomputer enters the hold state, stops the main operation of the CPU 1 and the like, and performs only the necessary minimum operation such as the clock function (S7). When the power supply voltage VDD returns,
The saved data is returned to each circuit. Power supply voltage V
With the return of DD, the output ro of the register 8 becomes H level, and the selector 14 selects the data output unit 2b side. The operation of the CPU 1 and the like in the microcomputer is resumed, and the process returns to step S1 where the CPU 1 checks the state of the flag FRF in the nonvolatile memory 2. Since the state of the flag FRF is “0”, various data are stored in the nonvolatile memory 2.
It is confirmed that she has been evacuated. "0" of the flag FRF
CPU 1 sets the address counter 1a to 00 in accordance with the state of
01H, the 0001 of the nonvolatile memory 2 is counted.
Addresses to 0100 are sequentially designated, and the saved data is read.

Since the selector 13 selects the program counter 3 in response to the first address signal ad2, the read data is set in the program counter 3.
When the address counter 1a is incremented and the address signal ad2 changes from 0002H to 00FFH, data at addresses 0002 to 00FF of the nonvolatile memory 2 is read. Since the selector 13 selects the RAM 4,
The read data is written to the RAM 4. It is further incremented and the address signal ad2 becomes 0100H
Then, the data at the address 0100 of the nonvolatile memory 2 is read. Since the selector 13 selects the stack pointer 5, the read data is stored in the stack pointer 5.
Is set to By the above operation, the data saved in the nonvolatile memory 2 is returned to each circuit. (S
8).

After the data reading is completed, the CPU 1 erases the data in the nonvolatile memory 2 (S9), and the flag signal FL
To control the address control unit 2c and the conduction circuit 12 to change the state of the flag area FRF in the nonvolatile memory 2 to 1
Is set (S10). Next, the process proceeds to step S3,
After confirming whether or not the CPU 1 is in the hold state, the CPU 1 returns to the normal operation. Since the normal operation starts after the saved data is set in the program counter 3, the RAM 4, and the stack pointer 5, the operation is continued from the operation immediately before being held.

As described above, data can be saved in the area of 0000H to 0100H of the nonvolatile memory 2 which is assigned the same address as that of the ROM 10 and is not used in the related art. In FIG. 1, the program counter 3, R
Although the data of the AM 4 and the stack pointer 5 are held, if the data is not to be lost and temporarily saved in the hold state, temporarily save not only the data of the above circuit but also the data of other circuits. Is also possible.

[0025]

According to the present invention, the data to be saved is written into the nonvolatile memory when the hold state is entered, and when the hold is released, the data is read from the memory and the data is set in each circuit. The operation can be continued from the state immediately before the hold after the release. In particular, since a non-volatile memory that can be electrically erased collectively is used as the memory, data can be stored even when the power is turned off. The operation can be continued from the operation.

Further, since data is saved in a part of the nonvolatile memory which has not been used in the related art, the nonvolatile memory can be effectively used.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of FIG.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a characteristic diagram for explaining the operation of FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Non-volatile memory 3 Program counter 4 RAM 5 Stack pointer 6 Instruction decoder 7 Power supply voltage detection circuit 8 Inverter 9 Register 10 Mask ROM 12 Conduction circuit 13 to 19 Selector

Claims (5)

[Claims] 1. A microcomputer for holding an operation when a power supply voltage drops, in which a nonvolatile memory in which program data is written and electrically erasable collectively and a program for rewriting a program in the nonvolatile memory are written. Along with
A ROM provided with the same address as the specific address of the nonvolatile memory; and a power supply voltage detecting means for outputting an output signal in a predetermined state in response to a decrease in the power supply voltage; A microcomputer comprising: a save unit for temporarily saving data to be saved in a specific address area of the nonvolatile memory in accordance with a signal. 2. The apparatus according to claim 1, further comprising: first selector means for selecting an address of the ROM during a normal operation and selecting an address of the nonvolatile memory at the time of evacuation for the same address assigned to the nonvolatile memory and the ROM. 2. The microcomputer according to claim 1, wherein: 3. When the hold is released, there is provided means for reading data saved in a specific address area of the nonvolatile memory and setting the read data in a circuit corresponding to the data. 3. The microcomputer according to claim 1, wherein And a second selector for selecting a circuit corresponding to data to be saved based on an address signal for designating an address of the nonvolatile memory. 4. The microcomputer according to claim 3, wherein data is written to and read from an address in a predetermined area corresponding to the circuit. 5. The microcomputer according to claim 2, wherein the nonvolatile memory includes a flag for holding a state as to whether data is saved.