JPS6150289A - Decoder circuit - Google Patents

Abstract

PURPOSE:To accelerate the discharge of a decoder circuit by discharging an electric charge, which is charged to an output in a writing or deletion mode, with the aid of a sufficiently low on-resistance. CONSTITUTION:In terms of this IGFETQ121, its drain and gate are connected to an output O' of a decoder circuit and to a signal DIS, respectively, and moreover a source and substrate are grounded. When a write or deletion mode is terminated, a pulse for becoming H for a certain period is impressed to the signal DIS. At this time, the electric charge, which is charged to a capacity added to the output O' in the write or deletion mode, is discharged to the ground by the prescribed time constant, while the voltage of the output O' comes to a power source voltage Vcc. The time width of the signal DIS can be set short when the on-resistance of the Q121 is made minimal. As a result, the discharging speed of the electric charge, which is charged to the capacity of the output O' in the write or deletion mode, is high. Then when the voltage of the output O' comes to the power source voltage Vcc, the operation becomes a read mode.

Description

[Detailed Description of the Invention] [Technical Field] The present invention uses a field effect transistor (hereinafter referred to as IGFET) having an insulated gate structure as its main component, and has a large capacity and high performance. Speed is required'
The present invention relates to a decoder circuit used in a write-erasable nonvolatile memory device.

[Prior art]

Figure 1 is a circuit diagram of a decoder circuit according to a conventional example (Japanese Patent Application No. 57-161861).
1 is connected to P-channel type IGFET'''c'.

Q1□2 is a P-channel type IGFET which is connected in parallel to KQll between the power supply CC and the ON state, and has the address input a2 connected to the gate as C2A. In Q1□3, the drain is lit.

This is an N-channel IGFET whose gate is connected to address input a1 and whose source is connected to point MK. Ql, 4 is an N-channel ff1 IGFET whose drain is connected to the point Δ(, the gate is connected to the address input a2, and the source is connected to the ground. Q115 has the source connected to the power supply CC and the gate turned on.

A P-channel IGFET whose drain is connected to point N.

Ql, 6 is an N-channel type IGFET whose drain is connected to point N, gate is connected to point N, and source is connected to ground. Q
1 and 7 are depleted by the N channel connected to the signal WOE, whose drain is the point NK and whose gate is 'L' during write or erase mode, and becomes 'H' when the write or erase mode ends. It is a type τIGFET.

Points pp/, c are set to the write control voltage Vpp' in write or erase mode, and otherwise set to the power supply voltage Mac.
Ke ;! := 1') VC'mm-Pi-'zE
nmi5t'Lfc'A'15N source, or high voltage vp by a booster circuit during writing or erasing mode.
It is an internal 1:1 source controlled by an internal circuit so that p' is omitted and the power supply voltage is Vcc in other cases. Q
1□8 is the source pp/. .

, the gate is at point 0, the drain is at point Q, and the substrate is at point pp.
/ccK connected P-channel type IGFET. Q
For l, 9, the drain is at point Q and the gate is at point 0.

This is an N-channel IGFET whose source is connected to ground. Q120 has a source at point pp10c and a gate at point Q
This is a P-channel WIGFET with the drain connected to point OK and the substrate connected to point pp/c. Here QllllQ
1121 The P-channel IGFET substrates indicated by Ql15 are all connected to the power supply CCK, and Qoa * Ql□4
．． The substrates of the N-channel WIGFETs designated Q1□6+Q119 are all connected to ground. Also, all IGFETs except Q117 are enhancement type, with a point of 0.
is the output of the decoder circuit of FIG.

Next, the operation of the decoder circuit shown in FIG. 1 will be explained using FIGS. 1 and 2. Figure 2 shows when writing or erasing mode.
and signal WOE when writing or erasing mode ends and changes to reading mode.

Point pp/c, *Decoder circuit output O9 signal READ
This shows the change in voltage over time.

i) When entering write or erase mode, signal WOE becomes L#
(time t21), the voltage at point pp/c increases by the write control voltage vpp't. Address input al
, JL2 are both I Hn, the decoder circuit is selected and the point I L 711 point N becomes 'H#. At this time Q1.
The difference between the voltage at the gate of point 7 and the voltage at point N is (-Vcc)
Therefore, if the threshold voltage of Ql17 is set below Vcci, no current flows from point 0 to power supply CCK. Therefore, the output voltage O rises to the write control voltage Vp p/ as shown in FIG. On the other hand a1 or a2
When is II L 7+, the decoder circuit has only three options, the point is u H179 point N is @ L n, and the output 0 becomes °゛L''.

By the way, the decoder circuit shown in Fig. 1 generally has the following (1
), and (2) are taken into consideration.

(1) :t! ! 'In write or erase mode, if the decoder circuit is selected, voltage (Vcc) is applied to point O.
(5V, for example) is applied to the point Pp/cc, and the voltage (Vp
p'] (e.g. 20v) is applied, Ql, 8 and Q
The gate length at which the inverter can be inverted is defined as the groove bottom from 119, and the gate width is indicated as W. ) is made smaller than C in Q119.

(2) In write or erase mode, the decoder circuit changes from selected (output 0 voltage is Vpp') to inactive9, a L
Oii LE "L" (Vcc: l to fz
In case of c, r of Q120 is made much smaller than ℃ of Q116 and r of Q117 so that the inverter drawn from Q1□8 and Q119 can be inverted W W W .

Q1□It is necessary to make the sound of 0 = 9.

The operation under such favorable conditions will be explained. WOE is par
When the write or erase mode ends (time t22), the voltage at point pp/cc becomes the power supply voltage Vcc. When the write or erase mode ends, the voltage at the point pp/cc becomes the power supply voltage Vcc. ?D; As the voltage at point pp/cc decreases, the charge is discharged to the power supply with a time constant determined by the capacitance of output 0 and the current drive capability of Q1□0 (hereinafter referred to as on resistance O). , ultimately the voltage of output 0 is the power supply voltage V
ccK becomes. As mentioned above, since r of Q1□0 is small, the on-resistance of Q12G is large9, and the time constant at which the voltage of the output O decreases is generally large as shown by Dl in FIG. 2. When the voltage of output 0 becomes the power supply voltage VccK, the signal R
EAD becomes H' and enters read mode (at time t
24) 0 As mentioned above, according to the conventional decoder circuit, the electric charge charged in the capacitance added to the output of the decoder circuit is discharged through the IGFET having a high onn resistance, so that it cannot be used in write or erase mode. Setting the timing for changing from the write mode to the read mode is complicated, and it is necessary to set a long time width for changing from the write or erase mode to the read mode. Therefore, it is unsuitable for applications that perform high-speed write or erase-read cycles.

[Purpose of the invention]

1. An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a decoder circuit that can perform write or erase-read cycles at high speed and that can easily set the timing for changing from write or erase mode to read mode. It is about providing.

[+1/1 of the invention] The present invention provides a NAND circuit into which a plurality of addresses are input, and a 218 circuit in which the output of the NAND circuit is connected to the input.
a first field effect transistor having a drain connected to the output of the first inverting amplifier; a first voltage being applied during a write or erase mode; and a second voltage being applied during a read mode; a second inverting amplifier inserted between the first node and ground, the input of which is connected to the source of the first field effect transistor; a second field effect transistor connected to a node of the first field effect transistor and having a gate connected to the output of the second inverting amplifier; a source of the first field effect transistor and a drain of the second field effect transistor; is connected to a second node; and DRA/ is connected to the second node; The present invention is characterized in that it has a field effect transistor and a third field effect transistor of an inverse quadrature type, and the second node is used as an output. .

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 3 is a circuit diagram of a decoder circuit according to an embodiment of the present invention. The same reference numerals in the circuit diagram of FIG. M1 indicate the same components. Q121 is an N-channel enhancement type IGFET Q1□1 having a drain connected to the output α of the decoder circuit, a gate connected to the signal DIS, a source connected to the ground, and a substrate connected to the ground. The signal DIS is
Normally, the voltage state is "L#", but after the write or erase mode ends, a pulse is applied that becomes "H#" for a certain period of time.Next, the operation of the embodiment will be explained.Write or erase The operation of the decoder circuit of the embodiment in mode and read mode is that the signal DIS becomes @L I+ and Q12
1 is in a non-conductive state, so it is exactly the same as the conventional example, so the explanation will be omitted, and the operation from the end of the write or erase mode to the read mode will be described in the third example.
This will be explained using FIG.

Figure 4 shows the signal WOE in write or erase mode and when the write or erase mode ends and changes to read mode, at point pp/cc *Decoder circuit output 0'
1 shows the temporal changes in the voltages of the signal DIS and the signal READ. When W'+E goes from 'L'' to H# and the write or erase mode ends (time t42), point p
The voltage of p/cc is the same as in the conventional example, the power supply 'iT+: voltage vc
It becomes c. When the write or erase mode ends, a pulse of "Hs" is applied to the signal DIS for a certain period of time. Therefore, the charge charged in the capacitor added to the output α during the write or erase mode is added to the output 0'. It is discharged to the ground with a time constant determined by the capacitance and the ON resistance of Q121, and the '1lfl voltage of the output O' becomes the power supply voltage Vcc. 4, that is, the on-resistance of Q121 can be controlled by reducing the slippage time term (t43-
t4□] can be set short, and by increasing the ON resistance of Q1□1, the inter-station width [t43-t4□] can be set long.

In the embodiment, in order to set the timerOJ width (t43-t42) short, the on resistance of Q1□1 is sufficiently reduced.For this reason, the capacitance of output 0' is set to 0' in write or erase mode. The speed at which the charged charges are discharged is faster than that of the conventional example, as shown by D2 in FIG. Because of this, the operating characteristics of the decoder circuit do not differ from those of the conventional example.When the voltage of the output O' reaches the power supply voltage Vcc, the signal READ becomes "H71" and the read mode is entered (time t44)0 In the embodiment, the case where the NAND circuit is powered by two people has been explained, but there is no limit to the number of inputs.
EVC'mU6it'1-fcf47'
Although the case of an N-channel type IGFET has been shown, it goes without saying that the present invention can also be applied to an N-channel type IGFET whose gate is connected to the power source CC.

〔Effect of the invention〕

As described above, according to the present invention, the charge originally released to the output during the write or erase mode is discharged by the IGFET with a sufficiently low on-resistance, so that the discharging speed becomes high. Therefore, it becomes easy to design the timing for changing from write or erase mode to read mode. It is also suitable for applications that perform high-speed write-down or erase-read cycles.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional decoder circuit. 2 is a signal waveform diagram of each part to explain the circuit operation of FIG. 1, FIG. 3 is a circuit diagram of a decoder circuit according to an embodiment of the present invention, and FIG. 4 is an explanation of the circuit operation of FIG. 3. Sudameno・
It is a signal waveform diagram. Qllll, Q112゜Ql15
+Q118 +Q12o -P channel type IGFETQ
II3 'QQ10, Q116 'Q1191Q121
""Channel/'Current IGFETQ117...N channel-depression type IGFET 1st figure 21 ・ 11N□1 ・ 2nd figure 4

Claims (1)

[Scope of Claims] A NAND circuit into which a plurality of addresses are input; a first inverting amplifier to which the output of the NAND circuit is connected to the input; and a drain connected to the output of the first inverting amplifier. a first field effect transistor, to which a first voltage is applied during write or erase mode;
a first node to which a second voltage is applied in the read mode; and a first node inserted between the first node and ground, the input being connected to the first node.
a second inverting amplifier connected to the source of the field effect transistor, the source connected to the first node and the gate connected to the second field effect transistor;
a second field effect transistor connected to the output of the inverting amplifier; a source of the first field effect transistor and the second field effect transistor;
The drain of the field effect transistor is connected to the second
and the second field effect transistor, the drain of which is connected to the second node, the gate of which is connected to a signal that conducts for a certain period of time after the write or erase mode ends, and the source of which is connected to ground. a third field-effect transistor of a conductivity type, and the second node is an output.