JPS6421794A - Decoder circuit for semiconductor storage device - Google Patents
Decoder circuit for semiconductor storage deviceInfo
- Publication number
- JPS6421794A JPS6421794A JP17712487A JP17712487A JPS6421794A JP S6421794 A JPS6421794 A JP S6421794A JP 17712487 A JP17712487 A JP 17712487A JP 17712487 A JP17712487 A JP 17712487A JP S6421794 A JPS6421794 A JP S6421794A
- Authority
- JP
- Japan
- Prior art keywords
- ground
- transistor
- discharge current
- time
- storage device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Read Only Memory (AREA)
Abstract
PURPOSE:To prevent the generation of ground noise or latch-up by reducing a discharge current to the ground by inputting a control signal of a lower potential than that at the time when it is written in the gate of a control transistor. CONSTITUTION:As a means for reducing the discharge current to the ground after the end of write, a control transistor TR consisting of an N-channel MOS transistor is added between an inverter 2 and a booster circuit 3. Then, the source electrode of the control transistor TR is connected to the output node 4 of the inverter 2, and an drain electrode is connected to the booster circuit 3, and further, the control signal A is inputted to a gate through a node 5. When the write is finished, a circuit becomes nonselective, and the discharge current flowing at this time is restricted by the on resistance of the transistor, and the discharge of large capacity charge is carried out not instantaneously while taking some time. Thus, the generation of the ground noise or the latch-up can be prevented.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17712487A JP2582791B2 (en) | 1987-07-17 | 1987-07-17 | Decoder circuit of semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17712487A JP2582791B2 (en) | 1987-07-17 | 1987-07-17 | Decoder circuit of semiconductor memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6421794A true JPS6421794A (en) | 1989-01-25 |
JP2582791B2 JP2582791B2 (en) | 1997-02-19 |
Family
ID=16025588
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17712487A Expired - Lifetime JP2582791B2 (en) | 1987-07-17 | 1987-07-17 | Decoder circuit of semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2582791B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03108195A (en) * | 1989-09-21 | 1991-05-08 | Seiko Instr Inc | Semiconductor integrated circuit device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6150289A (en) * | 1984-08-17 | 1986-03-12 | Nec Corp | Decoder circuit |
-
1987
- 1987-07-17 JP JP17712487A patent/JP2582791B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6150289A (en) * | 1984-08-17 | 1986-03-12 | Nec Corp | Decoder circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03108195A (en) * | 1989-09-21 | 1991-05-08 | Seiko Instr Inc | Semiconductor integrated circuit device |
Also Published As
Publication number | Publication date |
---|---|
JP2582791B2 (en) | 1997-02-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term | ||
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071121 Year of fee payment: 11 |