JP2587595B2 - Write circuit for nonvolatile semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write circuit of a nonvolatile semiconductor memory, and more particularly to a write circuit of a nonvolatile semiconductor memory having a configuration in which a plurality of memory cells formed by transistors having a floating gate are arranged.

[0002]

2. Description of the Related Art Before describing a conventional write circuit of a nonvolatile semiconductor memory, first, a write method and a principle of a memory cell formed by a transistor having a floating gate will be described with reference to FIGS. Will be described with reference to a circuit diagram and a schematic sectional view of the memory cell shown in FIG.

When the source S is grounded, a voltage of about 8 V is applied to the drain D, and a voltage of about 12 V is applied to the control gate CV,
The transistor of this memory cell (hereinafter referred to as a memory cell transistor) conducts, and a current flows between the source and the drain D. At this time, in the vicinity of the drain D, a collision separation phenomenon is caused by electrons accelerated by a strong electric field, and hot holes (+) and hot electrons (−) are generated. Some of the hot electrons move in the direction of the floating gate FG due to the electric field caused by the high voltage applied to the control gate CG, and are then captured and stored in the floating gate FG. As a result, the threshold voltage of the memory cell transistor is increased by 2 V before writing.
From the level to about 6 V after writing. Information is stored by the change in the threshold voltage.

When a voltage of about 5 V is applied to the control gate CG of the memory cell transistor before and after writing, the transistor is turned on because the threshold voltage of the memory cell before writing is 2 V and the transistor is turned on. In a later memory cell, the threshold voltage is 6 V, so that the transistor remains off. By determining whether the on state is the off state, the stored information can be read.

Next, a write circuit of a nonvolatile semiconductor memory having a configuration in which a plurality of memory cells formed of transistors having floating gates are arranged will be described with reference to a circuit diagram of FIG. 5 and a waveform diagram of signals of respective parts in FIG. (For example,
JP-A-62-62497).

The write circuit of this non-volatile semiconductor memory is formed of a transistor having a floating gate in a write mode, and has a plurality of memory cells MC (only one is shown in FIG. 5). A drain voltage application circuit 3 for applying a write drain voltage to the drain of the MC, a source, a control gate, etc.), a logic gate G2 for performing NAND processing of the mode signal MOD and the clock signal CK, and one end of the logic gate G2. A capacitor C1 connected to the output terminal of the gate G2, a transistor T receiving the write voltage Vpp at the drain and connecting the gate to the word line WL for selecting the memory cell MC.
1 and a transistor T2 having a drain and a gate connected to the source of the transistor T1 and a source connected to the word line WL, and a word line WL for selecting a memory cell MC selected by the X decoder 1 (hereinafter, a selected word line WL). W
L) and a selected word line voltage supply circuit 2x for supplying a word line voltage for writing.

In this example, when the mode signal MOD changes to a high-level write mode, a signal obtained by inverting the level of the clock signal CK is output to the output terminal (contact point N11) of the logic gate G2. Due to the charge pump operation by T1 and T2, the source voltage of the transistor T2 connected to the word line WL increases. The level of the word line WL (source of T2) is Vpp
When the voltage exceeds + Vt (T1) (Vt (T1) is the threshold voltage of the transistor T1), the boosted charge is released to the write voltage Vpp supply side, so that the level of the word line WL is stabilized at Vpp + Vt (T1). .

In this way, a write voltage of Vpp + Vt (T1) is supplied to the selected word (WL, the control gate of the selected memory cell MC) to reduce the write time. On the other hand, the floating gate voltage V _FG to-gate current I _G characteristics when viewed movement of hot electrons in the memory cell transistor as the gate current I _G is as shown in FIG 7. As can be seen from FIG. 7, the gate current I _G
Has a point that shows the maximum value with respect to the floating gate voltage _VFG ,
Since the writing time is inversely proportional to the gate current I _G, the floating gate voltage V _FG to the write time and the shortest (= V _o) I am present. Assuming that the capacitance between the control gate and the floating gate is C _CF and the capacitance between the floating gate semiconductor substrates is C _FS between the floating gate voltage V _FG and the control gate voltage V _CG , V _FG = V _CG · C _CF / (C _CF + C _FS ) Therefore, increasing the control gate voltage (selected word line voltage) of the memory cell MC does not necessarily shorten the write time. Generally, the point at which the gate current _IG is maximized is that the threshold voltage when the pinch-off phenomenon occurs in the memory cell transistor (hereinafter referred to as “pinch-off”) is Vt (MC), and the drain voltage is V _D (MC). Then, V _FG −Vt (MC) = V _D. The threshold voltage at the time of pinch-off of the memory cell transistor is substantially determined by its structure, dimensions, and the like.

[0009]

The above-described write circuit of the conventional nonvolatile semiconductor memory uses the voltage supplied by the boosting operation of the selected word line voltage supply circuit 2x as Vpp +
While the voltage is boosted to Vt (T1) and supplied to the selected word line, that is, the control gate of the selected memory cell MC, a control gate voltage that maximizes the gate current exists in the memory cell transistor. Therefore, increasing the control gate voltage does not necessarily shorten the write time, and Vt (T1) depends on manufacturing conditions and the like.
In addition, the thickness of the insulating film between the control gate and the floating gate and between the floating gate and the semiconductor substrate of the memory cell transistor may fluctuate, so that it is difficult to minimize the writing time.

An object of the present invention is to provide a writing circuit for a nonvolatile semiconductor memory which can surely minimize the writing time even if the parameters fluctuate due to manufacturing conditions and the like.

[0011]

A writing circuit for a nonvolatile semiconductor memory according to the present invention is a writing circuit for a nonvolatile semiconductor memory in which a plurality of memory cells each formed by a transistor having a floating gate are arranged. A drain voltage application circuit for applying a write voltage to a drain of a transistor of a selected one of the memory cells, and a dummy cell having the same structure and characteristics as those of the memory cell. A floating gate potential for generating a control signal having a first level when the potential is higher than a voltage obtained by adding a threshold voltage in a predetermined state to a drain voltage of the transistor, and a second level otherwise. A detection / control circuit, and when the control signal is at the second level, boosts the supplied voltage to the first level. A selected word line voltage supply circuit including a booster circuit for supplying a selected word line voltage obtained by stopping the boosting operation to a word line connected to a control gate of the memory cell and the transistor of the dummy cell when the boost operation is stopped; And

In addition, the floating gate potential detection / control circuit comprises:
A dummy cell and a drain voltage application circuit for applying a write voltage to a drain of the transistor of the dummy cell;
A comparator for comparing the drain voltage of the transistor of the dummy cell with the floating gate potential and outputting a control signal, wherein the comparator is configured to reduce the input offset voltage by the threshold voltage at the time of pinch-off of the transistor of the dummy cell. It is configured to have.

Further, the size of the transistor of the dummy cell is made larger than that of the transistor of the memory cell.

[0014]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In this embodiment, in the write mode, the drains of a plurality of memory cells MC (only one is shown in FIG. 1) formed of transistors having floating gates (hereinafter, the drains of the memory cells MC are provided at the ends) A drain voltage application circuit 3 for applying a write drain voltage to the source and control gates, and a dummy cell DMC having the same structure, the same dimensions, and the same characteristics as the memory cell MC.
And a drain voltage application circuit DVS for applying a write drain voltage to the drain of the dummy cell DMC, and a floating gate potential Vfg and a drain voltage V of the dummy cell DMC.
Comparator CM comparing d with an input offset voltage by the threshold value at the pinch-off time of the dummy cell transistor
P and the potential of the floating gate of the dummy cell DMC becomes the drain voltage and the threshold voltage Vt (DMC) at the time of pinch-off.
, A floating gate potential detection / control circuit 21 that generates a control signal CNT that is at a first level (low level) when the voltage is higher than the voltage added thereto, and a second level (high level) otherwise. A logic gate G1 that performs NAND processing of the signal MOD, the clock signal CK, and the control signal CNT, a capacitor C1 that has one end connected to the output end of the logic gate G1, and a drain that receives the write voltage Vpp at the drain and sets the gate to a word for selecting the memory cell MC A transistor T1 connected to the line WL and a transistor T2 having a drain and a gate connected to the source of the transistor T1 and a source connected to the word line WL. When the control signal CNT is at the second level, the supplied voltages (CK, Vpp ) Is boosted and the selected word line voltage obtained by stopping the boosting operation at the first level is obtained. -Option word line (WL), i.e. has a configuration and a selected word line voltage supply circuit 2 which includes a booster circuit 22 to the control gates of the memory cells MC and dummy cells DMC in the selected state.

Next, the operation of this embodiment will be described with reference to the waveform diagrams of the signals of the respective parts shown in FIG.

First, when the mode signal MOD enters a high-level write mode, the drain (V
d) immediately becomes the write drain voltage (about 8 V). Potential of floating gate of dummy cell DMC (Vfg)
Is determined by dividing the potential of the control gate by the capacitance between the control gate and the floating gate and the capacitance between the floating gate and the semiconductor substrate. At this time, the potential is lower than the power supply voltage (5 V). Is high, and the logic gate G1 outputs a level inversion signal of the clock signal CK. As a result, a boosting operation is performed by the boosting circuit 22, and the potential of the word line WL, that is, the control gate of the memory cell MC and the dummy cell DMC rises.

When the potential of the word line WL rises, the potential of the floating gate of the dummy cell DMC also rises in proportion thereto,
When the potential of the floating gate exceeds Vd + Vt (DMC), the control signal CND becomes a constant level, the output (N1) of the logic gate G1 is fixed at a high level, and the boosting circuit 22 stops the boosting operation. As a result, the potential of the word line WL gradually decreases, and the potential of the floating gate also decreases in proportion thereto. When the potential of the floating gate drops below Vd + Vt (DMC), the control signal CNT goes high, and the booster circuit 22 performs the boosting operation again. I do.

By repeating the above operation, the potential of the word line WL becomes the drain voltage V of the dummy cell DMC.
d is a threshold voltage Vt (D
MC) and the floating gate voltage Vfg is fixed to be equal. As a result, the gate current Ig
Can be kept maximum, and the writing time can always be minimized.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention. This embodiment is different from the first embodiment shown in FIG. 1 in that the dummy cell DMCa has the same structure and characteristics as the first embodiment.
By forming the same size as the dummy cell DMC of the embodiment of FIG.
The effect of the parasitic capacitance of the wiring between the input terminals of the comparator CMP is reduced so that the floating gate potential can be detected more accurately.

The basic operation and other functions and effects of this embodiment are the same as those of the first embodiment, and further description will be omitted.

In these embodiments, the threshold voltage Vt at the time of pinch-off of the dummy cells DMC and DMCa is
Although (DMC) and Vt (DMCa) are given to the comparator CMP by the input offset voltage, they can be given by other methods, for example, a method of providing a bias circuit at the input terminal of the comparator CMP. The overall circuit configuration is also shown in FIGS.
However, the present invention is not limited to this.

[0024]

As described above, the present invention includes a dummy cell having the same structure and the same characteristics as a memory cell, detects the floating gate potential of the dummy cell, and changes the floating gate potential to a drain voltage in a predetermined state of the dummy cell, for example. Since the control gate potentials of the memory cell and the dummy cell are controlled so as to be equal to the voltage obtained by adding the threshold voltage at the time of pinch-off, even if the parameters fluctuate due to fluctuations in manufacturing conditions, etc. Writing can be performed with the maximum gate current, so that there is an effect that the writing time can always be minimized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform chart of signals of respective parts for explaining the operation of the embodiment shown in FIG. 1;

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

4A and 4B are a circuit diagram and a schematic cross-sectional view of a memory cell for describing a writing method and a principle of a memory cell formed using a transistor having a floating gate.

FIG. 5 is a circuit diagram showing an example of a conventional write circuit of a nonvolatile semiconductor memory.

FIG. 6 is a waveform chart of signals of respective parts for explaining the operation of the write circuit of the nonvolatile semiconductor memory shown in FIG. 5;

FIG. 7 is a characteristic diagram of a gate current with respect to a floating gate potential during a write operation of a transistor having a floating gate.

[Explanation of symbols]

 Reference Signs List 1 X decoder 2, 2a, 2x Selected word line voltage supply circuit 3 Drain voltage application circuit 21, 21a Floating gate potential detection / control circuit 22 Boost circuit C1 Capacitor CMP comparator DMC, DMCa dummy cell DVS Drain voltage application circuit G1, G2 Logic Gate MC Memory cell T1, T2 Transistor WL Word line

Claims (4)

(57) [Claims] 1. A writing circuit of a nonvolatile semiconductor memory in which a plurality of memory cells each including a transistor having a floating gate are arranged, wherein a write circuit of a transistor of a memory cell in a selected state among the plurality of memory cells is provided. A drain voltage application circuit for applying a write voltage; and a dummy cell having the same structure and the same characteristics as the memory cell, and a threshold when a potential of a floating gate of a transistor of the dummy cell is in a predetermined state to a drain voltage of the transistor. A floating gate potential detection / control circuit for generating a control signal having a first level when the voltage is higher than the sum of the voltage values, and a second level otherwise; and when the control signal is at a second level. Boosts the supplied voltage and stops the boosting operation when the voltage is at the first level. A writing circuit for a non-volatile semiconductor memory, comprising: a selected word line voltage supply circuit including a memory cell in a selected state and a booster circuit for supplying a word line connected to a control gate of a transistor of the dummy cell. 2. A floating gate potential detection / control circuit compares a dummy cell and a drain voltage application circuit for applying a write voltage to a drain of a transistor of the dummy cell with a drain voltage of the dummy cell transistor and a floating gate potential. 2. A write circuit for a nonvolatile semiconductor memory according to claim 1, further comprising a comparator for outputting a control signal. 3. The write circuit for a nonvolatile semiconductor memory according to claim 2, wherein the comparator has an input offset voltage corresponding to a threshold voltage when the transistor of the dummy cell is in a predetermined state. 4. The write circuit according to claim 1, wherein the size of the transistor of the dummy cell is larger than that of the transistor of the memory cell.