JPH1011989A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can realize s high speed operation under a low voltage and prevent generation of a leak current in the operation mode under a high voltage. SOLUTION: This device comprises a level converting circuit 11 which is structured by PMOS transistors PT1, PT2, NMOS transistors NT1, NT2 and an inverter INV1, an output buffer 12 which is structured by PMOS transistor PT3 and NMOS transistor NT3 and an operation voltage supply circuit 13 which receives an operation mode signal SMOD indicating read, write and erase operation to supply an operation voltage Vpp and back bias voltages VBp, VBn preset to the voltage values depending on the operation mode to the corresponding supply terminals TVPP, TVBP and TVBn . During the write and erase mode where a high voltage is applied, the back bias voltages VBp, VBn having the absolute value which is larger than the operation voltage different from that in the read operation are supplied to a substrate of the transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having different operation voltages according to operation modes.

[0002]

2. Description of the Related Art In recent years, electrically rewritable flash EEPROMs have been actively developed and put to practical use. In this flash EEPROM, a writing operation is performed by generating channel hot electrons (CHE), and an erasing operation is performed by inducing a Fowler-Nordheim (FN) tunneling phenomenon. There is a type that utilizes the phenomenon. These flash EE
In the PROM, the writing operation and the erasing operation are performed using a high voltage V _{PP of} 12V to 20V or a negative high voltage V _BB of -6V to -20V which is different from the power supply voltage V _{CC of} 5V, for example. .

[0003] Flash EE of the type using CHE
In the PROM, two power supplies, a power supply for a voltage V _CC and a power supply for a high voltage V _PP are used. On the other hand, in a flash EEPROM of the type utilizing the FN tunneling phenomenon,
Only a single power supply for the voltage V _CC is used as the power supply, and an internal boosted power supply is used for the high voltages V _PP and V _BB .

[0004] By the way, the flash EEPROM described above is used.
In the case of M, there is a strong demand for low-voltage operation as in other semiconductor memories, and stable operation can be achieved even when the power supply voltage V _CC is lowered to 5 V to 3 V, and even 1.5 V. Required. And the power supply voltage V _CC and the high voltage V _PP ,
A circuit for supplying V _{BB to} the memory unit is composed of, for example, a MOS-based circuit including a CMOS inverter or the like. For example, the power supply voltage V _CC is higher 3V may or normal MOS transistors similar to about 0.7V, when the power supply voltage V _CC is considered the operation when the 1.5V, as the threshold voltage Vth , 0.5 V or less.

[0005]

However, as described above, in a flash EEPROM, high voltages V _PP and V _BB such as 12 V and −10 V are applied during a write operation and an erase operation. If the threshold voltage Vth of a transistor that handles such a voltage is simply reduced, there is a disadvantage that a so-called sub-threshold and a leak current due to punch-through flow.

FIGS. 7 and 8 show a sub-threshold current and a punch-through current which cause a leak current.
FIG. 7 is a diagram for explaining the sub-threshold current I _SUB , and FIG. 8 is a diagram for explaining the punch-through current I _PTH . In these figures, an n-channel MOS (NMOS) transistor NT is taken as an example as shown in FIG.

As shown in FIG. 7B, when the threshold voltage Vth is lowered due to the sub-threshold current I _SUB ,
Even if the gate voltage VG is 0 V, a slight current flows. Then, the sub-threshold current I
_{Since SUB} increases when the drain voltage VD is increased, the problem further increases during the writing operation and the erasing operation in which the high voltages V _PP and V _BB are applied.

Further, as shown in FIG. 8, the punch-through withstand voltage generally decreases, so that the leakage current increases as compared with the case where the threshold voltage Vth is high. However, punch-through is not a problem since it can be counteracted by ion-implanting impurities into a deep portion of the substrate.

FIG. 9 shows a leakage current _Ilk corresponding to a supply voltage, taking a CMOS inverter as an example. FIG.
(A) shows a p-channel M constituting a CMOS inverter.
0 V is supplied to the gates of the OS (PMOS) transistor PT1 and the NMOS transistor NT1,
12V is supplied to the source of the transistor PT1, and NM
This is a case where the source of the OS transistor NT1 is grounded. In this case, a leak current _Ilk flows through the NMOS transistor NT1.

FIG. 9B shows a PMOS transistor PT.
1 and 12V to the gate of the NMOS transistor NT1
Is supplied to the source of the PMOS transistor PT1.
2V is supplied, and the source of the NMOS transistor NT1 is grounded. In this case, a leakage current _Ilk flows through the PMOS transistor PT1.

FIG. 9C shows a PMOS transistor PT.
-10 at the gate of the NMOS transistor NT1
V is supplied, 1.5V is supplied to the source of the PMOS transistor PT1, and -10V is supplied to the source of the NMOS transistor NT1. In this case, a leak current _Ilk flows through the NMOS transistor NT1.

FIG. 9D shows a PMOS transistor PT.
1 and 1.5 to the gate of the NMOS transistor NT1.
V is supplied, 1.5V is supplied to the source of the PMOS transistor PT1, and -10V is supplied to the source of the NMOS transistor NT1. In this case, a leakage current _Ilk flows through the PMOS transistor PT1.

The leakage current is 12 V in a dual power supply type flash EEPROM using CHE.
The use of an external power supply is limited to lowering the voltage for reading only, so there is not much problem. However, a single power supply type flash EEPROM that uses the FN tunneling phenomenon for both writing and erasing uses an internal boosted power supply. In addition, since the writing operation and the erasing operation are performed at a low voltage, this poses a serious problem. That is, it is necessary to compensate for the leakage current by the booster circuit, and there is a problem that the area of the booster circuit and the power consumption are increased. Hereinafter, this problem will be considered more specifically.

As the power supply voltage decreases, the power supply voltage V _CC becomes 1.
When the voltage becomes 5 V, the threshold voltage Vth of the transistor
Must be 0.5 V or less, which is lower than 0.7 V of a normal transistor, as described above. For example,
Assuming that a worst case leakage current of 1 nA per 1 μm of transistor width (W) flows when a high voltage of 12 V is applied with Vth = 0.4 V ± 0.1 V, a word line is applied to a row decoder and a Y gate. W = 60μm per 1024 lines, W = 40μ per 1024 bit lines
If page writing is performed assuming that a transistor of m is used, a leakage current of about 100 μA will flow. It is difficult to cover this with a booster circuit.

Further, when the clock frequency for driving the booster circuit is 10 MHz and the gate oxide film thickness of the high-voltage transistor system is 30 nm, at least 100 μm square (10
20 stages of charge pumps having a capacitor of pF) are required. Consider a low voltage operation of a single power supply type flash EEPROM using the FN tunneling phenomenon for both writing and erasing. Here, it is assumed that high-speed reading (tAA ≦ 150 ns) is performed at V _CC ≦ 2 V. In this case, first, considering the read operation, it is desirable to lower the threshold voltage Vth as much as possible. However, when writing and erasing,
As described above, the threshold voltage Vth cannot be reduced because a high voltage such as 12 V or -10 V is applied to the high voltage transistors forming the decoder, the Y gate, and the like.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of realizing high-speed operation under a low voltage and preventing generation of a leak current in an operation mode under a high voltage. Is to do.

[0017]

In order to achieve the above object, the present invention has at least two operation modes, a first operation voltage is supplied in a first mode, and a first operation voltage is supplied in a second mode. A semiconductor device to which a second operating voltage is supplied, wherein at least one insulated gate type electric field that keeps an operating voltage supply terminal and an output terminal conductive or non-conductive according to a voltage applied to a gate terminal. An effect transistor, and in the second mode, when the absolute value of the second operating voltage is larger than the absolute value of the first operating voltage, the substrate of the insulated gate field effect transistor is provided with the first transistor.
And a voltage supply means for supplying a back bias voltage having an absolute value larger than that in the mode.

According to the present invention, in the first operation mode, the threshold voltage of the transistor is maintained as it is, and in the second operation mode in which the operation voltage is high, the voltage supply means applies, for example, to the substrate of the transistor. A back bias voltage having an absolute value larger than the second operation voltage is applied. Thus, the threshold voltage of the transistor is set higher than in the first operation mode. As a result, the operation at a low voltage can be performed at a high speed, or the operation low voltage limit can be further reduced. On the other hand, in the second operation mode, the leak current can be reduced, so that the area of the booster circuit and the power consumption can be reduced.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of the semiconductor device according to the present invention. As shown in FIG. 1, the semiconductor device 10 includes a cascaded level conversion circuit 11, an output buffer 12, and an operating voltage supply circuit 13.

The level conversion circuit 11 is a p-channel MOS
(PMOS) transistors PT1 and PT2, n-channel MOS (NMOS) transistors NT1 and NT2, and an inverter INV1. Threshold voltage Vth of PMOS transistors PT1, PT2 and NMOS transistors NT1, NT2 is, for example, 1.5 when power supply voltage V _CC is lower than normal 5V.
In the case of V, it is set to 0.3 V to 0.5 V, for example, 0.4 V. The PMOS transistors PT1, PT2 and the NMOS transistors NT1,
NT2 is formed of a high withstand voltage system in which, for example, a channel type transistor of either PMOS or NMOS is formed as a transistor in a so-called triple well. On the other hand, the inverter INV1 is configured by a V _CC system.

PMOS transistors PT1 and PT2
Is connected to the supply terminal T _VPP of the operating voltage V _PP ,
The sources of the NMOS transistors NT1 and NT2 are grounded. PMOS transistor PT1 and NMOS
The drains of the transistors NT1 are connected to each other, and the connection point N1 is connected to the gate of the PMOS transistor PT2. The drains of the PMOS transistor PT2 and the NMOS transistor NT2 are connected to each other, and the connection point N2 is connected to the gate of the PMOS transistor PT1 and to the output buffer 12. The gate of the NMOS transistor NT1 has the start signal V
i is connected to the input terminal T _Vi , the connection point is connected to the input terminal of the inverter INV1, and the output terminal of the inverter INV1 is connected to the gate of the NMOS transistor NT2. Then, the PMOS transistors PT1, P
The substrate of T2 is a supply terminal T of the back bias voltage VBp.
_VBp , and NMOS transistors NT1, NT2
Substrate is the supply terminal T _VBn of the back bias voltage _VBn.
It is connected to the.

The output buffer 12 comprises a PMOS transistor PT3 and an NMOS transistor NT3. The threshold voltage Vth of these PMOS transistor PT3 and NMOS transistor NT3
Is set to 0.3 V to 0.5 V, for example, 0.4 V, corresponding to the case where power supply voltage V _CC is lower than the normal 5 V, for example, 1.5 V. The PMOS transistor PT3 and the NMOS transistor NT3
Is configured with a high breakdown voltage system in which any channel type transistor is formed as a transistor in a so-called triple well.

PMOS transistor PT3 and NMO
The gate of S transistor NT3 is connected to output node N2 of level conversion circuit 11, and PMOS transistor PT
3 source connected to the operating voltage V _PP for supply terminal T _VPP, the source of the NMOS transistor NT3 are grounded. Then, the PMOS transistors PT3 and NM
The drains of the OS transistors NT3 are connected to each other, and the connection point N3 is connected to the output terminal T _OUT .

Operating voltage supply circuit 13 has a booster circuit composed of, for example, a charge pump and receives an operation mode signal _SMOD composed of, for example, 2 bits indicating a read, write, and erase operation, and responds to the operation mode. Operating voltage V _PP set to voltage value, back bias voltage VB
p, VBn to corresponding supply terminals T _VPP , T _VBp , T _{VB n}
To supply. Specifically, in the read mode, the operating voltage V _PP is set to 1.5 V, which is the power supply voltage V _CC , the back bias voltage VBp is set to 1.5 V, which is also the power supply voltage V _CC , and the back bias voltage VBn is set to 0 V. Set and supply.
In the writing mode and the erasing mode, the operating voltage V _PP is 12 V, which is sequentially raised from the power supply voltage V _CC , the back bias voltage VBp is, for example, 13 V higher than the operating voltage V _PP by 1 V to 4 V, and the back bias voltage VBn is 0 V. 1V
It is supplied by setting it to -4V lower, for example, -1V.

Next, the operation of the above configuration will be described with reference to the timing chart of FIG. First, at the time of reading, the start signal Vi is set to the ground level (0 V) and input to the input terminal T _Vi , and the mode signal S _MOD indicating the read mode is input to the operating voltage supply circuit 13.

In the level conversion circuit 11 to which the start signal Vi has been input, the start signal Vi is supplied to the NMOS transistor NT1.
And the start signal Vi is supplied to the inverter INV
The signal of V _CC level (1.5 V) inverted by 1 is NMO
It is supplied to the gate of the S transistor NT2. As a result, the NMOS transistor NT1 is kept off, and the NMOS transistor NT2 is kept on. As a result, the node N2 is pulled to the ground level,
The PMOS transistor PT1 whose gate is connected to the node N2 transitions to the conductive state. At this time, since the NMOS transistor NT1 is held in a non-conductive state, the level of the node N1 is held at the level of the operating voltage V _PP to the supply terminal _TVPP .

In the operating voltage supply circuit 13, the operating voltage V _PP
And the back bias voltage VBp is set to the power supply voltage V _CC level of 1.5 V, and the supply terminals T _VPP and T _VBp
, And the back bias voltage VBn is set to the ground level (0 V) and supplied to the supply terminal _TVBn . Therefore, the level of node N1 is the level of power supply voltage V _CC ,
The level of node N2 is kept at the ground level. The ground level of the node N2 is supplied to the gates of the PMOS transistor PT3 and the NMOS transistor NT3 of the output buffer 12. As a result, the PMOS transistor PT3 is kept conductive, and the NMOS transistor N
T3 is kept in a non-conductive state. As a result, the node N3
There drawn to V _CC level, V _CC level voltage Vo is outputted from an output terminal T _OUT.

At the time of writing or erasing, the start signal V
i is set to the V _CC level (1.5 V) and the input terminal T _Vi
And a mode signal S _MOD indicating the write mode or the erase mode is input to the operating voltage supply circuit 13.

In the level conversion circuit 11 to which the start signal Vi is input, the start signal Vi is applied to the NMOS transistor NT as shown in FIG.
1 and the start signal Vi is supplied to the inverter IN
The ground level (0V) signal inverted by V1 is NMOS
It is supplied to the gate of the transistor NT2. As a result, the NMOS transistor NT1 is held in a conductive state, and the NMOS transistor NT2 is held in a non-conductive state. As a result, the level VN1 of the node N1 is pulled down to the ground level, and the gate of the node N1 connected to the node N1
OS transistor PT2 transitions to the conductive state. At this time, since the NMOS transistor NT2 is held in the nonconductive state, the level VN2 at the node N2 will be held at the level of the operating voltage V _PP to the supply terminal T _VPP.

In the operating voltage supply circuit 13, after that, a booster circuit (not shown) is started (actually, the time for which the logic circuit operates is much faster than the time for boosting, so it is good to operate at the same time), the operating voltage V _PP , the back bias voltage VBp and VBn are raised or lowered to a predetermined level. Specifically, as shown in FIG.
_PP is set to 12 V, the back bias voltage VBp is set to 13 V, the back bias voltage VBn is set to -1 V, and supplied to the supply terminals T _VPP , T _VBp , and T _VBn , respectively. Therefore, the PMOS transistors PT1 to PT
The substrate 3 has a voltage V higher than the source voltage V _PP (12 V).
Bp (13 V) is applied, and the NMOS transistor NT
A voltage VBn (-1 V) lower than the source voltage GND (0 V) is applied to the substrates 1 to NT3. At this time, in the level conversion circuit 11, the level VN2 of the node N2 rises to the operating voltage V _PP level as shown in FIG. 2C without flowing a DC (direct current) current.

The _Vcc level of the node N2 is set to the level of the PMOS transistors PT3 and NM of the output buffer 12.
It is supplied to the gate of the OS transistor NT3. As a result, the PMOS transistor PT3 is maintained in a non-conductive state, and the NMOS transistor NT3 is maintained in a conductive state. As a result, the node N3 is pulled to the ground level, and the ground level voltage Vo is output from the output terminal _TOUT .

In this case, the leakage current is a concern
Transistors PT1 and NT to be held in a non-conductive state
2, PT3, and these transistors are set to 0.3 V to 0.5 V by the back bias of VBB (p channel) and VBB (n channel) by the back bias voltages VBp and VBn. Since the threshold voltage Vth has risen from 0.6V to 0.8V,
No leak current flows.

As described above, according to the present embodiment, the p-channel MOS (PMOS) transistor PT
1, PT2, n-channel MOS (NMOS) transistors NT1 and NT2, and a level conversion circuit 11 composed of an inverter INV1, an output buffer 12 composed of a PMOS transistor PT3 and an NMOS transistor NT3, and read, write, and erase. Upon receiving the operation mode signal S _MOD indicating the operation, the operation voltage V _PP and the back bias voltages VBp, VBn set to the voltage values corresponding to the operation mode are supplied to the corresponding supply terminals T _VPP , T _VBp , T _VBn . Operating voltage supply circuit 1
3, the back bias voltages VBp and VBn different from those in the reading operation can be supplied to the substrate of the transistor in the writing and erasing modes in which a high voltage is applied. , The threshold voltage Vth can be set higher, for example, reading at a low voltage of 3 V or less can be performed at a high speed, or the operating low voltage limit can be further reduced. On the other hand, at the time of writing and erasing, since the leak current from the boosted power supply can be reduced, there is an advantage that the area of the boosted circuit and the power consumption can be reduced.

Second Embodiment FIG. 3 is a circuit diagram showing a second embodiment of the semiconductor device according to the present invention. The difference between the second embodiment and the first embodiment is that the semiconductor device 10 of the first embodiment is different from the first embodiment.
Is capable of supplying a positive high voltage, whereas the semiconductor device 10A is configured as a circuit capable of supplying a negative high voltage.

Specifically, in the level conversion circuit 11A, the gate of the PMOS transistor PT1 is connected to the input terminal T
_Vi, and the gate of the PMOS transistor PT2 is connected to the output of the inverter INV1. Also, N
The gate of the MOS transistor NT1 is connected to the node N2, and the gate of the NMOS transistor NT2 is connected to the node N2.
1 connected. And the PMOS transistor P
The sources of T1, PT2 and PT3 are connected to the supply terminal T _VCC of the power supply voltage V _CC and the NMOS transistor NT
1, the sources of NT2 and NT3 are connected to the supply terminal T _VEW of the negative operating voltage V _EW .

In the read mode, the operating voltage supply circuit 13A changes the operating voltage _VEW to the ground level of 0V,
The back bias voltage VBn is set to 0 V, and the back bias voltage VBp is set to 1.5 V, which is the power supply voltage V _CC , and supplied. In the writing mode and the erasing mode, the operating voltage V _{EW is set} to −10 V, and the back bias voltage V
Bn is 1 V to 4 V lower than the operating voltage V _EW , for example, -1.
1 V, and the back bias voltage VBp is set and supplied at 1 V to 4 V higher than the power supply voltage V _CC , for example, 2.5 V.

Next, the operation of the above configuration will be described with reference to the timing chart of FIG. In the first embodiment, when the activation signal Vi is at the ground level, reading is performed and V _CC is read.
Although the description has been given of the case of the write / erase mode when the level is at the level, in the second embodiment, the activation signal V
i is selected when the V _CC leveling le, that the non-selection when the ground level, for example, shown for the decoder circuit. Therefore, the start signal Vi is used for both reading, writing and erasing.
Is at the V _CC level. First, at the time of reading, the start signal Vi is set to the V _CC level (1.5 V) and input to the input terminal T _Vi , and the mode signal S _MOD indicating the read mode is input to the operating voltage supply circuit 13A. .

In the level conversion circuit 11A to which the start signal Vi has been input, the start signal Vi is applied to the PMOS transistor PT.
1 and the start signal Vi is supplied to the inverter IN
The ground level (0V) signal inverted by V1 is a PMOS
The signal is supplied to the gate of the transistor PT2. As a result, the PMOS transistor PT1 is maintained in a non-conductive state, and the PMOS transistor PT2 is maintained in a conductive state. As a result, the node N2 is maintained at the power supply voltage V _CC level, and the NMOS transistor NT1 transitions to the conductive state.

In the operating voltage supply circuit 13A, the operating voltage V
_EW and the back bias voltage VBn are set to 0 V and supplied to the supply terminals T _VEW and T _VBn , and the back bias voltage VBp is set to the power supply voltage V _CC level (1.5 V) and supplied to the supply terminal T _VBp Is done. Therefore,
The level of the node N1 is held at the ground level,
Transistor NT2 is stably maintained in a non-conductive state.
The V _CC level of the node N2 is equal to the PM level of the output buffer 12A.
OS transistor PT3 and NMOS transistor N
It is supplied to the gate of T3. As a result, the PMOS transistor PT3 is maintained in a non-conductive state, and the NMOS transistor NT3 is maintained in a conductive state. As a result, the node N3 is pulled to the ground level, and the ground level voltage Vo is output from the output terminal _TOUT .

At the time of writing or erasing, the start signal V
i is set to the V _CC level (1.5 V) and the input terminal T _Vi
And a mode signal S _MOD indicating the writing mode or the erasing mode is input to the operating voltage supply circuit 13A.

In the level conversion circuit 11 to which the start signal Vi is input, the start signal Vi is applied to the PMOS transistor PT as shown in FIG.
1 and the start signal Vi is supplied to the inverter IN
The ground level (0V) signal inverted by V1 is a PMOS
The signal is supplied to the gate of the transistor PT2. As a result, the PMOS transistor PT1 is maintained in a non-conductive state, and the PMOS transistor PT2 is maintained in a conductive state. As a result, the level VN2 of the node N2 becomes the power supply voltage V
N is pulled up to _CC and the gate is connected to node N2.
MOS transistor NT1 transitions to the conductive state.

In the operation voltage supply circuit 13A, FIG.
As shown in the figure, the operating voltage V _EW is set to −10 V, the back bias voltage VBn is set to −11 V, the back bias voltage VBn is set to 2.5 V, and the supply terminals T _VPEW , T _VBn , and T _VBp are respectively set. Supplied. Therefore, P
A voltage VBp (2.5 V) higher than the source voltage V _PP (1.5 V) is applied to the substrates of the MOS transistors PT 1 to PT 3, and lower than the source voltage V _EW (−10 V) to the substrates of the NMOS transistors NT 1 to NT 3. Voltage VBn
(−11 V) is applied. At this time, in the level conversion circuit 11, the node N
2 rises to the power supply voltage V _CC level as shown in FIG. 4C. Then, as described above, with that level VN2 at the node N2 becomes V _CC level, NMOS transistor NT1 transitions to the conductive state,
The level VN1 of the node N1 drops to -10V. As a result, the NMOS transistor NT2 is stably held in the non-conductive state.

The V _CC level of the node N2 is set to the level of the PMOS transistors PT3 and N of the output buffer 12A.
It is supplied to the gate of the MOS transistor NT3. As a result, the PMOS transistor PT3 is maintained in a non-conductive state, and the NMOS transistor NT3 is maintained in a conductive state. As a result, node N3 drops to -10V,
A voltage Vo having a negative high voltage level (−10 V) is output from the output terminal T _OUT .

Also in this case, there is a concern about leakage current because the transistors PT1 and PT1, which are to be kept in a non-conductive state,
These transistors are NT2 and PT3, and these transistors are set to 0.3 V to 0.5 V by the back bias of VBB (p channel) and VBB (n channel) by the back bias voltages VBp and VBn. Since the threshold voltage Vth has risen from 0.6 V to 0.8 V, no leak current flows.

According to the second embodiment, the first
The same effect as that of the embodiment can be obtained.

Third Embodiment FIG. 5 is a circuit diagram showing a third embodiment of the semiconductor device according to the present invention. The difference between the third embodiment and the first embodiment is that the first embodiment has a positive high voltage V _pp.
Is a circuit that can supply only negative high voltage V _EW
Is also a circuit that can supply the same. The present semiconductor device 10
In B, between the level conversion circuit 11 and the output buffer 12, the PMOS transistors PT1B, PT2B and N
The level conversion circuit 11B including the MOS transistors NT1B and NT2B is cascaded.

In the level conversion circuit 11B, the PMO
The sources of the S transistors PT1B and PT2B are connected to the supply terminal T _VPP of the operating voltage V _PP , and the sources of the NMOS transistors NT1B and NT2B are connected to the supply terminal T _VEW of the operating voltage V _EW . PMOS transistor PT
1B is connected to the node N1 of the level conversion circuit 11, the gate of the PMOS transistor PT2B is connected to the node N2, and these transistors PT1B, PT2
The substrate B is a supply terminal T for the back bias voltage VBp.
_Connected to _VBp . PMOS transistor PT1B
And a connection point between the drain operation of the NMOS transistor NT1B and the node N1B.
It is connected to the gate of the OS transistor NT2B.
A node N2B is formed by a connection point of the drain operation of the PMOS transistor PT2B and the NMOS transistor NT2B, and the node N1B is connected to the NMOS transistor NT1.
B and the output buffer 1
2 are connected to the gates of a PMOS transistor PT3 and an NMOS transistor NT3 as input terminals. The substrates of the NMOS transistors NT1B and NT2B of the level conversion circuit 11B and the output buffer 12
The substrate of the NMOS transistor NT3 is connected to a supply terminal T _VBnB back bias voltage VBnB.

In the read mode, the operating voltage supply circuit 13B sets the operating voltage V _PP to the power supply voltage V _CC .
5V, 0V is ground level the operating voltage V _EW, a back-bias voltage VBp power supply voltage V _CC 1.5V, a back bias voltage VBn to 0V, and the back bias voltage VBnB also set to 0V Supply. In the writing mode and the erasing mode, the operating voltage V _PP is increased to 12 V by sequentially _{increasing the} power supply voltage V _CC , and the operating voltage V _{EW is set} to −10.
V, the back bias voltage VBp is set at 1 from the operating voltage V _PP.
V to 4V higher, for example, 13V, back bias voltage V
1 v to 4 v lower than 0V to Bn e.g. -1 V, 1 v to 4 v from operating the back-bias voltage VBnB voltage V _EW
It is supplied at a low setting, for example, -11V.

Next, the operation of the above configuration will be described with reference to the timing chart of FIG. First, at the time of reading, the start signal Vi is set to the V _CC level (1.5 V) and input to the input terminal T _Vi , and the mode signal S _MOD indicating the read mode is input to the operating voltage supply circuit 13. .

In the level conversion circuit 11 to which the start signal Vi has been input, the start signal Vi is applied to the NMOS transistor NT1.
And the start signal Vi is supplied to the inverter INV
The signal of the ground level (0 V) inverted by 1 is supplied to the gate of the NMOS transistor NT2. This allows
NMOS transistor NT1 is kept conductive, and N
MOS transistor NT2 is kept off.
As a result, the node N1 is pulled to the ground level, the gate is connected to the node N1, and the PMOS transistor PT
1 transitions to the conductive state. At this time, since the NMOS transistor NT2 is kept in a non-conductive state, the level of the node N2 is set to the operating voltage V _PP to the supply terminal _TVPP .
Level.

In the operating voltage supply circuit 13, the operating voltage V _PP
And the back bias voltage VBp is set to the power supply voltage V _CC level of 1.5 V, and the supply terminals T _VPP and T _VBp
, The back bias voltage VBn is set to the ground level (0 V) and supplied to the supply terminal T _VBn , and the operating voltage V _EW and the back bias voltage VBnB
_Are set to the ground level (0 V) and supplied to the supply terminals T _VEW and T _VBnB . Therefore, the level of node N2 is maintained at power supply voltage V _CC level. Level of the node N1 in the ground level is supplied to the gate of the PMOS transistor PT1B the next stage of the level conversion circuit 11B, the level of the node N2 in the power supply voltage V _CC level PMOS
The signal is supplied to the gate of the transistor PT2B. As a result, in the level conversion circuit 11B, the PMOS transistor PT1B is held in a conductive state, and the PMOS transistor PT2B is held in a non-conductive state. Thus, the node N1B rises to V _CC level, NMOS transistor NT2B transitions to the conductive state, node N2B is pulled to the ground level, NMOS transistor NT1
B is stably held in a non-conductive state.

The ground level of node N2B is supplied to the gates of PMOS transistor PT3 and NMOS transistor NT3 of output buffer 12. This allows
PMOS transistor PT3 is kept conductive, and N
MOS transistor NT3 is kept off.
As a result, the level of the node N3 rises to the V _CC level,
V _CC level voltage Vo is outputted from an output terminal T _OUT.

At the time of writing or erasing, the start signal V
i is set to the V _CC level (1.5 V) and the input terminal T _Vi
And a mode signal S _MOD indicating the write mode or the erase mode is input to the operating voltage supply circuit 13.

In the level conversion circuit 11 to which the start signal Vi has been input, the start signal Vi is applied to the NMOS transistor NT as shown in FIG.
1 and the start signal Vi is supplied to the inverter IN
The ground level (0V) signal inverted by V1 is NMOS
It is supplied to the gate of the transistor NT2. As a result, the NMOS transistor NT1 is kept conductive, and the NMOS transistor NT2 is kept non-conductive. As a result, the level VN1 of node N1 is pulled to the ground level, and the gate is connected to node N1 and PMV
The OS transistor PT1 transitions to the conductive state. At this time, since the NMOS transistor NT2 is held in the nonconductive state, the level VN2 at the node N2 will be held at the level of the operating voltage V _PP to the supply terminal T _VPP.

After that, in the operating voltage supply circuit 13, a booster circuit (not shown) is started (actually, the logic circuit operates much faster than the time for boosting, so it is good to operate simultaneously), and the operating voltages V _PP , V _EW back bias Voltage VB
p, VBn and VBnB are raised to predetermined levels,
Or lowered. Specifically, as shown in FIG. 6B, the operating voltage V _PP is 12 V, the operating voltage V _EW is -10 V,
The back bias voltage VBp is set to 13 V, the back bias voltage VBn is set to -1 V, the back bias voltage VBnB is set to -11 V, and the supply terminals T _VPP , T _VEW , T _VBp , T _VBn , _respectively . It is supplied to _TVBnB . Therefore, the PMOS transistors P1 to P
The source voltage V is applied to the substrates of T3, PT1B and PT2B.
_A voltage VBp (13 V) higher than _PP (12 V) is applied, and a voltage VBn (-1 V) lower than the source voltage GND (0 V) is applied to the substrates of the NMOS transistors NT1 and NT2.
Is applied, and the NMOS transistors NT1B and NT2
A voltage VBnB (-11 V) lower than the source voltage V _EW (-10 V) is applied to the substrates of B and NT3. At this time, in the level conversion circuit 11, the level VN2 of the node N2 rises to the operating voltage V _PP level as shown in FIG. 6C without flowing a DC (direct current) current.

The level of the node N1 at the ground level is equal to the level of the PMOS transistor PT of the next level conversion circuit 11B.
The level of the node N2 supplied to the gate of the transistor 1B and at the level of the power supply voltage V _CC is supplied to the gate of the PMOS transistor PT2B. As a result, in the level conversion circuit 11B, the PMOS transistor PT1B is held in a conductive state, and the PMOS transistor PT2B is held in a non-conductive state. As a result, the node N1B rises to the V _PP level, the NMOS transistor NT2B transitions to the conductive state, the node N2B is pulled to the V _EW level, and NM
OS transistor NT1B is stably held in a non-conductive state. At this time, in the level conversion circuit 11B, the DC (direct current) current is not flown and the level VN1 of the node N1B is applied.
B rises to the operating voltage V _PP level as shown in FIG.

The ground level of the node N2B is equal to the PMOS transistors PT3 and N of the output buffer 12.
It is supplied to the gate of the MOS transistor NT3. As a result, the PMOS transistor PT3 is kept conductive, and the NMOS transistor NT3 is kept non-conductive. As a result, the level of the node N3 rises to V _PP level, V _PP level voltage Vo is outputted from an output terminal T _OUT.

In this case, the leakage current is a concern
Transistors PT1 and NT to be held in a non-conductive state
2, PT2B, NT2B, and NT3. These transistors have back bias voltages VBp and VBp.
VBB (p channel) and VB by Bn and VBnB
B (n-channel) back bias is applied, and 0.3
Since the threshold voltage Vth set to V to 0.5 V has risen to 0.6 V to 0.8 V, no leak current flows.

As described above, according to this embodiment, the same effects as those of the first embodiment can be obtained.

[0060]

As described above, according to the present invention,
The threshold voltage of the transistor can be kept low in the first operation mode of reading, and the threshold voltage can be set high in the second operation mode of writing or erasing with a high operating voltage. (3V or less) can be read at a high speed, or the operating low voltage limit can be further reduced. On the other hand, in the second operation mode, since the leak current from the boosted power supply can be reduced, there is an advantage that the area of the booster circuit and the power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a timing chart at the time of writing and erasing of the circuit of FIG. 1;

FIG. 3 is a circuit diagram showing a second embodiment of the semiconductor device according to the present invention.

FIG. 4 is a timing chart at the time of writing and erasing of the circuit of FIG. 3;

FIG. 5 is a circuit diagram showing a third embodiment of the semiconductor device according to the present invention.

6 is a timing chart at the time of writing and erasing of the circuit of FIG. 5;

FIG. 7 is a diagram for explaining a sub-threshold current that is a source of a leak current.

FIG. 8 is a diagram for explaining a punch-through current as a source of a leak current.

FIG. 9 is a diagram illustrating a leakage current _Ilk according to a supply voltage in a CMOS inverter as an example.

[Explanation of symbols]

10, 10A, 10B ... semiconductor device, 11, 11A, 1
1B: level conversion circuit, 12, 12A: output buffer,
13, 13A, 13B: dynamic voltage supply circuit, PT1 to PT
3, PT1B, PT2B ... PMOS transistor, NT
1 to NT3, NT1B, NT2B ... NMOS transistors, T _VPP , T _VEW ... operating voltage supply terminals, T _VBp , T
_VBn , _TVBnB ... Back bias voltage supply terminal.

Claims (8)

[Claims] 1. A semiconductor device having at least two operation modes, wherein a first operation voltage is supplied in a first mode and a second operation voltage is supplied in a second mode. At least one insulated gate field effect transistor that keeps an operating voltage supply terminal and an output terminal conductive or non-conductive according to a voltage applied to a gate terminal; Voltage supply means for supplying a back bias voltage having an absolute value greater than that in the first mode to the substrate of the insulated gate field effect transistor when the absolute value of the operating voltage is larger than the absolute value of the first operating voltage A semiconductor device having: 2. The semiconductor device according to claim 1, wherein the back bias voltage supplied by the voltage supply means in the second mode is a back bias voltage having an absolute value larger than the second operation voltage. 3. The first operating voltage is a power supply voltage,
2. The semiconductor device according to claim 1, wherein the second operating voltage is higher than a power supply voltage generated by the booster circuit. 4. The semiconductor device according to claim 1, wherein said first operating voltage and said second operating voltage are voltages generated by a booster circuit and higher than a power supply voltage. 5. The first operation voltage is a ground voltage,
2. The semiconductor device according to claim 1, wherein the second operating voltage is a negative voltage generated by a booster circuit. 6. The first operating voltage is a power supply voltage and a ground voltage, and the second operating voltage is a voltage higher than a power supply voltage generated by a booster circuit and a negative voltage generated by the booster circuit. 2. The semiconductor device according to 1. 7. The semiconductor device according to claim 1, wherein said voltage supply means supplies a voltage substantially equal to a first operating voltage to a substrate of said insulated gate field effect transistor in a first mode. 8. The semiconductor device according to claim 1, wherein a threshold voltage of said insulated gate field effect transistor is set lower than a standard threshold voltage.