JPH0969014A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a reference voltage which has superior temperature characteristics and reduces the power consumption by using a voltage boosted in a chip as the source voltage of a band gap generator. SOLUTION: The band gap generator(BGR) operates with a high voltage boosted by a charge pump(CP) and a voltage generated by supplying a current IR to the BGR for a certain time is changed in a capacitor CR (dynamic operation). In this case, when a switch S1 connected to an internal power source terminal VP as the output of the BGR and CP reaches a high level, a source voltage is applied to the BGR. Consequently, a current flows and a voltage is outputted. At this time, a switch S2 connecting the output of the BGR and the capacitor CR is held at a high level to turn on, and the output voltage VBG of the BGR is applied to the capacitor CR. After the switch S2 is held at a low level to turn off, the switch S1 is also held at the low level to turn off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to low power supply voltage operation and low power consumption of a reference voltage generating circuit.

[0002]

2. Description of the Related Art FIG. 11 shows a conventional example. This is 199
3 Symposium on VL SIR KITZ, Digest of Technical Papers, pages 87-88 (1993 SYMPOSIUM ON VLSI C
IRCUITS, pp. 88-89). In this method, the reference voltage is generated using the difference between the threshold voltages of MP1 and MP2, but the switch controlled by f1 and f2 causes the circuit to operate for a certain period of time and the generated voltage is stored in the capacitor CH. Is used as a reference voltage. Since it is a dynamic operation, current is not constantly applied, resulting in low power consumption.

Also, IEEE, Journal of Solid State Circuits, Vol. 24, 1989, No. 597.
Page to page 602 (IEEE, Journal of S
solid-State Circuits, vol. Two
4, pp. 597-602, 1989) in BiCMO.
A bandgap generator using the S process is described.

[0004]

The temperature dependency of the reference voltage generating circuit using the difference in threshold voltage is inferior to that of the bandgap generator, and the process variation is large. For this reason, a bandgap generator is desirable for generating a highly accurate reference voltage. However, as miniaturization and higher integration progress, the power supply voltage becomes 2.5 V or less for higher reliability and lower power consumption. Under such a low power supply voltage, the conventional bandgap generator becomes difficult to operate. The reason is that the ON voltage VBE between the base and emitter of the bipolar transistor is about 0.8 V, which cannot be scaled. In addition, the collector voltage must be sufficiently higher than the base voltage in order to obtain good bipolar characteristics.

Further, in the conventional method described in the above-mentioned second document, a CMOS is used to form a bipolar transistor.
Some processes were added to the process. Therefore, although the temperature characteristic of the bandgap generator is excellent, the cost becomes high, and so-called Bi that realizes excellent performance in both the CMOS and the bipolar transistor is provided.
The CMOS process is adopted only in a specific field such as SRAM for cache.

[0006]

According to the present invention, a power supply voltage of a band gap generator is boosted inside the chip. Further, a switch is provided between the bandgap generator and the power supply, a capacity for level storage is provided, and a switch is also provided between this and the output of the bandgap generator for dynamic operation. Further, the bipolar transistor is formed by using a triple well which is indispensable when a negative voltage is used in a flash memory and electrically isolated so that noise is not induced in a memory cell due to the operation of a peripheral circuit in a DRAM. .

[0007]

With the dynamic operation, the current is supplied for a certain period of time to generate the reference voltage in the level storage capacitor, and the switch is turned off during the other period so that the current does not flow from the internal power supply. A boosted power supply can be used inside a chip.

[0008]

FIG. 1 is a diagram showing a first embodiment of the present invention. BGR is a band gap generator and has excellent temperature characteristics. CP is a charge pump circuit that generates an internal power supply, and CR is a capacitor that holds the output voltage of BGR. Further, S1 is a switch connected to the internal power supply terminal VP which is the output of BGR and CP, and S2 is BGR.
This is a switch that connects the output of the and CR. The voltage of VP is generally higher than the external power supply voltage Vcc. Hereinafter, the BGR, the switch, and the CR are collectively referred to as DBG. The power supply VP is applied to the DBG, the signals of S1 and S2 are input,
VRF is an output terminal. According to this embodiment, the bandgap generator is operated under a high voltage boosted by the charge pump, and the voltage generated by flowing the current IR to the bandgap generator for a fixed time is stored in the capacitor CR (dynamic operation). As a result, the power consumption can be reduced, and the voltage generated by the charge pump, which has a limited drive capability, can be used for operation. Further, since the power supply dependency of the output voltage of the bandgap generator can be minimized, it is not necessary to strictly control CP. Depending on the operating conditions, a high voltage created by a one-shot boost circuit instead of the charge pump circuit may be used. As described above, the features of the present embodiment can be summarized. Since a bandgap generator is used, a reference voltage with excellent temperature characteristics can be obtained. Moreover, since the operation is dynamic, the power consumption is small, which limits the current supply. It is possible to operate at a voltage higher than the external power supply voltage generated by a certain charge pump. In this way, a stable reference voltage can be generated even when the power supply voltage becomes low.

The operation of the first embodiment will be described with reference to FIG. Here, it is assumed that the operation of the present invention is being repeated. For the signals S1 and S2, it is assumed that the switch is turned on at the high level. First, when S1 goes high, a power supply voltage is applied to the bandgap generator. As a result, the bandgap generator operates, a current flows, and a voltage is generated at the output. here,
This switch is turned on by setting S2 to a high level, and the output voltage VBG of the bandgap generator is taken into the capacitor CR (sample). After S2 is set to low level and the switch is turned off, S1 is also set to low level and the switch is turned off.
However, the output voltage of the band gap is maintained in CR. This voltage drops (holds) due to various leak currents. Therefore, the lower limit voltage VBL is determined, and if the holding voltage of CR becomes lower than VBL, the voltage is switched to VBG by switching S1 and S2 again.
I'll go back to. In this way, the current flows in the band gap only during the time from when the voltage of CR becomes lower than the constant value VBL to when it returns to VBG. As a result, low power consumption can be achieved.

Although not shown in FIG. 1, there is actually a comparison circuit using the voltage VRF taken into CR as an input, and the timing of the switches S1 and S2 is determined by comparing with the above VBL. ing.

FIG. 3 is a diagram showing an example of a sectional structure of the present invention. A p-type substrate is used to form a p-well, a p-well among n-wells, and an n-well. The first nMOS is
An n-type high concentration layer is formed as a source and a drain in a p-well in a p-type substrate. A p-type high concentration layer is also formed to apply a voltage to the p well. In the second nMOS, an n-type well region is first formed in the p substrate, and the p-type
A mold well can be created and created in the region of this p-well. In this, n-type high concentration layers are formed as a source and a drain. By doing so, the potential of the p-type well can be set almost independently of the potential of the p-type substrate.
A voltage such that a reverse bias is applied to the p-type substrate and the p-type well may be applied to the n-type region between them. This allows the second nMOS to be independent of the first nMOS.
Negative voltage can be handled by MOS. The pMOS is formed in the n well in the p substrate. A p-type high-concentration layer may be formed as a source and a drain in the n-well, and an n-type high-concentration layer may be formed to apply a voltage to the n-well. With this structure, a bipolar transistor can be formed by utilizing the structure of the second nMOS. That is, an npn bipolar transistor can be formed by using the n-type well region in the p-substrate as the collector, the p-type well in the region as the base, and the n-type high-concentration layer of the MOS as the emitter. As described above, in order to realize the second nMOS structure, a process of forming an n-type well region in the p-substrate and further forming a p-type well therein is required. However, the flash memory already uses this structure because it uses a negative voltage.
Even in AM, triple wells are used for electrical isolation so that noise is not induced in memory cells due to the operation of peripheral circuits. The implementation of the present invention only utilizes this structure and does not increase the process.

An example of voltage application in the case of a flash memory will be described with reference to FIG. 4 to show that there is no process increase in the present invention. The memory cell of the flash memory has a structure as shown in FIG. 4 and has a floating gate and a control gate. Information is read out by injecting or releasing charges from the floating gate and reading the difference in threshold voltage. Here, the operation of lowering the threshold voltage, that is, the operation of pulling out electrons from the floating gate is called writing, and the operation of injecting electrons into the floating gate is called erasing. In order to realize this, at the time of writing, a negative voltage of -9V is applied to the control gate.
Is applied, and 4 V is applied to the drain. by this,
A voltage of 13 V is applied between the control gate and the drain with the drain side being positive. For this,
The electrons in the floating gate are emitted to the drain.
Since this operation is determined by the voltage difference, 1
3V may be applied and 0V may be applied to the control gate. However, in this case, the withstand voltage of the circuit that generates the signal of this voltage must be made large, which makes designing difficult. Further, in order to realize a non-selected memory cell, a voltage of 9 V, for example, must be applied to the control gate, and power consumption increases as a whole. Therefore, a negative voltage is used for the gate. In the case of erasing, 12V is applied to the gate and -4V is applied to the substrate (well).
As a result, a voltage of 16 V is applied between the control gate and the substrate with the control gate side being positive. Therefore, electrons are injected from the substrate to the floating gate. After all, 16V may be applied only to the control gate without using a negative voltage, but it becomes difficult to design the withstand voltage of the peripheral circuit that generates this. Therefore, a negative voltage is used. As described above, since a negative voltage is used in the flash memory, the sectional structure shown in FIG. 3 is essential.

FIG. 5 is a diagram showing a second embodiment of the present invention. It is an example in which the DBG portion in the first embodiment is embodied. In this figure, a bandgap generator is composed of a circuit composed of Q1 and Q2 and R1 and R2, and MP4, MP5 and MN3 which feed back to a common base due to a difference in collector voltage of Q1 and Q2. The voltage of the output N2 of the bandgap generator is equal to the voltage difference of R2 by Q2.
VBE is added. Where Q is on both ends of R1
A difference in VBE between 1 and Q2 appears, which has a positive temperature coefficient. In the equilibrium state where feedback is applied to MP4, MP5 and MN3, twice the current flowing in R1 flows in R2, so the voltage difference at this time is only the ratio of R1 and R2 of the difference voltage of VBE above. It is twice the large value, which is also a positive temperature coefficient. Since VBE of Q2 has a negative temperature coefficient, the temperature coefficient of the output voltage can be made almost zero by the voltage difference of R2 which is a positive temperature coefficient. Explaining other components, MP3 is a switching MOS between the bandgap generator and the power supply terminal VP, and includes MN1, MN2, MP1, MP2 and an inverter I.
1 is M by the switching signal S1 of Vcc level.
A level conversion circuit for generating a signal for turning on / off P3 in N1. Here, VP is a voltage generated by the charge pump inside the chip. This voltage need not be tightly controlled. This is because the output of the bandgap generator is determined by Vss as described above.
Depending on the voltage of VP, the collector voltage of Q1 and Q2 and
Although the operating points of MP4, MP5, and MN3 change, the rough voltage of VP and the transistor constant can be selected so that this influence is reduced. The MN4, MP6 and the inverter I2 are switches that connect the output N2 of the bandgap generator and the output terminal VRF having the capacitance CR, and are driven by S2.

The operation of the second embodiment will be described with reference to FIG. This figure also does not include the beginning of the operation, but is a state when the operation proceeds. At the beginning of this figure, S1 is 0V
And N1 which is the gate of MP3 is VP, so M
P3 is off. Further, S2 is also 0V, and MN4 and MP6 between N2 and VRF are off. This time,
Voltage of VRF By the previous operation not shown in this figure, the charge of CR charged in VBG is being removed by the leak current due to various factors and is decreasing. When this potential drops to near VBL, S1 first switches.
As a result, a voltage is applied to the bandgap generator, and as described above, the voltage VB having a small temperature dependence is applied.
G occurs. When the voltage of VBG becomes stable, S2 is switched next time. As a result, N2 and VRF are connected, and the voltage of VRF that has dropped to VBL becomes the voltage of VBG again. Thereafter, S2 is switched to separate N2 and VRF, and S1 is switched to turn off the bandgap generator. This VRF voltage is used as a reference voltage. The voltage of VRF decreases again due to leak currents of various factors. S1 and S2 are controlled as shown in the figure so that this voltage does not become lower than VBL. As described above, according to the present embodiment, since the bandgap generator is used, a reference voltage having excellent temperature characteristics can be obtained, and since the dynamic operation is adopted, the power consumption is small, and therefore the current supply is limited. It can operate at a voltage higher than the external power supply voltage generated by a certain charge pump. As a result, a stable reference voltage can be generated even if the power supply voltage becomes low. FIG. 7 is a diagram showing a third embodiment of the present invention. This appears in VRF 1.2
This is a method of generating a desired reference voltage from a reference voltage of about V. Here, VRF is first input to the OP amplifier OP1, the output impedance is lowered, and the same voltage as VRF is set to V
Occurs at RF1. Based on this VRF1 voltage,
The voltage of VRF2 is controlled by the OP amplifier OP2 which receives the voltage obtained by dividing the desired reference voltage generated in VRF2. V1 and V2 are power supply terminals of each OP amplifier and may use an external power supply or a chip internal power supply. In this figure, when the voltage of VRF2 is stepped down and used by R1 and R2, that is, the voltage of VRF2 is VR.
Although the case of higher than F is shown, the case of lower than F can be realized by a system using two similar OP amplifiers. According to this embodiment, the reference voltage of a desired voltage can be generated from the output of VRF.

FIG. 8 is a diagram showing the voltage relationship of the present invention.
An example of VP and VRF is shown on the horizontal axis of Vcc. If the bandgap generator is operated using Vcc instead of VP, as shown by the dotted line,
At about Vcc = 2V, the voltage difference from the generated voltage VRF is 0.
It is as small as 8V. Therefore, a voltage having desired characteristics cannot be generated. On the other hand, if VP is used, in the example of this figure, Vc
Since c = 2V and VP is 3V or more, the bandgap generator can operate normally. This VP voltage must be generated by the charge pump,
In the present invention, since the bandgap generator is operated dynamically, the current supplied by the charge pump is small. Depending on the operating conditions, a high voltage created by a one-shot boost circuit instead of the charge pump circuit may be used.
When Vcc = 2V, the power supply voltage is plus or minus 10.
%, The CP is not strictly controlled in the present invention. Therefore, as shown in the figure, it varies about ± 20%. However, in this voltage range, the variation of VRF is small as shown in the figure.

FIG. 9 is a diagram showing a fourth embodiment of the present invention. A feature of this embodiment is that a charge pump that generates a large voltage VH (positive voltage or negative voltage) with an absolute value inside the chip is controlled by using the reference voltage of this embodiment. VH is, for example, a voltage applied to a word line at the time of writing in a flash memory, and since the writing speed greatly differs depending on the voltage condition, accurate control is required. In this embodiment, a charge pump C that generates VH
A clock generation circuit PG for controlling PH is level-shifted from VH by a level shift circuit LS to generate voltages VH1 and RE.
The difference between the reference voltage VRF2 generated at F and the OP amplifier OP
1 detects and controls. For example, the frequency of the output CK of PG is changed according to the potential of the output AN of OP1. VR of the first or second embodiment instead of VRF2
You may use F. Since the reference voltage generated by REF is a stable voltage having excellent temperature characteristics, a large voltage (positive voltage or negative voltage) with an absolute value can be stably generated inside the chip according to this embodiment.

FIG. 10 shows a fifth embodiment of the present invention. The feature of this embodiment is that the current of the output circuit of the chip is kept constant by using the reference voltage of this embodiment. Dout is the chip output terminal, and MP1, MP
2, MN1 and MN2 are its drivers. For example, in a flash memory, a signal obtained by amplifying a read signal of a memory cell appears in ROT and ROB, and this is output buffer D.
Amplify with OBF. In this embodiment, the differential output of DOBF drives the inverter I1 to drive MP2 and the inverter I2 to drive MN2. Where if MP
2 and MN2 are directly connected to the power supplies V0 and Vss, a large current flows when the output terminal switches from a low level to a high level, for example, and the driving speed varies from chip to chip due to process variations. .
In this embodiment, a constant current is generated in MN3 and MN4 by the reference voltage generation circuit REF of the present invention. This MN
The gate lengths of 3 and MN4 are set large in consideration of process variations. Further, the temperature characteristics of REF can be designed including the temperature characteristics of MN3 and MN4. Regarding the constant current of MN3, the upper limit of the current on the high potential side of the output driver can be suppressed to a constant value by the current mirror circuits MP3 and MP1. The constant current of MN4 is the current mirror circuit MP
4 and MP5 and MN5 and MN1 can suppress the upper limit of the current on the low and high potential side of the output driver to a constant value. As a result, according to this embodiment, the output of the chip can be controlled without passing an excessive current.

[0018]

Since a bandgap generator is used, a reference voltage having excellent temperature characteristics can be obtained, and
Since the dynamic operation is used, the power consumption is small, and therefore the voltage can be operated higher than the external power supply voltage generated by the charge pump having a limited current supply. As a result, a stable reference voltage can be generated even if the power supply voltage becomes low.

[0019]

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing an operation example of the first embodiment.

FIG. 3 is a diagram showing an example of a sectional structure of the present invention.

FIG. 4 is a diagram showing an example of voltage application to a flash memory.

FIG. 5 is a diagram showing a second embodiment of the present invention.

FIG. 6 is a diagram illustrating an operation example of the second embodiment.

FIG. 7 is a diagram showing a third embodiment of the present invention.

FIG. 8 is a diagram showing a voltage relationship of the present invention.

FIG. 9 is a diagram showing a fourth embodiment of the present invention.

FIG. 10 is a diagram showing a fifth embodiment of the present invention.

FIG. 11 is a diagram showing a conventional example.

[Explanation of symbols]

DBG ... Dynamic bandgap generator circuit, CP ... Charge pump circuit, VP ... Charge pump output terminal, output voltage, BGR ... Bandgap generator, CR ... Reference voltage storage capacity, VRF ... Reference voltage output terminal, reference voltage, S1, S2 ... DBG activation signal.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical display location H02M 3/07 (72) Inventor Katsutaka Kimura 1-280 Higashi Koigokubo, Kokubunji, Tokyo Hitachi, Ltd. Central Research Center

Claims (4)

[Claims] 1. A booster circuit which receives an operating voltage between a first potential and a second potential and boosts the operating voltage; a boosted voltage boosted by the boosting circuit and the first potential. A bandgap reference voltage generating circuit provided in between, a first switch provided in series with the bandgap reference voltage generating circuit between the first potential and the boosted voltage, and the bandgap reference voltage A second switch having one end connected to an output terminal of the generation circuit; and a capacitor connected between the other end of the second switch and the first potential, the first switch Is turned on, the second switch is turned on, the second switch is turned off, and then the first switch is turned off. 2. A first n-type region in a semiconductor device having a well structure of an nMOS transistor in which a first n-type region is formed on a p-type substrate and a second p-type region is formed therein. Is a collector, the second p-type region is a base, and nMO
2. The bandgap reference voltage generator according to claim 1, wherein a bipolar transistor having the source or drain structure of the S transistor as an emitter is formed and used. 3. A memory cell having a floating gate and a control gate using a negative voltage for write or erase operations, wherein a negative voltage is used to create a first n-type region on a p-type substrate. NMO in which a second p-type region is formed in
In a non-volatile semiconductor device having an S-transistor well structure, a bipolar transistor having the first n-type region as a collector, the second p-type region as a base, and the source or drain structure of an nMOS transistor as an emitter is produced. The bandgap reference voltage generator according to claim 12, wherein the bandgap reference voltage generator is used. 4. A well structure of an nMOS transistor having a memory cell of one transistor and one capacitor, wherein a first n-type region is formed on a p-type substrate and a second p-type region is formed therein. In a volatile semiconductor device or a non-volatile semiconductor device, a bipolar transistor having the first n-type region as a collector, the second p-type region as a base, and the source or drain structure of an nMOS transistor as an emitter is formed. The bandgap reference voltage generator according to claim 1, wherein the bandgap reference voltage generator is used.