JP2735221B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improving the performance of a semiconductor device, and more particularly to a semiconductor device suitable for high stability and high reliability of a highly integrated semiconductor device.

[Conventional technology]

In a semiconductor memory (for example, a DRAM) using a MOS transistor as a transfer transistor of a memory cell, a data line is set so that a word line voltage is higher than a data line voltage in order to reduce loss of a signal voltage due to the transfer transistor. There is a method of driving a word line using a high voltage source boosted to a voltage or higher. Japanese Patent Application Laid-Open No. Sho 62-21323 discloses such a method.

[Problems to be solved by the invention]

Japanese Patent Application Laid-Open No. Sho 62-21323 discloses that the high voltage boosted above the data line voltage is output so as not to make the high voltage boosted above the data line voltage in FIG. 15 excessively high. A circuit is disclosed in which a clamp circuit is provided at the output of a booster circuit, and when the voltage becomes excessively high, a current is leaked to prevent a rise in potential.

However, in such a method, the voltage rise cannot be sufficiently controlled only by the leak current flowing through the clamp circuit.

Accordingly, an object of the present invention is to provide a semiconductor device that generates a stable word line voltage.

[Means for solving the problem]

The above object is to drive a plurality of memory cells, a plurality of word lines respectively connected to gates of MOS transistors in each memory cell of the plurality of memory cells, and a selected word line of the plurality of word lines. A semiconductor device including a word line driving circuit, wherein when operating information is read from a memory cell in which the gate of the MOS transistor is connected to the selected word line among the plurality of memory cells, an operating voltage is reduced. The word line driving circuit (FIG. 59) further includes a voltage generating means (MST) for supplying the supplied voltage higher than the operating voltage to the word line driving circuit. Forming a current path between the selected word line and the output of the voltage generating means which is higher than the operating voltage. A voltage boosting circuit (TMC240, TMC241) for boosting the operating voltage to a voltage higher than the operating voltage;
And a control circuit (QD24) that compares the voltage corresponding to the output of the booster circuit with a predetermined voltage and controls the operation of the booster circuit.
0, QD241, QD242, QD243, QD244, QD245, TM246, TM247, NA24
0).

[Action]

When the output of the booster circuit is higher than the predetermined voltage, the control circuit stops the boosting operation to suppress a further voltage rise, and when the output of the booster circuit is lower than the predetermined voltage, performs a boosting operation to prevent a further voltage drop. Let This suppresses fluctuations in the output voltage of the voltage generation means, so that a highly reliable semiconductor device can be provided.

〔Example〕

FIG. 1 is an embodiment showing the basic concept of the present invention. In FIG. 1, reference numeral 1 denotes a semiconductor chip, 2 denotes an original internal circuit of a semiconductor device, and 3 denotes a control circuit of the present invention. The control circuit generates a control signal or a controlled internal voltage according to a change in manufacturing conditions or use conditions. The operation of the circuit 2 is controlled via the control line 5. 5
Is shown as one signal, but a plurality of signals may be prepared according to the circuit of the circuit 2.

According to the present embodiment, the characteristics of the circuit 2 are maintained in a certain relationship according to the manufacturing conditions and the use conditions, so that a highly stable and highly reliable semiconductor device can be realized.

FIG. 2 shows another embodiment of the present invention, which is different in that the operation characteristics of the circuit 2, for example, the operation speed, the operation current, etc., are detected via the detection line 6, and the control signal is generated accordingly.

According to this embodiment, since the control signal is generated by directly detecting the operation characteristics of 2, the control can be performed with higher precision than in FIG. 1, and a more stable and highly reliable semiconductor device can be realized. it can.

Here, it goes without saying that a plurality of detection lines 6 may be provided as necessary.

FIG. 3 shows another embodiment of the present invention, which differs from the embodiment of FIG. 2 in that a detection circuit 4 having characteristics similar to 2 is provided in order to detect the operation characteristics of 2.

According to the present embodiment, even if there is no appropriate circuit section for detecting the operating characteristics in the circuit 2, the characteristics of the circuit 2 can be indirectly detected via 4 and thereby the circuit 2 can be detected. The characteristics can be controlled so as to maintain a certain relationship.

Here, 4 is also controlled by 5 but this is to change the characteristic of 4 in the same manner as 2 and it is possible to operate it independently of 5 depending on the purpose. .

FIG. 4 shows an embodiment in which the embodiment of FIG. 1 is applied. In this embodiment, the control circuit 3 supplies the power supply voltage of the internal circuit 2 through the power supply line 5I. This embodiment is suitable, for example, for a case where the internal circuit 2 is composed of fine elements. That is, if the potential of 5I is set to a value lower than the withstand voltage of the elements constituting the internal circuit 2, the control circuit 3 can operate the highly integrated semiconductor device composed of fine elements while maintaining stable and high reliability. it can. Furthermore, according to the present embodiment, there is no need to lower the external voltage, so that no burden is imposed on the user. For example, in DRAMs and the like, it is necessary to miniaturize elements to increase the integration density to 256K bits, 1M bits, and 4M bits.In this case, reducing the external voltage to cope with the decrease in withstand voltage is a conventional technique. This embodiment is effective because it is not desirable in terms of compatibility with products. Although a plurality of control lines are shown in FIG. 4, the characteristics of the internal circuit may be stabilized by controlling only the voltage of the internal circuit 2 with the control circuit in some cases. Internal voltage is external power supply V
_After compensating the variation of the internal voltage with respect to the _CC, it is also possible to change the compensation so as to compensate for the characteristic change of the internal circuit due to the variation of the external condition such as the temperature and the manufacturing condition. In the embodiment shown in FIG. 4, it goes without saying that the control circuit to which the external voltage V _CC is directly applied is constituted by using an element having a withstand voltage of V _CC or higher. However, in some cases, in order to improve the degree of integration or to match the characteristics of the control circuit and the internal circuit, it may be necessary to configure a part of the control circuit with fine elements having a low withstand voltage. . In that case,
As FIG. 5, inside provided with a voltage conversion circuit 3A of the control circuit 3 supplies a lower V _CC voltage through its output line 5I, the lower portion of the breakdown voltage in the internal circuit 2 and the control circuit 3
3B can be controlled. As described above, according to the embodiment shown in FIG. 5, since it can be constituted by miniaturized elements including the control circuit, the degree of integration is further improved. Control circuit 3B and internal circuit 2
Can be composed of elements having the same characteristics,
There is an advantage that the characteristic fluctuation can be precisely controlled based on the characteristic fluctuation of the circuit in the control circuit 3B. The fourth, may be operated with high element of a part of the pressure in the internal circuit in the external voltage V _CC as required in the embodiment of FIG. 5. By the way
4 and 5, it is a matter of course that the device can be configured in the same manner as in FIGS. 4 and 5 even when a fine element having a low withstand voltage is used in FIGS. Also, in the embodiment of FIGS. 1 to 5, an example is shown in which one control circuit is provided in each chip. However, if necessary, the internal circuit 2 is divided into several parts to control each other. A circuit may be provided. Further, in this case, it is needless to say that the components shown in FIGS. 1 to 5 may be combined as needed. When the internal circuit 2 is divided into several parts and the characteristics are controlled as described above, it is possible to control the characteristics to the optimum characteristics by the functions of the individual circuits. FIG. 6 shows a case where the operating speed of the circuit is controlled to a different constant value. In Figure 6, the dashed line C ₁₁ is intended to show the operation speed of the conventional circuit without the control circuit, manufacturing conditions, the operating speed in accordance with a change in use conditions have changed significantly. The case of providing a plurality of control circuits contrast, circuits requiring high-speed operation was held constant at a high speed as B _11, circuits requiring low speed operation constant at a low speed as A ₁₁ It is possible to keep. For example, in an output circuit or the like, if the output is charged and discharged at a high speed, noise is generated in the power supply, which adversely affects the operation of the internal circuit or a semiconductor device arranged nearby. In such a case, by controlling only the output circuit at a low speed, the operating speed can be kept constant without reducing the overall speed. Here, an example has been described in which the circuit operation is controlled so as to be constant by fluctuations in manufacturing conditions and use conditions. However, a desired dependency may be given to a desired factor as needed. For example, it is possible to perform control so that the operating speed of the circuit increases as the temperature rises.

In this case, the speed of the semiconductor device or the entire system including the semiconductor device is controlled by controlling so that the delay of the resistance of the wiring in the semiconductor device or the wiring between the semiconductor devices is canceled by the temperature. Can be kept. According to the embodiment shown in FIGS. 1 to 6, since the characteristics of the circuit do not fluctuate due to the manufacturing conditions, the yield of non-defective products in mass production is improved. Further, since the characteristics do not vary depending on the use conditions, the reliability of a system such as a computer constituted by using the semiconductor device of this embodiment is also improved.
Further, in some cases, in two circuits in circuit 3,
In some cases, it is necessary to synchronize the operations of the two. In such a case, the use of the present embodiment makes it possible to minimize the timing margin because there is no change in circuit characteristics. Therefore, there is an advantage that the speed of the semiconductor device can be increased accordingly. For example, in a DRAM, it is necessary to synchronize the operation of the memory cell array and the peripheral circuit. In such a case, the application of the present invention can minimize the timing margin and thus increase the speed. The same applies to the case where the operation must be synchronized between two or more semiconductor devices. The use of a semiconductor device to which the present invention is applied makes it possible for a system such as a computer including a plurality of semiconductor devices to be used. The operating speed can also be increased. In FIGS. 4 and 5, the positive power supply is connected to V _CC
Assuming a so-called TTL interface, the same applies to ECL. In the following, description will be made focusing on the TTL interface, but the present invention is not limited to this, and can be applied to the ECL interface.

Hereinafter, specific circuit examples will be described. First, a method for controlling characteristics of a driving circuit which is a basic circuit of an integrated circuit will be described.

FIG. 7 shows one specific embodiment for controlling the characteristics of the driving circuit in the circuit 2. In FIG. The figure shows an example in which the characteristics are controlled by changing the power supply voltage of the circuit.
Here, a P-channel is used as an element circuit 2 ′ constituting 2.
A CMOS inverter composed of a MOS transistor T _P1 and an N-channel MOS transistor T _N1 is used.
Other logic circuits such as an OR circuit, a circuit formed by bipolar transistors, a circuit formed by a combination of a bipolar transistor and a MOS transistor, or a circuit obtained by arbitrarily combining a plurality of these circuits may be used.

According to the present embodiment, by changing the voltage V _CONT of 5, 2 ', that is, the overall characteristics of 2, can be controlled.
A highly stable and highly reliable semiconductor device can be realized. The value of V _CONT depends on the type of circuit 2 'to be controlled and its purpose. For example, it is shown in FIG. 7 (A). In order to stabilize the operation speed of the CMOS inverter and increase the reliability, V _CONT may be changed as shown in FIG. That is, the delay time td of the CMOS inverter is a main variable factor of the gate length Lg of the MOS transistor, the threshold voltage V _T , the gate oxide film thickness t _OX , the channel conductance β ₀ , the temperature T (absolute temperature), and the load capacitance. For C _L In a relationship. In an actual circuit, the relationship may slightly deviate from this relational expression due to various circumstances, but the tendency shown by the expression (1) is almost maintained in the entire CMOS circuit. Therefore, to keep td constant according to this equation, V
_What is necessary is _just to change _CONT . In other words, as the qualitative tendency, as shown in FIG. 7B, if the fluctuation factors (where β ₀ is the reciprocal thereof) are large or high and the value of V _CONT is high, td can be reduced. It can be kept almost constant. As a result, the operating speed can be kept constant even if the manufacturing conditions or the use conditions change. Further, in this embodiment, since the semiconductor device responds to a temperature change, the semiconductor device itself responds to a temperature change or an ambient temperature change due to a difference in the heat generation amount of the chip depending on the operation state of the semiconductor device itself during standby and normal operation. Can also keep the performance constant.

In equation (1), Lg, v _T , t _OX , β ₀ are commonly defined for both P / N channel MOS transistors.
In practice, they often have different values. However, in both channels, only the polarity of the voltage and the current are different, and the relationship of the expression (1) holds as it is. Therefore, here, they are handled without distinction unless particularly necessary.

As described above, in some cases, the circuit speed may not be constant, and a desired parameter may have a desired dependency. For example, if it is desired to increase the speed of the circuit as the temperature rises as described above,
From equation (1), (V _CONT −V _T ) ∝T− ^1.5 is not used and (V _CONT −V _T ) ∝T− ⁿ may be set as n> 1.5.

Next, regarding the element withstand voltage, the breakdown withstand voltage is expressed as Lg, t _OX
Becomes smaller, the V _CONT may be similarly controlled as shown in FIG. It has also occurred near the drain of a MOS transistor, which has recently attracted attention. A high-energy carrier is injected into the gate oxide film, which increases the threshold voltage and lowers the channel conductance. This causes a deterioration in characteristics, such as a withstand voltage that defines the upper limit of the operating voltage (hereinafter referred to as a hot carrier withstand voltage). ) Also L
Since g and t _OX are small and the temperature T is low, the V _CONT may be controlled as shown in FIG. As a result, even if the hot carrier breakdown voltage decreases due to manufacturing variations, V _CONT also decreases, so that problems such as characteristic deterioration do not occur. Further, even if the threshold voltage becomes high due to the hot carrier phenomenon or the like due to the long-term operation, or the channel conductance becomes small, V _CONT is controlled as shown in FIG. Can be kept constant.

As mentioned earlier, the embodiment of FIG.
Various circuits can be used without being limited to the inverter.
For example, a BiCMOS inverter as shown in FIG. 8 may be used. In this case, since the output can be driven by the bipolar transistor, higher-speed operation can be realized. In FIG. 8, the collector of the bipolar transistor Q _N3 is connected to the external power supply V.
Connected to _CC . This allows most of the output current to be
Since the power is supplied from V _CC, the driving capability of the control circuit 3 can be reduced, and the design becomes easy. Note that when the breakdown voltage of the bipolar transistor is low, the collector may be a V _CONT of Q _N3 to increase the driving capability of the control circuit 3. A circuit as shown in FIGS. 9 and 10 can be used as 2 'in FIG.

FIG. 9 shows an embodiment in which an output buffer circuit comprising T _N3 and T _N4 is added to the embodiment of FIG. The operating speed and output voltage of this embodiment are controlled by V _CONT as in FIG.
Since the driving current of the load capacitance C _L of the output is supplied from the V _CC, the Figure 8 embodiment as well as the drive capability of the control circuit 3 can be reduced, thereby facilitating the design.

FIG. 10 shows an embodiment in which T _N3 is replaced by a bipolar transistor Q _N3 . Since the driving capability of _QN3 is large, it is possible to drive the load at a higher speed and further reduce the driving capability of V _CONT .

8 to 10, the embodiment shown in FIG.
The circuit characteristics can be controlled by V _CONT .

FIG. 11 shows another specific embodiment for controlling the characteristics of the drive circuit. FIG. 7 shows only a part of the element circuit 2 'in FIG. 7, and a P-channel MOS transistor T _P2 , between a CMOS inverter of T _P1 T _N1 and an external current voltage V _CC and ground.
By inserting an N-channel MOS transistor T _N2 and controlling its gate voltage, the operating current of the inverter is controlled and finally the operating speed is controlled. That is, the speed at which the current is increased increases, and the speed at which the current decreases decreases. The delay time td has the same tendency as shown in Expression (1) for each variation factor. It was but connexion, as shown in FIG. _{(B), Lg, V T} , t OX, 1 / β 0, T, as C _L increases, so that each current increases, i.e.,
V _CONT for gate control of the P-channel MOST goes from a high value to a low value, V _CONT ′ for controlling the gate of the N-channel MOST.
If is changed from a low value to a high value, td can be kept almost constant.

According to the present embodiment, the operating current of the circuit is directly supplied from the power supply voltage, and V _CONT and V _CONT ′ need only drive the gate of the MOS transistor. Extremely easy. In this embodiment, the control is performed by using both the P and N channel MOS transistors. However, it is also possible to provide only one of them if necessary. In the embodiment of FIG. 11,
By the gate width of the MOS transistor T _P1, T _N1 such as large compared to T _P2, T _N2, if the on-resistance of the T _P1, T _N1 is larger than T _P2, T _N2, T _P1, T _N1 current flowing through is determined by on-resistance of T _P2, T _N2, it becomes easier to control.

Although FIG. 11 shows an example of an inverter, the present embodiment is not limited to this and can be applied to various logic circuits such as a NAND circuit and a NOR circuit. That is, the DRIV having the function of the drive circuit in FIG. 11 may be replaced with a logic circuit.

FIGS. 12A and 12B show an example in which the control method shown in FIG. 11 is applied to a BiCMOS drive circuit having a higher drive capability than CMOS. As is well known, in BiCMOS, a MOS transistor controls the base current of a bipolar transistor, and the bipolar transistor amplifies the current to drive a load capacitance. Accordingly, the speed of the circuit can be controlled by controlling the base current as shown in FIG. Twelfth
In the figure (A), when the input IN goes low, pMOST _P2 , nM
OST _N4 is turned on, and nMOST _N3 , T _N2 and T _N1 are turned on. as a result,
Bipolar transistor Q _N3 turns on and Q _N4 turns off.
At this time, the base current through Q _N3 can be controlled by T _P1 where V _CONT is applied to the gate. _Therefore , the speed at which the output is charged can be controlled by V _CONT . On the other hand, input IN becomes high, the bipolar transistor Q _N3 is turned off, Q _N4 discharge output turned off it is started. Then Q
The base current of _N4 is supplied from output OUT, which is
_The output discharge rate can be controlled by V _CONT '
Can be controlled by Thus, in this embodiment, the BiCMOS
The operation speed of the circuit can be controlled. In addition, BiCMOS
To control the speed of the circuit, the DRIV portion in FIG. 11 may be simply replaced with a BiCMOS circuit as shown in FIG. 12 (B). In this case, since the current can be generated by the MOS transistors T _P2 and T _{N2 in} FIG. 11 (A), the current can be controlled with higher precision than when only the base current is controlled as shown in FIG. 12 (A). Further, compared with the circuit of FIG. 11, there is an advantage that the MOS transistor in the DRIV can be reduced by the amount corresponding to the driving capability of the bipolar transistor, so that the input capacitance viewed from the input IN is small. That is, since the load at the preceding stage is light, the speed can be increased.

The method of controlling the current by inserting a MOS transistor between the power supply and the drive circuit as shown in FIG. 11 can be applied to other applications. FIG. 13 shows an example applied to a level conversion circuit for obtaining an output amplitude higher than the input amplitude. Fig. 13 using Fig. 14
The circuit operation in the figure will be described. When the input IN goes to the high potential V _A while E is at the high potential, the potential of F becomes V _A −V _T11n through nMOST _N3.
Potential. Next, when E becomes low potential, pMOST _P3 turns on and the potential of F becomes _VH . This results in pMOST _P1 off, n
MOST _N1 turns on and the output OUT goes to 0V. Note When F is increased to a high potential V _H, A, the potential of C is a V _A, T _N3 the potential of F will not be lowered by flowing out current from the F to C because it is off. On the other hand, when IN goes to a low potential while E is at a high potential, T _N3 turns on, and F goes to the same low potential as IN. Consequently T _P1 is turned on, T _N1 is turned off, the output OUT is charged to a high potential V _H. In this circuit, as shown by the broken line in FIG.
Since the high potential of F stays at V _A −V _T for a while if t _CE is long from the time when IN becomes the high potential V _A to the time when E becomes the low potential, a through current flows through T _P1 and T _N1. , OUT may remain at an insufficiently low potential. Therefore t _CE
It is desirable to shorten the time. For that purpose, it is sufficient to switch E to a low potential at the same time as IN becomes a high potential. This solves the above problem.

As described above, according to the embodiment of FIG. 13, the amplitude of the input IN
V _A can be converted to high amplitude V _H. At this time, MOS
Since the current can be controlled by the transistors T _P2 and T _N2 , the transistor can be operated at a desired constant speed. The embodiment of FIG. 13 is effective as a circuit for obtaining an output voltage higher than the input voltage such as a word driver of a dynamic memory. FIG. 15 shows another embodiment for controlling the speed of the drive circuit. This embodiment is an example in which a non-inverter is configured so as to obtain an output directly from the current control MOS transistor in FIG. In FIG. 15, when the input voltage becomes high, pMOST _P1 and T _P3 are turned off, and nMOST _N1 and T _N3 are turned on. As a result, the gate of pMOST _P2 becomes V _CONT ,
The gate of nMOST _N2 goes to 0V. This turns on T _P2 T _N2
Is turned off, and a current controlled to a desired value by V _CONT flows through the output to charge the load. Conversely, when input IN goes low
_TP2 is turned off, _TN2 is turned on and the discharging operation starts, and OUT becomes 0V. At this time, since the gate voltage of T _N2 is V _CONT ′,
V _CONT also controls the rate of discharge. In this embodiment,
It is suitable for high-speed operation because two MOS transistors are not connected in series between the power supply and the output. In addition, the control is easier than in the case of FIG. 11 in which the influence of the characteristic fluctuation of the two transistors connected in series must be considered.

The method of controlling the operation speed of the drive circuit has been described above. In the circuits of FIGS. 7 to 12 and 15, an external voltage V _CC is applied to a part of the circuit. Therefore, in some cases, it may be difficult to compensate for fluctuations in V _CC . In that case, the fifth
The voltage conversion circuit 3A to the control circuit 3 as shown in provided Figure V the internal circuit by keeping the output voltage V _I constant
It can be operated stably against the fluctuation of _CC . In this case, by setting a low internal voltage V _I, the lower miniaturized device withstand voltage can be stably operated. FIG. 16 shows an embodiment in which the voltage conversion circuit is provided in the chip as described above. 5I in FIG. 16, a power supply line for supplying a voltage V _I to the circuit 3B, and the internal circuit 2 in the control circuit from the voltage conversion circuit 3A. The ICL is a current control circuit for controlling the current of each circuit DRIV in the internal circuit, like the MOS transistors T _P2 and T _N2 in FIG. According to this configuration, the device is miniaturized by a constant voltage V _I not according to the external voltage V _CC can be operated stably, yet can be moved at a desired speed corresponding to the function of the circuit of each.

FIG. 17 is an embodiment showing another means for controlling the operation speed of the CMOS inverter. Here, by controlling the voltage of the substrate SBP1, SBN1 of T _P1 and T _N1, to control the threshold voltage of T _P1, T _N1, and controls the operating characteristics of the inverter as a result. The present embodiment is suitable for compensating for a characteristic change due to a threshold voltage fluctuation.

Fig. 17 shows a CMOS inverter.
It can be applied to other circuits using MOS transistors such as OS inverters. In addition, it is of course possible to combine such a method of controlling the substrate voltage with the other control methods described above.

Although FIGS. 7 to 17 have mainly described a method of controlling the characteristics of a drive circuit such as an inverter and a non-inverter NAND circuit, in an integrated circuit, a differential amplifier that outputs an output according to a voltage difference is additionally provided. Is also frequently used. Hereinafter, an embodiment of the differential amplifier will be described.

FIG. 18 shows another embodiment of the present invention, in which the control method of FIG. 11 is applied to control of the operating speed of a differential amplifier constituted by MOS transistors. In the figure, IN1 and IN2 are differential inputs, and OUT1 and OUT2 are differential outputs. In this circuit as well, the operating speed is affected by changes in control conditions and operating conditions, as shown in FIG.
It changes in the same tendency as in FIG. Therefore, V _CONT , V
_{By controlling CONT} 'in the same manner as in FIG. 11 (B), the operating current changes, and as a result, the operating speed can be controlled according to manufacturing conditions and use conditions. The output voltage of this differential amplifier depends on the operating current and the load MOS transistor T _PL ,
It is determined by the product of the ON resistance of T _PL ′. Therefore, if the operating current is determined and V _CONT , V _CONT ′ is controlled so that the ratio of the ON resistance of T _{NC to} the ON resistance of T _PL , T _PL ′ becomes constant, the operating current and T _PL , T _The operating speed can be controlled while keeping the product of the ON resistance of _PL ', that is, the output voltage constant.

FIG. 19 shows an embodiment in which T _NA and T _NA ′ in FIG. 18 are replaced by NPN bipolar transistors Q _NA and Q _NA ′, and the same effect as that of FIG. 18 is obtained, and the amplification factor can be increased. Features such as

FIG. 20 is a diagram in which the current control transistor T _NC of FIG. 19 is replaced by an NPN bipolar transistor Q _NC and a resistor _RC , and the operation speed can be controlled in the same manner as in FIG. 18 and FIG. Further, since the operating current is made more constant, there is a feature that the amplification factor can be increased.

In the case where application of V _CC in FIG. 18-20 is problematic in terms of characteristic fluctuation due to fluctuation of withstand voltage or V _CC , a voltage conversion circuit provided inside the chip as shown in FIG.
What is necessary is just to give a desired voltage by 3A.

The preferred embodiment for controlling the characteristics of various element circuits constituting the circuit 2 has been described above. Next, a specific embodiment of the control circuit 3 will be described.

FIG. 21 shows an embodiment thereof. T _PR is P-channel MOS transistor in FIG, CC is a constant current source for supplying a constant current i. According to this embodiment, the gate length of the T _PR, threshold voltage, manufacturing conditions such as a gate oxide film thickness, or be varied using conditions such as temperature, the output 5 supplies a constant current to the T _PR The required gate voltage is always output. Accordingly, V in FIGS. 11 to 13, FIG. 15, and FIGS.
It is suitable as a _CONT generation circuit. When applied to these circuits, T _PR and T _P2 in FIGS. 11 to 13 and FIG.
T _PL and T _PL ′ in FIGS. 18 to 20 are connections of a well-known current mirror circuit. Therefore, T _P2 or T
By appropriately selecting the transistor dimensions of _PL and T _PL ′ with respect to those of T _PR , the operating current of each circuit can be controlled to an arbitrary constant value.

FIG. 22 shows an embodiment in which FIG. 21 is constituted by N-channel MOS transistors, which is optimal as a circuit for generating V _CONT ′ in FIGS. 11 to 13, 15 and 18 to 19. Yes, No. 21
The same effect as in the figure can be obtained.

FIG. 23 shows an embodiment in which FIG. 21 and FIG. 22 are combined.
According to this embodiment, FIG. 11 to FIG. 13, FIG. 15, FIG.
Since V _CONT and V _CONT ′ for FIG. 19 can be generated at the same time, and these voltages are generated based on the same constant current source,
An extremely stable voltage with high mutual matching can be obtained.

Figure 24 is P-channel MOS transistor T _PR and N-channel
This is an embodiment in which V _CONT is generated by connecting MOS transistors _TNR in series. According to this embodiment, both P and N channel MOS
The effect of fluctuations in transistor manufacturing and operating conditions is V
Reflected in the value of _CONT . Therefore, FIGS. 7 to 10
It is suitable as a V _CONT generation circuit.

FIG. 25 shows an embodiment in which an amplification stage comprising an amplifier 7 and a feedback circuit 8 having a feedback ratio β is added to the output of FIG. In the present embodiment, if the amplification factor is selected sufficiently large, the output V _CONT becomes By setting β appropriately, an arbitrary value can be obtained. Therefore, in addition to reflecting the effects of fluctuations in manufacturing conditions and use conditions with V _O , β can also be made to have part or all of its role by giving β dependencies on manufacturing conditions and use conditions. it can.

FIG. 26 shows one specific embodiment of the constant current value CC. Constant current source CC ₁ as shown in the figure is constituted by resistors R ₁ ~R _4, NPN bipolar transient scan Q _N1, Q _N2. Voltage of the base B _N1 of Q _N1 in this embodiment, the current amplification factor of the bipolar transistor is sufficiently large and the emitter - when the base forward voltage and V _BE, of _{V BE (R 2 + R 3} ) / R 3 The voltage becomes constant.

Therefore, Constant current flows. V _BE is less susceptible to fluctuations in manufacturing conditions and can output a stable current.

In this embodiment, since i flows from the outside toward the ground, it is suitable as a constant current source for a circuit as shown in FIG.

FIG. 27 shows an embodiment in which a constant current source is constituted by using a PNP bipolar transistor. Voltage and current polarities are 26
The operation is exactly the same except for the difference from the figure. In this embodiment, since i flows out of the power supply voltage V _CC ,
It is suitable as a constant current source for the circuits shown in FIGS.

FIG. 28 shows an embodiment in which a constant current source of a type in which a current flows from a power supply voltage as shown in FIG. 27 is realized by an NPN bipolar transistor. In this embodiment, there is a problem that the operating currents of R ₁ , R ₂ , R ₃ , and Q _N2 are added to the constant current, but the effect can be ignored by sufficiently increasing the current amplification factor of Q _N1 .

According to the present embodiment, a constant current source of a type in which current flows from V _CC can be easily formed using a high-performance NPN bipolar transistor. Note that the present embodiment can be used as any type in which current flows in and out.

FIG. 29 is a diagram in which the above constant current source is applied to the circuit of FIG. 23 taking advantage of this feature. According to this embodiment, V _CONT ,
V _CONT 'can be output simultaneously.

FIG. 30, for example, a current source CC that aerodrome current flows into the ground as a constant current source CC ₁ of FIG. 26, a current mirror circuit composed of P-channel MOS transistor T _PM and T _PM ', from V _CC This is an embodiment in which a constant current source formed so that a current flows out is realized. By making the dimensions of _TPM and _TPM 'the same, the current flowing in both can be made equal, and a current having the same value as the output current i of _CC can be output from the power supply voltage Vcc to the outside. This similar to the FIG. 22 by inputting the N-channel MOS transistor T _NR, it is possible to obtain the V _CONT '. In this embodiment, the output current can be arbitrarily determined with respect to the current value of CC by appropriately selecting the dimensional ratio between _TPM and _TPM '.

FIG. 31, the voltage by connexion occurs T _PM and CC in Figure 30 is obtained by in service as the voltage V _CONT. According to the present embodiment, V _CONT and V _CONT ′ can be simultaneously generated, and have the feature that the characteristics of both can be controlled with good consistency as in FIG.

FIG. 32 shows an embodiment for realizing a highly stable constant current source using MOS transistors.

In the figure, T _{N61 to} T _N63 are N-channel MOS transistors, T _N61 has a negative voltage, and T _N62 has a positive threshold voltage. T _N63
The threshold voltage may be either positive or negative. R _{61 to} R ₆₃ are resistors, and 7 is a differential amplifier.

Here, if the values of R ₆₁ and R ₆₂ and the dimensions of T _N61 and T _N62 are set to be equal to each other, the operation is performed so that the currents flowing through T _N61 and T _N62 become equal to each other. _Therefore, the gate voltage V _I6 of T _N62 becomes a voltage equal to the difference between the threshold voltages of T _N61 and T _N62 . The value of the difference between the threshold voltages is kept substantially constant irrespective of the manufacturing conditions and the use conditions.

In the above circuit, since the drain and source currents of _TN63 are equal, the output current i is Can be expressed as Was but connexion, current output is obtained having the same characteristics as V _I6, its value can be controlled by connexion optionally R _63.

This embodiment enables highly stable characteristic control by being used as a constant current source in each embodiment such as the current source CC shown in FIG.

According to the present embodiment, since a circuit can be formed without using a bipolar transistor, the present embodiment is suitable for an integrated circuit including MOS transistors.

FIG. 33 shows a further preferred embodiment as a constant current shown in FIGS. 21 to 25 and FIGS. 30 to 31. In this embodiment, a well-known bandgap generator circuit is applied as a constant current source, and it is possible to obtain a highly stable current with respect to fluctuations in temperature, power supply voltage, and the like.

In the figure, Q _{51 to} Q ₅₆ are bipolar transistors, R
₅₁ to R ₅₅ is a resistor, it is possible to make a constant current i having a desired temperature characteristic. Note that i ₅₁ is the current flowing through the resistor R ₅₁ , i
₅₂ the collector current of the bipolar transistor Q _52, i ₅₃ is the collector current of the bipolar transistor Q _53. Hereinafter, before describing the output current i, the value of the internal voltage V _I1 and the temperature dependency of the present circuit will be described first. In the following description, for simplicity, it is assumed that the base current is negligible compared to the collector current of the bipolar transistor, and that the collector current and the emitter current are substantially equal. Voltage V _I1 is expressed by the following equation.

V _I1 = V _BE (Q ₅₁ ) + I ₅₂ · R ₅₂ + V _BE (Q ₅₂ ) −V _BE (Q ₅₆ )
(4) Here, V _BE (Q ₅₁ ), V _BE (Q ₅₂ ), and V _BE (Q ₅₆ ) are forward voltages between the base and the emitter of the bipolar transistors Q ₅₁ , Q ₅₂ , and Q ₅₆ , respectively. (4) current I ₅₂ in formula is represented by the following equation.

I ₅₂ = {V _BE (Q ₅₅ ) −V _BE (Q ₅₄ )} / R ₅₄ (5) Here, the emitter area of the bipolar transistors Q ₅₅ and Q ₅₄ is appropriately selected to obtain the bipolar transistor.
By setting the current density of Q ₅₅ to n times of the bipolar transistors Q _54, Holds. In the equation (6), k is Boltzmann's constant, T is absolute temperature, and q is electron charge. From equations (4) to (6) Holds. Accordingly, the bipolar transistors Q ₅₅ and Q
_If the emitter current densities of ₅₆ are designed to be equal, the third and fourth terms on the right side of Equation 7 cancel. _Holds , and the temperature dependence of electricity _VI1 is Becomes As is well known, the base-emitter voltage of a bipolar transistor has a negative temperature dependence.
Therefore, by changing the ratio of the resistors R ₅₂ and R ₅₄ or the ratio n of the emitter current densities of the bipolar transistors R ₅₅ and R ₅₄ from equation (9), ΔV _I1 / ΔT can be set arbitrarily. . The value of V _I1 obtained when the temperature coefficient to zero, substantially equal to the bandgap voltage of silicon semiconductor
Since the value is around 1.2V, it is generally called a bandgap generator.

In the circuit described above, since the collector current and the emitter current of Q ₅₆ are substantially equal, the output current i Can be expressed as Was but connexion, current output is obtained having the same characteristics as V _I1, its value can be controlled by connexion optionally R _55.

If this embodiment is used as a constant current source in each of the embodiments described above, extremely stable control can be performed. In particular, as for the temperature, the temperature coefficient of the constant power supply is set to 0 or any positive or negative value according to the purpose, whereby the operating characteristics of the circuit can be arbitrarily controlled.

Further, the internal voltage V _I1 of the present embodiment can be used as a highly stable constant voltage source. At this time, if the constant current output i is unnecessary, its output terminal may be connected to V _CC .

V _I1 can be used, for example, as V _CONT ′ in FIG. 20, in which case the temperature characteristics of the differential amplifier can be controlled.

The method of controlling the circuit characteristics according to the present invention has been described with reference to some specific embodiments. These embodiments can be easily realized, but when a fine element is used to increase the degree of integration, the withstand voltage of the element is low, and it is difficult to directly request the external voltage V _CC to the element. It is possible. Also, if the external voltage fluctuates, it may be difficult to obtain desired characteristics. In such a case, FIG. 4, FIG. 5, as in the embodiment of FIG. 16, to make a stable voltage V _I internal chip may be used it instead on V _CC. May be applied to V _CC is in place there is no problem by applying a V _CC by the case this time. It can be kept higher stability V _I Since the burden of the voltage source for generating a voltage V _I is reduced if not. Figure 34 shows the internal voltage V _I
5 shows an embodiment for controlling the operation speed to a desired value when using. Here, the CM shown in FIG.
An example in which the OS inverter is controlled by the circuits shown in FIGS. 21 and 22 will be described. However, the present invention is not limited to this and can be applied to the various embodiments described above. In the FIG. 34 pMOST _P2 and T _PR, and nMOST _N2
T _NR forms a current mirror. The was is connexion the embodiment just like T _PR charging current of the driving circuit DRIV be appropriately set the size of the T _P2 for a can be set to any value.
Also, by appropriately setting the size of T _N2 with respect to T _NR , the discharge current can be set to any value. Here, lower than the source voltage and the power supply voltage V _I and the breakdown voltage of the current source CC ₂ of pMOST _PR and T _P2, it is possible to use a low fine elements of the device breakdown voltage Keeping the value. Further, this embodiment, the output since Fuhaba also becomes V _I, voltage input to the next stage can also be controlled stably, next work can be kept stable. Note that V
_CONT , V _CONT ′ The generating circuits 31, 32 can be shared by a plurality of circuits. Even in this case, if the size of _TP2 , _TN2 is set for each circuit, each circuit is controlled at a desired speed. be able to.

Next, as shown in FIG. 4, FIG. 5, FIG.
An embodiment of a voltage conversion circuit suitable for generating a voltage lower than V _CC will be described.

FIG. 35 is an embodiment showing the configuration of the voltage conversion circuit. Here, A is a voltage conversion circuit, F is a constant voltage generation circuit, and G is an amplifier. The constant voltage generation circuit F generates a constant voltage V _I1 from the external power supply voltage V _CC . The amplifier G amplifies the voltage V _I1 to increase the internal circuit 2 or a part 3 of the control circuit.
And it outputs a voltage value V _I required A control line 5I. Where voltage V
_I can have various characteristics by the constant voltage circuit F and the amplifier G. For example, if the temperature dependency and the external power supply voltage dependency are compensated, the output amplitude of the circuit as shown in FIG. 34 can be made constant regardless of V _CC and temperature, so that a more stable operation can be realized. According to this embodiment, the output voltage V _I1 of the constant voltage circuit can be increased to a desired voltage value by the amplifier G. Therefore, it sets the value of the voltage V _I without being limited to a value of the output voltage V _I1 of the constant voltage circuit.

In the embodiment shown in FIG. 36, the amplifier G shown in FIG. 35 is constituted by a differential amplifier GD and a feedback circuit H. Here feedback circuit H is designed so that a voltage is output is equal to the constant voltage V _I1 to the output I ₂ when the voltage V _I take a desired value. Due to the feedback of the variation of the output voltage V _I according to this embodiment through the feedback circuit H, the output voltage V _I even if the current supplied from the control line 5I is rapidly changing with time
Can be kept constant with high accuracy.

Figure 37 is Figure 35, the collector of the V _CC of the bipolar transistor Q ₅₆ in the current source shown in FIG. 33 in that shows a specific configuration example of the constant voltage generating circuit F in the embodiment of Figure 36 This is the circuit connected to. In the circuit of FIG. 37, the output voltage V _I1 and its temperature dependence are given by equations (8) and (9). As described above, the temperature dependency can be set by changing the resistance ratio or the current density ratio of the bipolar transistor. This embodiment is shown in FIGS.
When used in the constant voltage generating circuit F of the embodiment shown in the figure, the amplifier G or the differential amplifier GD and the feedback circuit H
In accordance with the temperature characteristics can be Yotsute to design the value of ∂V _I1 / ∂T, a zero or a desired value of temperature dependency of the output voltage V _I of the voltage conversion circuit A for. In addition,
In the embodiment shown in FIG. 37, the external voltage V _CC is almost twice the base-emitter forward voltage of the bipolar transistor,
When the voltage exceeds about 1.8 V, the voltage V _I2 becomes almost constant regardless of V _CC . Therefore, if this embodiment is used in FIGS. 35 and 36,
Temperature dependence, can be easily obtained an output voltage V _I with no external voltage dependency.

By the way, like the embodiment described so far,
When the constant voltage circuit F and other circuits are formed simultaneously on the same semiconductor substrate, the transistors used for both are MOS transistors.
In some cases, unifying the transistor or one type of bipolar transistor simplifies the process steps and can reduce the manufacturing cost in some cases. Therefore, as the constant voltage circuit F, a circuit using a MOS transistor instead of a circuit using a bipolar transistor as in the embodiment of FIG. 37 may be desirable. In that case, for example,
In FIG. 32, V _I6 of a circuit in which the drain of the MOS transistor T _N63 is V _CC may be used, or OGUEY, Journal of Solid-State Circuit, SC-15, Jun. '
80 or BLAUSHILD, Journal of Solid-State Circuit, SC-13, D
ec. '78 may be used.

FIG. 38 shows a specific embodiment of the differential amplifier circuit GD in FIG.

In FIG. 38, the output voltage of the constant voltage circuit F to the terminal I ₁
V _I1 is the output voltage V _I2 of the feedback circuit to the terminal I ₂ is applied.
In this embodiment, since the terminal I _1, I ₂ is the base electrode of the bipolar transistor can be suppressed small variation of the gain is high voltage V _I. Note that the P-channel MOS transistor in FIG. 6 can be replaced by a resistor as shown in FIG. Since this resistor can be formed by the base diffusion layer of the bipolar transistor, it can be formed in the impurity layer for the collector of the bipolar transistor. Therefore, the layout area of the circuit can be reduced.

Although various circuits can be considered as the current sources of the differential amplifiers in FIGS. 38 and 39, they can be realized by one MOS transistor as shown in FIGS. 40 and 41. is there. Here the gate of the MOS transistor T _I61, T _I71 connected to I _1. Since V _I1 has a constant value with respect to V _CC as described above, this configuration can keep the current of the amplifier constant with respect to V _CC . Further, when it is necessary to stably control the characteristics of the amplifier, various controls can be performed by using circuits as shown in FIGS.

FIG. 42 shows a specific embodiment of the feedback circuit H in FIG.

In the first 42 view, the voltage V _I control lines 5I, the output terminal I _2, Is output to the differential amplifier shown in FIG. Therefore, the output voltage of the constant voltage circuit F is V _I1 , and the desired voltage to be output to the control line 5I is V _I0. If resistors R ₈₁ and R ₈₂ are designed to satisfy the condition, V _I = V _I0 and V _I1
= V _I2 , and the voltage of the control line 5I stabilizes at the desired voltage V _I0 . Here, if the output voltage V _I1 of the constant voltage circuit F is designed to have zero temperature dependency as described above,
The temperature dependence of _E0 can be made almost zero.

It is needless to say that V _{IO can} have a desired temperature dependency as required.

FIG. 43 shows another embodiment of the feedback circuit H in FIG. In the embodiment shown in FIG.
Do not connect 5I directly to the resistor, and use the bipolar transistor Q ₉₁
Was connected to the base electrode. Since the although by connexion current connexion bipolar transistor Q ₉₁ are Zohaba further be realized a high-speed operation than the 42 FIG. Also, the load current of GD can be reduced. In Fig. 43, equations (11) and (12) are Therefore, the values of the resistors R ₉₁ and R ₉₂ may be determined so as to satisfy the expression (14). However, in this case, as is clear from equation (14), _Therefore , the temperature dependency of the voltage V _I0 does not match the temperature dependency of the voltage V _I1 due to the second term of the equation (15). In this case, from equation (15), Therefore, according to desired V _I0 , ∂V _I0 / ∂T, (15),
It is only necessary to design so as to satisfy (16), and it goes without saying that ΔV _I0 / ΔT can be made zero.

Now, using the above circuit, the power supply voltage (V _CC )
Even if the value becomes excessive, the output voltage can be kept at a constant value lower than V _CC , so that there is an advantage that a fine element can be prevented from being destroyed. However, on the other hand, it may not always be suitable for conducting an effective aging test.

In a normal integrated circuit, after the final manufacturing process, a voltage higher than the voltage used in normal operation is intentionally applied to each transistor in the circuit, and a transistor that is likely to cause a failure due to a gate oxide film defect or the like is initially found. Aging tests are performed to ensure reliability. In order to improve the defect detection rate by this aging test, it is necessary to apply a voltage slightly lower than that of a normal element to a destruction. However, in the integrated circuit chip configured to supply a constant power supply voltage via the voltage conversion circuit inside the chip as described above, there is a possibility that a sufficient aging voltage may not be applied to the internal circuit. In that case,
As shown in Fig. 44, the voltage V generated by the voltage conversion circuit
_I may be designed to increase when the external power supply voltage V _CC becomes excessively large. In Figure 44, the external power supply voltage
From V _CC is V _CI to V _CE keeps internally generated voltage V _I at a constant value V _I0, V _CC is such that together a connexion increase the V _CE rises electromotive force El and V _CC. Since the V _I also increases and raising the V _CC or more to V _CE in, V _CE the V _CC at the time of aging test
When the above is raised, a voltage higher than _VIO can be applied to the circuit in the chip. Therefore, an effective aging test can be performed.

FIG. 45 shows a specific embodiment for realizing the voltage characteristics shown in FIG. Constant voltage circuit F in Figure 45, the resistance R ₁₁₁ between the collector and the terminal D of the bipolar transistor of the output stage J in the embodiment of Figure 37
The differential amplifier GD and the feedback circuit H were connected in the same manner as in FIG.

Also, connect the collector of the bipolar transistor Q ₁₁₁ to the base of the bipolar transistor Q _112, the emitter of the bipolar transistor Q ₁₁₂ to the control line 5I, and a collector connected to V _CC. In this circuit, the external power supply voltage V
_CC is, after reaching the stable point V _I0 of the output voltage V _I, at equal constant V _I is V _I0 until the bipolar transistor Q ₁₁₂ is turned on, after the bipolar transistor Q ₁₁₂ is turned ON output voltage V _CC Rise with. Bipolar transistor Q
_The point V _{CE at which 112} turns on is given by the following equation.

V _CE = V _I0 + V _BE (Q ₁₁₂ ) + R ₁₁₁ · i ₁₁ (17) where the current i ₁₁ is a current flowing through the resistor R ₁₁₁ and satisfies the following equation.

i ₁₁ = V _I1 / R ₁₁₂ … (18) In it, V _I and V _CC rises above V _CE is to follow connexion rise to the following equation.

According to this embodiment, as described above, since the external voltage V _CC exceeds V _CE voltage V _I increases with the V _CC, it is possible to perform effectively the aging test.

By the way, when the temperature dependence of V _I0 is designed to be zero, V
_From equation (19), the temperature dependence of _CE On the other hand, the temperature dependence of V _I at the V _CC> V _CE is Becomes Here, when the circuit of FIG. 42 is used for the feedback circuit H, from the equation (12) Therefore When V _CC > V _CE , Becomes

Temperature dependence of the normal V _CE is the temperature dependency of V _I at about -2 mV / ° C. Since the temperature dependence and V _CE of V _CE> V _CC is very small.
When the embodiment of FIG. 43 is used for the feedback circuit H, And from equation (14) Therefore, from equations (21) and (22), V _CC > V _CE Becomes Here, from equations (15) and (19), Let η be Holds. Therefore, for example, when V _CE = 6 V and V _I0 = 4 V, V _BE (Q ₁₁₂ ) = V _BE (Q ₉₁ ) = 0.8 V 23V _CE / ∂T and V _CC from (23-A) and (23-B)
∂V _E / ∂T at V _CE is about -1.25 mV / ° C and about +1.25, respectively.
mV / ° C. and since the temperature dependence of V _E at a temperature storability and V _CC> V _CE of V _CE even when a circuit of FIG. 43 in the feedback circuit H is very small. Further, when the circuit of FIG. 43 is used, the value of V _CE is set to almost twice the value of V _I0 , whereby
Temperature dependence of V _I at a temperature dependence and V _CC> V _CE of _CE can also be substantially zero at the same time. That is, V _BE (Q ₁₁₂ )
If BEV _BE (Q ₉₁ ), then (23−C), V _BE when η = 1
≒ 2V _I0 , Becomes Also, from (23-B) Becomes As described above, both when the circuit shown in FIG. 42 is used as the feedback circuit H and when the circuit shown in FIG.
Voltage characteristics of Fig can hardly be realized without temperature fluctuations, can also generate a little voltage V _I of the temperature dependence in the region of the aging test in even V _CC> V _CE in normal operation region in V _CC V _CE , The internal circuit group can be operated stably.

As described above, it is, of course, possible to give temperature dependence to _VIO as needed. Furthermore, when in the temperature dependence of the aging test area must be set independently of the V _I0 is the desired temperature dependence and R ₁₁₁ the collector of Q ₁₁₁ as Figure 37 for the bias connected to V _CC K A current source having a characteristic may be provided separately from F.

In Figure 45 using the bipolar transistor Q ₁₁₂ to raise the voltage V _I at V _CC V _CE. But,
The gate of the nMOS transistor replacing the Q ₁₁₂ by the nMOS transistor to the terminal K, that the also possible of course be constructed by connecting the source to drain to V _CC in E. At this time, since the terminal K is connected to the gate of the nMOS transistor, there is no need to supply a current, so that the design of the constant voltage generating circuit can be facilitated.

According to the embodiment described above, a stable voltage having a desired temperature dependency and not depending on the external power supply voltage within a desired range can be supplied from the control line 5I. Therefore, circuits in the same chip can be operated stably. However, when the current supplied from the control line 5I is particularly large, a buffer circuit for current amplification is added to the voltage conversion circuit A in order to prevent voltage fluctuation, and the output 5I 'of the buffer circuit is used as a control line. I just need.

FIG. 46 shows an embodiment of the buffer circuit.
C _121, C ₁₂₂ is a Kiyapashita for reducing the potential variation of the terminal N _B, the control line 5I '. In Fig. 46, the voltage of 5I '
V _I ′ is V _I ′ = V _CC −V _BE (Q ₁₂₁ ) (V _CC V _I + V _BE (Q ₁₂₁ )... (24) or V _M = V _I + V _BE (Q ₁₂₁ ) −V _BE (Q ₁₂₁ ) (V _CC > V _I + V _BE (Q
₁₂₁ )… (25)

Was but connexion, approximately equal to V _I 'is V _I in the region of the _{V CC ≧ V I + V BE} (Q 121) ... (26) in this embodiment. Temperature dependence of V _I 'by using the embodiment described above the generator of V _I can also be controlled. In this circuit, since 5I 'is connected to the emitter of the bipolar transistor, the control line 5I'
A larger current can be supplied. That is, even when the current supplied to the circuit is large, the voltage V _I ′ can be kept stable.

FIG. 47 shows an example in which the bipolar transistor of FIG. 46 is replaced with a MOS transistor. In this embodiment, V _TH (M
₁₃₂ ) is defined as the threshold voltage of the MOS transistor, and in the region of V _CC ≧ V _I + V _TH (Q ₁₃₂ ) (27), V _I ′ becomes substantially equal to V _I.

Since the threshold voltage of the MOS transistor can be easily controlled, the V _I 'from among low V _CC in this embodiment V _I
And the output voltage V _I ′ can be stabilized.

In the two embodiments described above, the voltage V _I, the range of the output voltage V _I 'is equal to the external voltage of the buffer circuit, (26)
As expressed by the equation (27), the voltage is limited by the forward voltage between the base and the emitter of the bipolar transistor or the threshold voltage of the MOS transistor. It was but connexion example, as an output voltage V _I of the voltage conversion circuit in the external voltage V _CC is higher 4V was designed to be constant at 4V, the output voltage V _I of the buffer of Figure 46 'is, V _CC is About 4.8
Unless it becomes more than V, 4V is not constant. Therefore it may sometimes become narrowed the operation margin of the internal circuit to the external voltage V _CC. In such a case, a buffer circuit as shown in FIG. 48 may be used. FIG. 48 shows that 5I ′ is connected to the drain of a P-channel MOS transistor M141,
Connect the source of the MOS transistor to the external power supply V _CC ,
The gate G141 is controlled by the output voltage of the differential amplifier O. Here, the input terminal of the differential amplifier
The output voltage V _I of the voltage conversion circuit A and the output voltage V _I ′ of the buffer circuit were input. Here, the capacitor C ₁₄₁ is for suppressing the fluctuation of the output voltage V _I ′. According to this configuration, the output voltage V _I ′ by the differential amplifier is
It is kept equal to V _I. The While connexion Figure 46, unlike the embodiment of FIG. 47, stable in a wide range of the external voltage V _CC because the output voltage V _I 'can be equal to the voltage V _I regardless of the external voltage V _CC Voltage can be obtained.

FIG. 49 shows an example of a specific circuit configuration in FIG. 48. In FIG. 49, signals having opposite phases are applied to the terminals P and P, respectively. Hereinafter, the circuit operation when the signal P is at a high level and when the signal P is at a low level will be described.
The same applies when is at a low level and is at a high level.
In addition, the description of the present embodiment is described the V _CC 5V, a V _I as 4V, is the same when in another voltage relationship. For simplicity, it is assumed that the base-emitter voltage of the bipolar transistor is 0.8V. When V _I is 4 V, the base potential V _B153 of the bipolar transistor Q ₁₅₃
Is 1.6V. At this time, 'the potential V _I' of terminal 5I is 4V, the base potential V _{B 154} of the bipolar transistor Q ₁₅₄ becomes 1.6V. Here V _{B 154} also decreases when V _I 'is reduced, collector current of the bipolar transistor Q ₁₅₄ is reduced. On the other hand, the collector current of the bipolar transistor Q ₁₅₃ is to increase, the current flowing through the resistor R ₁₅₁ is increased. as a result
Gate V _GM141 of the MOS transistor M ₁₄₁ is reduced. As a result, the drain current of the MOS transistor M ₁₄₁ increases and V _I ′
Rises to 4V. Conversely, when V _I ′ rises, V
_GM141 rises, MOS transistor M ₁₄₁ is V _I 'is turned off to restore the lowered 4V. Here, diodes D ₁₅₃ to D ₁₅₅ are connected between the collector of bipolar transistor Q ₁₅₃ and V _CC.
Are connected in series, the collector potential does not fall below 2.6V. On the other hand, the base potential of the bipolar transistor Q ₁₅₃ for the base potential V _B153 is 1.6V is always lower than the collector potential. Bipolar transistor Q
₁₅₃ never saturates. Bipolar transistor Q
The base potential of ₁₅₄ V _I '-2.4 V, the collector potential V _CC -2.
QV ₁₅₄ does not saturate because V _I is typically less than V _CC . By the way, when the circuit connected to the control line 5I 'is in the waiting state, the current flowing from 5I' is small and often almost constant. Even by reducing the current flowing through the amplifier at this time, it can keep the V _I constant, it is possible to suppress the power consumption low by reducing the current. For this purpose, the resistance value of the resistor R ₁₅₂ and larger than R _151, MO
The gate widths of the S transistors M ₁₅₃ , M ₁₅₄ , M ₁₅₅ are set to M ₁₅₆ , M
₁₅₇ and M ₁₅₈ , and when the circuit connected to 5I 'is on standby, the potential of the terminal P is set to a low level.
You can switch to a higher level.

It is also possible to use as the V _CONT in FIG. 35, second 49 Figure 7 to 10 diagram the output V _I or V _I 'in addition to such supply of the FIG. 34 of the voltage generating circuit has been described in FIG. As previously mentioned,
According to the embodiment of FIGS. 35 to 49, fluctuations of V _I , V _I ′ due to external voltage V _CC and temperature can be controlled.
The circuit characteristics shown in the figure can be kept constant with respect to V _CC and temperature. Therefore, especially for V _CC,
Or, it is effective when temperature fluctuation is a problem.

So far, specific methods for controlling the circuit operation have been described. Of these, the means for detecting and controlling the characteristics of the internal circuit mainly focus on those that detect voltage values as shown in Fig. 48. I'm sorry. However, depending on the case, a method of detecting and controlling the phase difference of the signal as follows can be used.

FIG. 50 shows a specific embodiment using the configuration of FIG. In this embodiment, two predetermined pulse phi ₁ in the circuit 2 _detects the phi ₂ of the phase time difference Delta] t, and controls the second operation response, is an example of keeping the operating speed constant.

F / F in the figure is a flip-flop of the excisional-reset type, and outputs a signal phi _I of pulse width equal to the time difference Δt of phi ₁ and phi _2. SW _I, SW _R, SW _S is switch, C _I, C _H is the capacitance, V _REF is the reference voltage for reference. Hereinafter, the operation of this circuit will be described with reference to FIG.

First, when phi ₁ is input phi _I is outputted. Thus SW _I is turned on, capacitor C _I is charged with a constant current i C _I
The voltage of the terminal 31 gradually increases. After elapse of Δt, φ
If ₂ is input, phi _I becomes a low potential, SW _I is turned off. It was but connexion, voltage V _HL 31 becomes a voltage proportional to Delta] t. This voltage phi _S is input SW _S is taken into the turned on capacity C _H. Here, if it is assumed that C _I >> C _H , the voltage of 32 becomes substantially equal to V _HL . On the other hand, C _I is the Yotsute SW _R in phi _R turned on, it is discharged to 0V, and prepare for the next operation. C _H V _HL incorporated into is compared with by connexion reference voltage V _REF to the amplifier 7, and outputs a voltage corresponding to the difference to 5, thereby controlling the second operating characteristic. 2
Is constituted by circuits as shown in FIGS. 7 to 20, and its operation characteristics are changed by the voltage of 5, and finally, the values of V _REF and V _HL become equal. Is controlled as follows. As a result, the circuit characteristics of 2 are kept constant.

In the present embodiment, since the operation characteristic of (2) is directly detected and the characteristic is controlled, even if the characteristic changes due to factors other than the fluctuation factors considered in advance, it is possible to respond to the characteristic change, and the characteristic can be extremely accurately determined. Can be controlled. V _REF , i of the present embodiment
Needs to be highly stable to dominate control accuracy,
As V _REF , the embodiments shown in FIGS. 32 and 37 can be used, and as i, the embodiments shown in FIGS. 26 to 33 can be used.

Note that, here, the detection is performed based on the time difference between the operation characteristics φ ₁ and φ ₂ of the circuit 2, but it is also possible to detect the operation current amount and control the characteristics.

FIG. 51 shows an embodiment in which the embodiment in FIG. 50 is applied to the embodiment in FIG. In this embodiment, 2 '4 constitute a second dummy part of, the output phi _1' internal circuitry 2 constituting the senses operating characteristics phi _{2 'in} FIG. 50 the same method as 2 are controlled. As 2 ', a ring oscillator may be formed by using an inverter as shown in FIG. 7, or various circuit types can be selected according to the purpose.

 In this embodiment, the same effect as in FIG. 50 can be obtained.

When the base and collector currents of the bipolar transistor are supplied from the same power supply as shown in FIG. 12 among the embodiments described so far, the base potential is reduced due to the voltage drop due to the collector resistance of the bipolar transistor. There may be a case where the collector potential is temporarily lowered to saturate the bipolar transistor. In this case, as shown in FIG. 52, two collector terminals may be provided, C1 may be used as a collector electrode of the bipolar transistor, and a MOS transistor for supplying a base current may be connected to C2. In this case, since the potential of the second collector electrode is lower than the original potential of the collector C0 of the bipolar transistor, the potential of the base connected to the second collector electrode through the MOS transistor does not become higher than the potential of the collector C0. Therefore, the saturation of the bipolar transistor can be effectively prevented. This embodiment can be used without being limited to FIG.

FIG. 53 is a specific embodiment in which each of the above embodiments is applied to a DRAM.

In the figure, MA is a memory cell array, in which memory cells MC are two-dimensionally arranged. PC is a data line precharge circuit, and SA is a sense amplifier that amplifies a small signal output from the memory cell to the data line, and is composed of both P and N channel MOS transistors. AB is an address buffer circuit that converts address input Ain to internal signal, X-Dec & Dri
v., Y-Dec & Driv. are an X decoder driver and a Y decoder driver, respectively. DP is a data line precharge voltage generation circuit during standby of memory operation, SAD, ▲
▼ is a drive circuit of the sense amplifier SA, WC is a write control circuit for writing the data input signal Din to the memory cell in accordance with the instruction of the write signal WE, and the peripheral circuit is an external input CE for supplying a pulse signal required for the operation of each circuit. Is a main amplifier that amplifies the read signal on the I / O line, and here, the embodiment shown in FIG. 19 is applied. Reference numeral 3 outputs a signal corresponding to fluctuations in manufacturing conditions, use conditions, and the like to 5, thereby controlling the operation of each circuit and stabilizing characteristics. Each circuit is constituted by a circuit as shown in FIGS. 7 to 20 so that it can be controlled by the output 5 of 3.

In the operation of this circuit, when CE is input, the memory operation starts, Ain is amplified by AB, and signals are supplied to X-Dec and Y-Dec. The signal information charges X-Dec & Driv in Yotsute one word line W is stored in the C _S of the selected memory cell in response to is output to the data line. As a result, a small signal appears on the data line and is amplified by SA. Y-Dec
& Driv, the selected data line signal is I / O, ▲
Output to ▼. This signal is amplified by the MA,
Output to the outside as Dout. In the write operation, a signal is written to the memory cell via the WC via the reverse path.

Various purposes can be controlled in the above configuration.

First, there is a control method for keeping the operation speed or the reliability characteristic of the entire circuit constant. As described in some embodiments, the control circuit 3 controls the operation according to the manufacturing conditions and the use conditions. Then, a signal matching each circuit to be controlled may be output to 5 and controlled.

Next, a method of controlling each circuit according to the purpose can be considered. In particular, in a DRAM, since the memory cell array section is configured using the finest elements, the element withstand voltage is lower than the others, and the problem of lowering the reliability is likely to occur. Therefore, it is conceivable to control the memory cell array section for high reliability, and to control other circuits for stable operation speed. A method for keeping the operation speed constant may be in accordance with the embodiments described above. There are several methods for controlling the memory cell array. First, there is a way to keep the electric field of the insulating film thickness of the C _S in the memory cell constant. Information charges Q _S for the stable operation by increasing the C _S may larger, in order to achieve a greater C _S in a smaller area, the dielectric as the insulating film thickness t _OXS within semiconductor chip of in it is common to thinnest dielectric strength of C _S is because the lowest in the chip. To compensate for reliability by keeping the electric field E _OXS constant, depending on the variation in the insulating film, SAD, DP, by controlling the output voltage, such as WC, controls the voltage V _S to be written in C _S do it. At this time, the information amount of charge Q _S is represented as follows.

Here epsilon _OXS is the dielectric constant, A _OXS is the area of the C _S.

Q _S is also kept constant Keeping was but go-between, the E _OXS constant,
The reliability is improved and the operation is stabilized. Further, when the temperature increases, the diffusion layer leakage current in the MC increases, so that it is necessary to increase the minimum information charge amount required for stable operation. Therefore, there is a control method that increases Q _S , that is, E _OXS , as the temperature increases, to further improve the reliability.

In this case, can be controlled without significantly increasing the peak value of the data line charge and discharge current because g _m of the MOS transistor decreases as the temperature rises.

Next, there is a control method focusing on the MOS transistor of the memory cell. This is because this MOS transistor is the finest in a chip, and its breakdown voltage and photocarrier breakdown voltage are often lower than others. Various withstand voltages of the MOS transistor decrease as the gate length _Lg is shorter and the gate insulating film thickness _tOX is smaller. Therefore, as _Lg becomes shorter and _TOX becomes thinner, the voltage applied to the word line, the data line, etc. should be reduced. The control of the applied voltage can be performed in the same manner as described above. As described above, when the temperature decreases, the hot carrier breakdown voltage also decreases. Therefore,
When the temperature decreases, the word voltage, the data line voltage, and the like may be reduced. Thereby, stable and highly reliable characteristics can be obtained. In addition, the control method described here
It is also possible to combine control method that focuses on C _S.

According to the embodiment described above, the operation of the DRAM can be controlled according to various purposes. Note that, as described above, it is necessary to use a fine element in the DRAM in order to achieve higher integration. Currently, although using a 5V as a current voltage V _CC, the future, 4M, to apply to the element that is directly finer 5V Considering the decrease in breakdown voltage of the device to advance the 16M bits and high integration Expected to be difficult. But V _CC is 5V
It is not preferable to lower the value because it places a burden on the user in consideration of compatibility with the conventional DRAM. Therefore, in the DRAM, as shown in FIG. 4 and FIG.
_After generating a voltage lower than _CC to protect the fine elements,
Various controls can be performed.

FIG. 54 shows an embodiment of a control circuit including the above-described power supply circuit. In FIG. 54, 5I1 'is a control line for supplying a voltage V _I ' lower than V _CC to peripheral circuits such as an address buffer decoder and a clock driver, and 5I2 is a voltage higher than V _I 'for a word driver. The control lines for supplying V _CH , 5I3H and 5I3L,
Is a control line for controlling the drive circuit SAD, ▲ ▼. Although omitted here, it goes without saying that the control circuit 3 in FIG. 54 includes other necessary control circuits. FIG. 54 is based on the constant voltage generating circuit F for generating a reference voltage which is suitable for stable aging test, the bipolar transistor Q _112, comparator GD, a feedback circuit H, the reference voltage V _I, address cross Hua , A decoder O, a MOS transistor M ₁₄₁ for supplying V _I ′ lower than V _CC to decoders, clock drivers, etc.
High voltage generating circuit for operation for supplying a high voltage V _CH than _I 'HOP, the drive circuit controls the high voltage generation circuit V _st and the data line voltage V ₀ and the data line charging current for at palliative DR
V, DRV '. According to this configuration, V _I ′ is equal to V _I, and V _CH and V ₀ are also determined based on V _I ′, so that all internal voltages in the DRAM can be controlled by V _I. Therefore, according to the above-described embodiment, it is possible to realize a DRAM with a very stable operation, in which the peripheral circuits of the memory cell array are hardly subjected to the characteristic change due to the fluctuation of the temperature and the _VCC . Also, the aging test can be performed effectively. Note that the constant voltage circuit F in FIG.
When the embodiment shown in FIG. 45 is used, the power consumption can be reduced as follows. That is, FIG.
In the constant voltage circuit F shown in FIG. 45, the output voltage V _I1 is (1
Determined by the resistance ratio as shown in equation 5). The aging voltage characteristic is also determined by the resistance ratio as shown in equation (20). Therefore, the characteristics are not changed by the absolute value of the resistance, and the influence of the manufacturing variation is small. Therefore, by uniformly multiplying the absolute value of the resistance by Z times (Z> 0), only the current can be set to a desired value without changing the resistance ratio.

If the current value is reduced, it may be susceptible to noise from other circuits on the same semiconductor substrate in some cases.
When the semiconductor device including the above is in the operating state, the current flowing through the reference voltage generating circuit F is increased to prevent voltage fluctuation due to noise or the like, and when the semiconductor device is in the standby state, the current may be reduced to reduce power consumption. FIG. 55 and FIG. 56 are specific embodiments for that purpose. In FIG. 55, a pMOS is connected between the positive power supply terminal D of the reference voltage generation circuit F and the external power supply V _CC.
A transistor is provided. In FIG. 56, an nMOS transistor is provided between the ground terminal of the reference voltage generating circuit F and the ground power supply. According to these examples, pM
The current value of the reference voltage generation circuit F can be easily controlled by changing the gate voltage of the OS transistor TM200 or the nMOS transistor TM210. For example, in the embodiment of FIG. 55, when the potential of the gate terminal 200 is decreased, the resistance value of the pMOS transistor M200 is decreased, and the current flowing through the reference voltage generation circuit F is increased. When the potential of the gate terminal 200 is increased, the resistance value of the pMOS transistor M200 is increased, and the current flowing through the reference voltage generating circuit F is reduced. Therefore,
According to the embodiment of FIG. 55, when the semiconductor device including the reference voltage generating circuit F is in the operating state, the potential of the terminal 200 is lowered, and in the standby state, the potential of the terminal 200 is increased. Thus, the voltage value can be prevented from fluctuating, and the current can be reduced during standby to reduce power consumption. In the embodiment of FIG. 56 as well, a similar effect can be obtained by increasing the potential of terminal 210 during operation of the semiconductor device and decreasing the potential of terminal 210 during standby. In the embodiment shown in FIG. 56, an nMOS transistor is used, so that a transistor having a smaller gate width than the pMOS transistor in the embodiment shown in FIG. 55 can be used.
The area occupied by the circuit can be reduced. The 55th
As shown in FIG. 56 and FIG. 56, when a MOS transistor is inserted between the power supply and the reference voltage generation circuit F, the net voltage applied to the reference voltage generation circuit decreases due to the resistance between the source and drain of the MOS transistor. I do. However, the output voltage V _I1 of the circuit shown in FIG. 37 or 45 remains almost constant regardless of the power supply voltage as shown in equation (15), so that the current can be controlled without changing the voltage characteristics. it can.

Driving circuits such as an address buffer, a decoder, and a clock driver which operate using the control line 5I 'in FIG. 54 as a power supply are the same as those shown in FIGS. 9 to 17.
What used V _CC as V _I ′ may be used. Further, V _CONT in FIGS. 7 and 8 may be set to V _I ′ as necessary. In addition,
Although logic circuits such as a NAND circuit used for a decoder and the like are omitted in FIGS. 7 to 17, they can be easily realized, for example, by replacing the DRIV portion with NAND in FIG. By the way, the speed can be increased by using a BiCMOS circuit where the load capacity is large.
Figure, the collector may be left on V _CC if the breakdown voltage of the bipolar transistor Q _N3 in FIG. 12 or the like is enough. At that time, since the collector current is supplied from V _CC ,
Most of the charging current flows from V _CC and V _I ′ needs to supply only the base current. If the collector potential is within the range where the bipolar transistor does not saturate, it does not significantly affect the circuit characteristics.
The supply current of V _I ′ can be reduced. Thereby, V _I ′ can be kept more stable.

Further, the first stage or the like of an address cross Hua external input signal is applied directly, through current increases the power of this portion V _I when the amplitude of the external input signal is insufficient 'When V _I'
In some cases, it may be difficult to keep V _I ′ stable. In that case, it is possible to operate only the first stage at V _CC .

Next, an embodiment for controlling the charging and discharging of the data lines in FIG. 54 will be described.

In DRAM, a data line is a memory cell (an example of a memory cell composed of one MOST and one capacitor)
Is charged and discharged by a well-known sense amplifier formed of a pMOS and an nMOS in accordance with the read information. At this time the charge amount Q _C accumulated in the Kiyapashita the memory cell is the product of the data line voltage V _DL and Kiyapashita capacity C _S. DRA
It is desirable from the viewpoint of reliability to maintain the stable above Q _C M. It was but if not to rely connexion data line voltage V _DL to the external power supply voltage V _CC and temperature can be assured stable and reliable operation regardless of external conditions. The power consumption can be reduced by setting the V _DL lower than V _CC value in the range that does not adversely affect the operation at the same time. Further, for example, in the latest megabit DRAM, it is necessary to charge 1024 pairs of data lines at a high speed simultaneously. The total capacity of this data line is
Since the current reaches 500 to 1000 pF, the transient current becomes a problem. Therefore, it is desirable to reduce the transient current. In addition, it is desirable to perform charging and discharging of the data line symmetrically in order to reduce noise accompanying the charging and discharging of the data line.

This embodiment external power supply voltage dependency of the V _DL and equal to V _I 'data line voltage V _CL is controlled by the above-described voltage conversion circuit, and at the same time eliminate the temperature dependency, the voltage V _DL from V _CC The transient current and the noise are reduced by lowering the power consumption and controlling the data line charging / discharging speed. Hereinafter, this embodiment will be described. The data line is charged by a drive circuit DRV connected to a flip-flop common line cl, which is a sense amplifier including a pMOS. The present embodiment is characterized in that this drive circuit includes a current mirror circuit and a comparator. The current mirror circuit is controlled by a kind of inverter composed of transistors Q ₁ and Q ₂ . Q ₂ is turned on, if Q ₁ is off Q ₃ and the constant current source (i / n) and the output drive transistor Q
_A current mirror circuit is formed with _D, and Q ₂ is off and Q
₁ If on, Q _D is turned off. If the current inlet of the current source in the mirror circuit i / n, the gate width w / n of the MOST, the gate width of Q _D is W, on-current of Q _D is a constant current i. Once you have even i / n with a threshold voltage changes in the variation in Yotsute w or gate length and the transistor fabrication process at a constant driving steady flow Q _D is substantially constant. Here, the reason why the constant current source is set to i / n, w / n is to reduce the current consumption and the occupied area, and it is preferable that n is large.

The comparator outputs the output voltage V _I ′ (eg, 4
V) and is intended to compare the Dekyu voltage V _O. When V _I ′> V _O , the output of the comparator becomes a high voltage, and when V _I ′ <V _O , the output becomes low.

 The operation will be described with the above preparations.

In a normal DRAM, the data pair is not connected during the precharge period.
It is set to approximately half the value of the V _DL, so called half Purichi yer di scheme, Purichiyaji period, the common drive line
cl or all the data line pair is Purichiyaji the V _DL / 2.
In this state, when a pulse is applied to the selected word line, a minute differential read signal appears on each data pair line. This situation is typically shown in FIG. 58 with D ₀ , ▲ ▼ symmetry. After that, the sense amplifier formed by nMOST and pMOST discharges the low voltage side to 0V and the high voltage side
Charged to V _I ′. Discharge is performed by the MOS transistor T _N2 . Here, only charging will be described below. cl is driven by applying an input pulse φ. When the input pulse φ is turned on (high voltage input), the output voltage of the control circuit AND becomes the high voltage, the output voltage V _S becomes the gate voltage V _G is a constant current source Q _D, Q _D are constant load current Drive with i. As a result, 'rises from / 2 at a constant speed, V _I' voltage V ₀ which load V _I and the comparator actuation exceeds the control circuit AN
D output is Q ₁ is turned on becomes a low voltage, Q ₂ is turned off, Q _D is turned off, V ₀ is thus clamped to approximately V _I '. One data line of the I connexion each data line pair to which is charged to 'substantially V _I from / 2' V _I.

When φ is applied to the discharge, nMOST _M3 ′ and T _N2 form a current mirror, so that the speed can be controlled in the same manner as charging.

Zero temperature dependence of the data line voltage V _DL since it substantially equal to the data line voltage V _DL to V _I 'according to the embodiment described above, it is possible to eliminate the external power supply voltage V _CC dependency desired range it can. Further, since the data line can be charged with a substantially constant current, the data line can be charged at a high speed without an increase in transient current. In addition, by keeping i ₀ constant, even if there is a fluctuation in power supply voltage or manufacturing variation, the influence thereof can be minimized. Further, since the data line voltage is kept low, power consumption is also reduced. Further, since the data line charge / discharge speed can be made the same, noise can be reduced.

Next, an embodiment of a word line driving circuit will be described.
In a DRAM, the voltage of a word line is set to be about 2 V higher than the voltage of a data line. When the voltage, for example, 4V data line, the voltage of the word line is required approximately 6V, it is required means for boosting the word line than the value 5V on V _CC. As a circuit for driving a word line by _VH boosted to _Vcc or more, for example, the circuit in FIG. 59 can be used. The V _H generation circuit will be described later.

First, the operation of the circuit in FIG. 59 will be described with reference to the voltage waveform diagram in FIG. When E becomes high potential and C becomes high potential
F potential through nMOS11 is a potential of V _A -V _T11n. Next, when E becomes low potential, 12 (pMOS) turns on and the potential of F becomes _VH . As a result, 13 (pMOS) is turned off, 14 (nMOS) is turned on, the bipolar transistor 15 is turned off, 16 (nMOS) is turned on, and the output W becomes 0V. Note When F is increased to a high potential V _H, A, the potential of C is a V _A, 11 is the potential of F will not be lowered by flowing out current from the F to C because it is off. On the other hand, when C becomes low potential while E is at high potential, 11
Is turned on, and F also has the same low potential as C. As a result, 13 turns on, 14 and 16 turn off, the node G becomes _VH , and the output D is charged to a high potential at high speed. The high potential of this output is V _H −V _BE
It is. In this circuit, as shown by a dashed line in FIG. 60, a period t from when C goes to the high potential V _A to when E goes to the low potential is reached.
Since _CE is long and high potential of F a while stays in V _A -V _T11n, through current flows in 13 and 14, there may be a period in which D remains in poor low potential. Therefore, t _CE
It is desirable to shorten the time. For that purpose, it is sufficient to switch E to a low potential at the same time as C becomes a high potential. This solves the above problem.

According to this circuit, a word line because of the use of bipolar transistors to the output can be charged to V _H -V _BE faster. In FIG. 7, G may be directly output without using the bipolar transistor 15. Since this time, the output voltage rises up to V _H, may be generated equal V _H and the desired word voltage. Therefore, the design of the power supply G becomes easier than when using the bipolar. In addition, there is an advantage that the manufacturing process is simplified because the MOS transistors are used. In the circuit of FIG. 59, it is also possible to control the operation speed by inserting a MOS transistor between the power supply and the power supply as shown in FIG.

FIG. 61 is an embodiment of a circuit for obtaining a high voltage of more than V _CC on the basis of the voltage V _I ', FIG. 62 is an operation waveform. Hereinafter, the operation of the circuit of FIG. 61 will be described with reference to FIG.

The circuit in FIG. 61 is a circuit for boosting the voltage of the VCH terminal in synchronization with the signal ▲ in the DRAM. When the signal becomes low and the DRAM enters the operating state, as shown in FIG. 23, φ _{1PS is changed} to low level, φ _{2PS is changed} to high level, and φ _1S and φ _1SA are changed to high level. As a result, G1, G, which are precharged to the same potential as V _CC in advance,
Through 2, G3, of the G4, G1 and G2 are by connexion boosted MOS capacitor MC _221, MC _222, resulting MOS transistors M _229, M _22A
Current flows from G1 to G4, G3, and the potential of G3, G4 rises. At this time, since G2 is boosted above V _CC, G3, G4 of the potential can be boosted without being limited to the threshold voltage of the MOS transistors M _229, M _22A. Next, φ _1S and φ _{1SA fall} to low level, and φ _2S and φ _3S transition to high level. As a result, G1 and G2 transition to a low level, and G3 and G4 are boosted. At this time, the potential of G2 becomes MOS when _φ2S becomes high level.
Since the transistor _M22B is turned on, the voltage becomes 0 V, and the MOS transistor _M22A is reliably turned off. Difference in timing of this for phi _2S or potential of G2 in such cutlet pulling nozzle does not increase. Was it from connexion G3, current through MOS transistor M _22C are flow 5I2 is boosted. At this time, since six diodes are connected in series between the gate of the MOS transistor G4 and 5I1 ', the potential of G4 becomes
Clamped at V _CL + 6V _BE . As a result, the voltage of V _H is
V _I 'the threshold voltage of the MOS transistor M ₂₂ as V _T22C +
_Clamped to 6V _BE -V _T22C . For example, V _I ′ is 4 V, V _BE
If 0.8V and _VT22C are 0.8V, it will be 8V. Here, six diodes are used, but by changing this number,
When connected to the word driver in so V _H relative to V _I 'can be prevented from becoming a fixed voltage above example V _H can control the word line voltage to a desired value. Next, when the signal of the DRAM goes high, φ _2S and φ _3S are returned to low level, φ _{1PS is set} to high level, and φ _{2PS is set} to low level. As a result, the MOS capacitance MC
The potential of G5 is boosted by ₂₂₀ , and the pMOS transistor M ₂₂₁
, The gate voltages of the MOS transistors M ₂₂₅ , M ₂₂₆ , M ₂₂₇ , and M ₂₂₈ are boosted to V _CC or higher, and the potentials of G 1, G 2, G 3, and G 4 return to V _CC by these MOS transistors. . Note that, MOS transistors M ₂₂₃ is for protecting the M ₂₂₄ prevent high pressure from being applied to the drain of M _224. In the case of using a diode in series, because of the temperature dependence on V _BE, V _H resulting in having a temperature-dependent. To resolve this, the Fuhaba of φ _1S ~φ _3S
The clamp circuit may be omitted as V _I ′ instead of V _CC .
At this time, in order to set the voltage of 5I2 to a desired value, a circuit as shown in FIG. 63 may be used. In FIG. 63, if VCH 'is maintained at a high voltage by a circuit as shown in FIG. Is output. Note that V _I ′ may be used as V _REF , or a voltage having a temperature dependency that cancels the temperature dependency of V _BE of the bipolar transistor Q ₆₃₁ may be applied. As described above, according to the present embodiment, a voltage higher than V _CC can be obtained at 5I2. In the present embodiment, since the _VH is boosted during the operation of the DRAM in synchronization with the signal ▲ ▼, the power is not consumed by the boosting operation during the standby period when there is no need to supply the current from the _VH, and the low power consumption is achieved. Operation is possible. However, depending on the DRAM usage conditions,
The waiting state may continue for a long time, and the potential of _VH may be reduced by some leakage. In that case, a circuit for compensating for the leakage during the waiting period may be separately provided. For this purpose, the embodiment shown in FIGS. 61 to 63 in which the capacity and the size of the transistor are reduced and the current driving capability is reduced may be separately provided and operated independently of the triangle. Alternatively, a circuit as shown in FIG. 64 may be used. Hereinafter, the operation of the circuit of FIG. 64 will be described with reference to FIG.
Is low, MOS transistors TM ₂₄₀ , TM ₂₄₁ , TM
_{According to 243} , G ₂₄₀ , G ₂₄₁ and V _H are pre-charged near V _CC . Next, when φθ is raised to a high level, the inverter I ₂₄₁
And output respective high-level I _242, a low level. It was Although boosted connexion G ₂₄₀ is above V _CC, G ₂₄₀ current flows to G ₂₄₀
Potential rises. Next, when φθ is set to a low level, the outputs of the inverters I ₂₄₁ and I ₂₄₂ are set to a low level and a high level, respectively, so that G ₂₄₁ is further boosted and a current flows to V _H. As described above, the potential of _VH rises by periodically raising and falling φθ. Diode QD ₂₄₀ ~ with increasing V _CH
Potential of Yotsute G _246, V _G246 to QD ₂₄₅ also rises maintain the relationship V _CH -6 V _BE. 'When the -V _T246 + 6V _BE above, V _G246 is V _I' MOS transistor V _H when the threshold voltage is -V _T246 of TM ₂₄₆ is V _I -V _T56 and Do connexion, TM ₂₄₆ is turned off, D247
Becomes 0 V by the MOS transistor TM ₂₄₇ . As a result the voltage of the output theta ₅ of NAND circuit NA240 is fixed to high level step-up operation is stopped. Thereafter, the potential of V _H is lowered by the current I _H flowing from the control line _{5I2, V I '-V T246 +} 6V BE
In the following _cases, M ₂₄₆ is turned on again, and the boosting operation of _VH starts.

According to this circuit as described above, it is possible to keep the potential of the V _H higher than _{V CC V I '-V T246 +} 6V BE. V _I ′ is 4V,
If V _T246 is 0.5V and V _BE is 0.8V, V _H will be 8.3V. According to this embodiment, as described above, by combining the level shift circuit described above with Chiyajiponpu circuit, it is possible to keep the output voltage V _H to a higher fixed voltage than V _CC. It is needless to say that the number of diodes QD _{240 to} QD ₂₄₅ for clamping may be increased or decreased as the case may be. Further, if when the current flowing through the QD ₂₄₀ ~QD ₂₄₅ than V _CH is too large by the QD ₂₄₅ as the 66th view and a bipolar transistor, by connecting the collector of the V _CC based on the output of the QD _244, The current can be reduced to 1 / h _FE . The number of diodes may be determined so that the difference between the voltages V _H and V _I ′ has a desired value. Further, it is possible to replace the MOS transistor TM ₂₄₈ other elements such as a resistor. When a MOS transistor is used, a high resistance value can be easily obtained with a relatively small occupied area by setting the gate length _Lg larger than the gate width W.
Further, here, a pn junction type diode is assumed as the diode. A pn junction diode can be easily realized by connecting, for example, a base and a collector of a bipolar transistor. For this reason, it can be formed simultaneously with the bipolar transistor, and the manufacturing process can be simplified. At this time, if the resistance is also realized using the base layer of the bipolar transistor, the process can be further simplified. Since the forward voltage V _BE of a pn junction diode is usually about 0.8 V, the difference between the voltages V _H and V _I ′ in the embodiment of FIG. Although not possible, the difference between V _H and V _I ′ may need to be set to a value other than n times 0.8 V (n = 1, 2,...) In some cases. At that time, if a try bract key diode having a forward voltage V _F of about 0.4V, can set the value of _{V H V H = V I '} -V T246 + iV F becomes, 0.4V as a unit. Also,
Of course, an nMOS diode as shown in FIG. 67 may be used, and in this case, the threshold voltage of nMOST _MA is changed to V
Since the _{V H = V I '-V T246} + iV TMA as _TMA possible potential difference variable V _TMA units. An arbitrary potential difference can be created by using a circuit as shown in FIG. 4 instead of a diode. In FIG. 4, the potential difference between terminals 3A and 3B is Since it and can alter the connexion continuously potential difference due to changing the ratio of R _A and R _B. In addition, various modifications are possible. In the embodiment shown in FIG. 69, the level shift circuit L shown in FIG. 1 is constituted only by nMOS. In this embodiment, the clamp diode is an nMOS diode, and the bipolar transistor Q ₁ and the resistor R are each an nMOS diode.
M ₅₁ and M ₅₂ were replaced. In this embodiment, 'the relationship between the threshold voltage of T _M51 V _TM51, MOS diode V _H = V _I the threshold voltage as V _TD of' V _H and _{V I -V T246 + V TM51 +} nV TD becomes It can be set a potential difference the threshold voltage V _TD units. In this embodiment, the current flowing through the nMOS diodes MD51 to MD5i is the bias current I flowing through the nMOSM _53.
Since it is only _N , there is no need to increase the current supply capacity of 5I2 more than necessary. Further, in this embodiment, since it is not necessary to use a bipolar transistor and is constituted only by a MOS transistor, an LSI comprising only a MOS transistor is used.
It is suitable to be applied to. The gate voltage, gate length, and gate width of the MOS transistors M ₅₁ and M ₅₃ may be determined so that the currents I _R and _IN have desired values. For example, if set to 10 times the value of I _R with respect to I _L, the variation of the drain current of the MOS transistor M ₅₁ can be kept substantially constant V _L can be suppressed to about 10%. In the above embodiment,
When the temperature characteristic of the clamp circuit becomes a problem, the source voltage of the MOS transistor TM ₂₄₆ can be made to have a temperature dependency to compensate for the temperature dependency of the clamp.

The present invention is effective even when applied to SRAM as well as DRAM as described above. FIG. 70 is an example of an SRAM memory cell configured using an nMOS transistor and a resistor. For example, if the voltage V _C70 is supplied from the voltage conversion circuit of the present invention, the temperature dependency of the memory cell characteristics and the dependency of the external power supply voltage can be eliminated, thereby realizing extremely stable memory operation such as improved soft error resistance. it can. At this time, V _C70
Since the supplied current, that is, the holding current of the memory cell is very small and almost constant DC current, the voltage V _C70
Can be easily maintained at a constant accuracy. Further, if the voltage of the data lines DL and ▼, that is, the write voltage or the voltage of the word line W is stably controlled, the reliability is further improved. For this purpose, the voltage V _I obtained according to the invention is
If the write voltage is determined based on the above, the temperature dependency and the external voltage dependency can be eliminated, and the reliability can be further improved. In addition, a stable and highly reliable operation can be realized by performing the above-described control on the driving circuit and the differential amplifier used for the peripheral circuit of the SRAM.

Further, the present invention is also applicable to a logic LSI other than a memory. In FIG. 53, the control circuit detects the characteristics of the peripheral circuit by using 6, but this detection can be performed at various places according to the purpose. For example, the time until the word line is applied and the sense amplifier minute signal is amplified is detected, and based on the result,
There are various control methods such as changing the drive voltage and drive current of the SA to control the operating characteristics of the array unit. Also,
Although the description has been given by taking the MOS transistor and the bipolar transistor as examples of the main constituent elements, the principle of the present invention can be applied to other elements formed of a compound semiconductor such as GaAs. In addition, although the element constant of the MOS transistor was mainly taken up as the characteristic variation factor,
It goes without saying that variations in the current amplification factor, cutoff frequency, forward voltage and the like of the bipolar transistor can be dealt with similarly. Further, in each of the embodiments, the description has been made with the main object of keeping the various characteristics constant. However, if the present invention is used, the fluctuation due to the manufacturing conditions such as the gate length and the threshold voltage, the power supply voltage, If the fluctuation of the operating conditions such as temperature fluctuates to increase the speed of the semiconductor device, control is performed so as to further increase the speed,
Conversely, if the manufacturing conditions and the use conditions fluctuate to lower the speed of the semiconductor device, it can be controlled to further lower the speed.

Although the embodiments described so far have been described mainly with respect to the TTL interface, it is needless to say that the same can be applied to other cases such as ECL.

〔The invention's effect〕

As described above, according to the present invention, a stable and highly reliable semiconductor device can be realized even when there are fluctuations in manufacturing conditions, use conditions, and the like. At the same time, the yield of non-defective products can be kept high during mass production, so that the semiconductor device can be manufactured at lower cost than conventional semiconductor devices.

[Brief description of the drawings]

1 to 6 are views showing an embodiment showing the basic concept of the present invention, FIGS. 7 to 52 are views showing specific embodiments of the present invention,
FIGS. 53 to 69 and 70 show a DRAM and an SRAM according to the present invention.
FIG. 1 ... chip, 2 ... internal circuit, 3 ... control circuit, 5 ...
... control lines.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Goro Tachibana 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Yoshiki Kawajiri 2-280 Higashi Koikebo, Kokubunji-shi, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Takayuki Kawahara 1-280 Higashi Koikebo, Kokubunji-shi, Tokyo Hitachi Central Research Laboratory Co., Ltd. (56) References JP-A-61-113195 (JP, A) JP-A-56-166352 (JP) JP-A-61-217991 (JP, A) JP-A-57-172587 (JP, A) JP-A-62-65937 (JP, A) JP-A-62-5422 (JP, A) 62-171315 (JP, A) JP-A-62-73755 (JP, A) JP-A-56-120158 (JP, A) JP-A-59-132014 (JP, A) JP-A-61-156762 (JP, A A) JP-A-49-11238 (JP, A) JP-A-62-69306 (JP, A) JP-A-58-188388 (JP, A)

Claims (10)

(57) [Claims] A plurality of memory cells; a plurality of word lines respectively connected to gates of MOS transistors in each of the plurality of memory cells; and a word line driving circuit for driving the word lines. A semiconductor device, further comprising: a first voltage generation circuit supplied with an operation voltage and supplying a voltage higher than the operation voltage to the word line drive circuit, wherein the word line drive circuit includes the first voltage generation circuit A current path between the output of the first voltage generation circuit and the word line to be selected. The first voltage generating circuit increases the operating voltage to a voltage higher than the operating voltage by a charge pump operation based on a pulse signal supplied to the first voltage generating circuit. A booster circuit for a semiconductor device characterized by a control circuit for controlling the charge pump operation of the booster circuit in accordance with the output level of the reference described above booster circuit the output of the booster circuit. A first circuit for determining an output level of the booster circuit and forming a control signal in accordance with a result of the determination; and a booster circuit responsive to the control signal from the first circuit. 2. The semiconductor device according to claim 1, further comprising a gate circuit for controlling the pulse signal supplied to the circuit. 3. The first circuit receives an output level of the booster circuit and forms an output level-converted to the operating voltage level, and responds to the output level-converted by the input circuit. 3. The semiconductor device according to claim 2, further comprising: an output circuit for generating said control signal of said operating voltage level. 4. The input section circuit includes a level shift element that uses a voltage between terminals of a diode as a level shift voltage, and an output of the level conversion according to an output of the booster circuit by the level shift element. 4. The semiconductor device according to claim 3, wherein said semiconductor device is formed. 5. The semiconductor device according to claim 1, further comprising: a second voltage generating circuit configured to receive an external power supply voltage to form a reference voltage, wherein the first circuit refers to the reference voltage from the second voltage generating circuit. 4. The semiconductor according to claim 2, further comprising a MOS transistor for determining an output level of said booster circuit as a reference, wherein said MOS transistor outputs said control signal. apparatus. 6. The semiconductor device according to claim 5, wherein said second voltage generating circuit has a band gap reference circuit configuration. 7. The semiconductor device according to claim 5, wherein said second voltage generating circuit forms said reference voltage based on a threshold voltage difference between a plurality of MOS transistors. Semiconductor device described 8. The charge pump according to claim 1, wherein the booster circuit has a first capacitive element for receiving a pulse signal supplied through the gate circuit at one end thereof, and a first capacitive element for the charge pump.
A charging circuit for providing charging electrification to the other end of the capacitive element of
8. A rectifying MOS transistor which receives a voltage at the other end of the first capacitive element for the charge pump and forms an output of a booster circuit, wherein the rectifying MOS transistor is provided. 2. The semiconductor device according to claim 1. 9. The charge pump in the booster circuit according to claim 1, wherein the charge pump circuit forms a voltage boosted by a pulse signal having a phase different from a pulse signal applied to one end of the charge pump first capacitor. 9. A charge pump according to claim 8, wherein said charge pump second capacitor is charged by said charge pump second capacitor. Semiconductor device. 10. The semiconductor device according to claim 1, wherein said memory cell is a dynamic memory cell that retains information by a capacitance.