JP2914989B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a semiconductor device, and more particularly, to a highly integrated semiconductor device including fine elements that can support a wide range of power supply voltages and power supply types.

[Prior art]

In recent years, portable electronic information devices represented by laptop personal computers and electronic organizers, solid-state recorders for recording audio without using a magnetic medium, and portable cameras represented by solid-state cameras (electronic still cameras) for storing images. Electronic media devices are beginning to appear on the market. For these portable electronic devices to become widespread, the key is to realize an ultra-high-integrated circuit (hereinafter abbreviated as ULSI) capable of battery operation or information retention operation (battery backup) using a battery. On the other hand, there is an increasing need for a semiconductor disk that can be accessed at a higher speed than a magnetic disk as a large-capacity auxiliary storage device for realizing a higher-performance computer. The semiconductor disk requires an ultra-large-capacity memory LSI capable of holding information by a battery. The following are required for ULSI used in these applications.
(1) Operation in a wide power supply voltage range (1 to 5.5 V). This allows other types of power supplies, such as current TTL compatible digital L
5V which is the reference power supply voltage of SI, 3.3V which is one of the standard power supply voltage candidates of the conventional TTL compatible digital LSI, 3 ~ 3.6V which is the typical output voltage of the primary battery using lithium, etc. A single chip can handle the typical output voltage of a cadmium and nickel secondary battery of 1.2V. (2) Response to time-dependent (short-term or long-term) changes in power supply voltage. This eliminates the risk of malfunctioning even if the battery voltage changes over time or a voltage change occurs due to power supply switching during movement between the standard operation and the battery backup operation. (3) Reduction in power consumption during operation or battery backup operation. Thus, the battery can be operated for a long time even with a small battery. (4) Transient current reduction. As a result, the transient fluctuation of the battery voltage can be reduced, and malfunction can be prevented. An example of a microprocessor product that operates over a wide power supply voltage range is described in page 148 of the NEC Corporation 4-bit Microprocessor Handbook. The product model name is μPD7507SC. The operating power supply voltage range of this microprocessor is 2.2 to 6.0V. Further, information of the data memory can be held at a minimum of 2V. Similarly, in the case of a static memory, the recommended operating power supply voltage is generally 5 V, and the information retention (retention) is generally 2 V. As dynamic memory for battery backup,
Examples of reducing the current consumption during information retention (refresh) are described in IEEJ Journal of Solid State Circuits, Vol. 23, No. 1, No. 12-
Page 18 (1988) (IEEE Jounal of Solid-State Circui)
ts, Vol. 23, No. 1, pp. 12-18, February 1988). In this case, both the standard operating power supply voltage and the power supply voltage for retaining information are 5V.

[Problems to be solved by the invention]

Although the microprocessor and the static memory described above have a wide operating power supply voltage range of 2 to 5 V, they are designed around a power supply voltage of 5 V.
For the operation outside the permissible power supply voltage fluctuation range (usually ± 10%), the operation speed (equivalent to the maximum clock frequency for a microprocessor and the access time for a static memory) is guaranteed. In particular, the operating speed is usually significantly reduced particularly at a low power supply voltage. In addition, since the operating speed depends on the power supply voltage depending on the product, the speed must match the slowest operating speed of the LSIs that compose the system. This makes the system design at a low power supply voltage extremely difficult. Since these LSIs have a minimum operating power supply voltage of 2.2V,
It was not possible to support all of the various types of power sources described above, and the system configuration was restricted. Also, consider the case where the above-described dynamic memory is incorporated into a system. Its minimum power supply voltage is 4.5V,
It becomes more difficult to deal with the various types of power sources described above. In particular, since there is no difference between the standard operating power supply voltage and the power supply voltage at the time of retaining information, the configuration of the power supply switching circuit becomes very complicated, and it becomes difficult to retain information. The miniaturization of semiconductor elements is rapidly progressing, and if a processing technology of 0.5 micron or less is used, it is possible to configure a so-called system LSI in which a certain degree of system is integrated on one chip. Such a system LSI
It is required that the operating power supply voltage ranges and operating speeds of the respective LSI blocks constituting the LSIs be matched.
However, as described above, such a system LSI cannot be configured only by combining conventional LSIs. An object of the present invention is to make it possible to cope with various power supply voltages, to reduce power consumption, and to make use of element performance suitable for fine processing.

[Means for Solving the Problems]

The above purpose has a low power consumption mode suitable for battery backup and operates even with a low power supply voltage of at least about 1V
This can be achieved by configuring the device with an LSI circuit block, a power supply voltage conversion circuit that provides an internal power supply environment optimal for the operation mode to the LSI, and an input / output circuit that converts a signal amplitude.

[Action]

By operating the main LSI block that stores and processes information at a substantially constant low voltage regardless of the value of the external power supply voltage, it is possible to obtain a substantially constant speed performance over a wide power supply voltage range. Also, if necessary,
Since the external power supply voltage can be reduced by the operating voltage of the LSI block, the power consumption during information retention can be reduced to the minimum necessary value, and the battery backup circuit can have a simple configuration. Furthermore, since the optimum operating voltage that matches the characteristics of the fine elements that make up the main LSI block can be limited independently of the value of the external power supply voltage, high integration, high speed, and low power consumption must be simultaneously achieved. Can be.

【Example】

 FIG. 1 illustrates the basic concept of an LSI chip according to the present invention.
This is an example. In the figure, reference numeral 1 denotes an LSI chip, which is generally used.
LSI chip with information storage function or information processing function
Points, such as dynamic and static types.
Random access memory (RAM) or serial access
Memory (SAM) or read-only memory (ROM)
Which memory LSI and even microprocessor (MP
U), memory management unit (MMU), floating point
Logic LSI such as arithmetic unit (FPU),
Any form, such as a system LSI that integrates multiple
A type LSI chip may be used. In addition, its components are
Transistor, MIS transistor, these elements
Combination of elements or materials other than silicon, such as gully
An element of arsenic may be used. 2 is the fall of the external power supply voltage
Detects the bottom and shifts to battery backup state, power supply
It is an example of a circuit. With such a power supply circuit, commercial power supply
V due to momentary interruption of_EXTIs reduced, the LSI chip
Required information can be prevented from being lost. Among them, 3 is power supply
Voltage drop detection circuit, SW
Switch for preventing current from flowing to the source terminal;
Is the switch control signal, B is the battery, V_BTIs the voltage
In the information retention mode, this current is used as a power supply
The whole top works. D indicates that current flows through the battery during normal operation.
This is a diode for preventing the light from entering. This power supply
Depending on the circuit, V_EXTBut information retention
At times, V_BTIs applied to the power supply terminal (PAD1) of the chip
Is done. Now, in this example, the difference between the normal operation and the
Detected by detection means on the LSI chip. Where 5a, 5b
Is a main circuit block, 5 is a set of them, 6 is a chip
Power supply voltage V input from outside_CCThe power supply of each circuit block
Pressure V_CL1, V_CLnPower supply voltage conversion circuit
You. Among 6, 6 a and 6 c are conversion circuits for normal operation, 6
Reference numerals b and 6d denote conversion circuits for holding information. General
In addition, when information is retained, the circuit
Since the operating voltage and operating current can be small, supply the power supply voltage.
Supply current of the supplied voltage conversion circuit
No problem if dropped. This allows the main circuit block
Power consumption of the entire LSI chip
The flow can be significantly reduced. In this example,
Shows a method of switching between two voltage conversion circuits.
The number of conversion circuits may be three or more. Also, 1
Output voltage and current consumption using two voltage conversion circuits.
You can change it. SW6a and SW6c are V_CCIs V_CL1And V_CLnUp to a value approximately equal to
If it drops, the power supply voltage V_CCDirectly on the circuit block
Switch to add. Using switches
The voltage conversion circuit is turned off and the current consumption is further reduced.
Can be reduced. In the above example, the switch and
A power supply voltage conversion circuit is constituted by a plurality of voltage conversion circuits.
Was described, but if a similar effect is obtained, one
May be used. Also, in FIG.
Is the reference voltage V_LIs a generation circuit. Based on this voltage, the internal
Source voltage V_CL1And V_CLnOccurs. 8 is an information holding operation state
This is a circuit for generating a signal PD indicating that there is. How PD occurs
As the power supply voltage V_CC
And the reference voltage Vcx, and if the former is smaller than the latter,
The method of outputting PD at the time is used. 10 is Remi
This is a circuit for generating the enable signal LM. Power supply voltage is
Voltage conversion circuit (voltage limiter) higher than the unit power supply voltage
High voltage (“1”) when operating
Low when the voltage drops to a value equal to the internal power supply voltage.
Outputs voltage (“1”) respectively. Power in the latter case
Apply voltage directly to the circuit block and simultaneously convert the voltage
Keep the current consumption low without operating the circuit. Shown in the figure
In the example, the power supply voltage V_CCAnd reference voltage V_LXAnd compare the former
LM is output when is larger than the latter. Two letters
The power supply voltage of the power supply voltage conversion circuit and the power
Current consumption can be switched. 7 in the figure
The I / O buffer 11 is used to control signals and data with the outside of the chip.
I / O bus for sending and receiving, 12 is inside the chip
For exchanging control signals and data between circuit blocks
It is an internal bus. The input / output buffer also functions as a level conversion circuit.
The logic signal amplitude inside the chip and the external logic signal
Transfer control signals and data even if the amplitudes do not match.
can do. In the information holding operation state,
Transfers data with control signals when the chip is closed outside and inside
Since there is no need to perform the
Turn off the output buffer. FIG. 2 (a) shows the power supply voltage V_CCAnd internal power supply voltage V_CLconnection of
It is a figure showing an example of. In the figure, the horizontal axis is the power supply voltage V_CC,
The vertical axis is the internal power supply voltage V_CLCorresponding to Here, the standard
The source voltage is 3 to 3.6 V, the power supply voltage for holding information is 1 to 2 V,
Reference voltage for switching between quasi-operation and information retention
V_CX2.5V, but the minimum value V of the standard power supply voltage_{CC (min)},
Maximum power supply voltage V when information is retained_{BT (max)}, Reference voltage V_CX
Between_{BT (max)} <V_CX<V_{CC (min)} If the following relationship holds, the values may not be the values shown here.
I don't know. In addition, the internal power supply voltage V during standard operation_CLIs
1.5V, but the power supply voltage V_CCOf the circuit within the range not exceeding
It is OK to set an appropriate voltage value according to the operating performance.
No. In this example, the power supply voltage is 1.5 V or less.
And power supply voltage V_CCIs directly applied to the internal circuit,_CL
Is set to 1.5V. In this LSI chip, the power supply voltage V_CCChanges over time
The internal power supply voltage V_CL, Two control signals LM, PD
FIG. 2 (b) shows an example of each time change. here
Then time t₀~ T_ThreeOver the power supply voltage V_CCLow to 3.5-1V
Lower, time t_Four~ T₇Over the power supply voltage V_CCTo 1-3.5V
I'm thinking of going up. Power supply voltage V_CCIs V_CL= 2.5V
T₁~ T_FiveSignal PD is high voltage (“1”) during
And the chip enters the information holding state. Also, the power supply voltage
V_CCIs V_LXT = less than 1.5V_Two~ T_FiveSignal LM
Is low voltage (“0”), and the chip has the power supply voltage V_CCIs straightforward
Contact and applied. Note that the voltage values shown here are
This is an example, and other combinations of voltages can be similarly applied. FIGS. 2 (c) and (d) show the limiter enable
An example of a method and a circuit configuration for generating the
You. The signal LM is the power supply voltage V_CCWhen we lowered
And the internal power supply voltage V_CLHigh for the first time equal
Just change from voltage (“1”) to low voltage (“0”)
No. In this example, the power supply voltage V_CCVoltage β × V proportional to
_CC(0 ≦ β ≦ 1) and the reference voltage V_LAnd comparison by comparison circuit
High voltage (“1”) when the former is large, small when the former
Sometimes a low voltage ("0") is output. Power supply like this
Voltage V_CCBetween high voltage and low voltage using a voltage proportional to
By inputting the voltage, the voltage gain of the comparator
Good for circuit operation, such as large size
No. For example, β = 0.5, V_LV = 0.75V_LX= 1.5V
And the power supply voltage V_CCIs higher than 1.5V
Cable signal LM becomes high voltage ("1"), and the voltage conversion circuit
Operate. Where power supply voltage V_CCThe voltage proportional to
It can be caused by division or the like. FIGS. 2E and 2F show the information holding state signal PD.
An example of a method and a circuit configuration for generating the above will be described. Basic
Can be configured by a circuit similar to the LM generation circuit described above.
In this case, the power supply voltage V_CCVoltage α × V proportional to_CC(0 ≦ α
.Ltoreq.1) is input to the inverting input of the comparison circuit. For example,
α = 0.5, V_LWhen = 0.75v, V_CX= 2.5V, power supply
Pressure V_CCIs 2.5V or less, the information holding state signal PD is high voltage.
(“1”), and the information is held. Here, the power supply
Pressure V_CCThe voltage proportional to₁And R_TwoGenerated by resistance division
Alive. Resistance R₁And R_TwoIndicates that the
Pure diffusion layer, polysilicon, and MIS-FET channel
Any configuration may be used, such as a resistor. FIG. 3 (a) includes a static memory as a part thereof.
1 shows an embodiment in which the present invention is applied to an LSI. Figure
Inside, 5c is a memory cell array of static memory, 5d is
Circuit blocks that do not need to hold information such as logic circuits.
And each power supply voltage is V_CL2And V_CL1It is. Note
The recell is four N-channel MOS-FET T₆~ T₉And two
Anti-element R₇, R₈It consists of Assuming that the resistance value is R,
The current value flowing per memory cell is V_CL2/ R and
You. Therefore, the noise margin (noise marker)
(Gin) as low as possible within the range that can be secured
It is desirable. In this example, as shown in FIG.
Is V in standard operation_CL21.5V, V when information is held_CL2With 1V
doing. The logic circuit block 5d includes an inverter and a logic gate.
And the like. In the figure, there is an arrow
T₁₁, T₁₃Is P-channel MOS-FET, other T_Ten, T₁₂Is N
2 shows a channel MOS-FET. When holding information,
Since the logic circuit does not need to operate, supply the power supply voltage.
There is no need to pay. Therefore, here, the standard operation
V_CL11.5V, V when information is held_CL1Is set to 0V. Internal power supply
Voltage V_CL2And V_CL1Is the power supply voltage conversion circuit 6e or switch.
P-channel MOS-FET T operating as switch₁With
Be paid. The power supply voltage conversion circuit is a differential amplifier circuit A₁, Differential
A resistor created to control the operating current of the amplifier circuit
R_ThreeAnd two N-channel MOS-FETs T_Three, T_Four, Differential amplifier circuit
3 to control the amount of feedback to the inverting input terminal of
Two resistors R_Four~ R₆And P-channel MOS-FET T_Five, And sui
P-channel MOS-FET T operating as switch_Two, And
Has been established. High power supply voltage, internal power supply voltage V_CCOr
The limiter enable signal LM
High voltage (“1”). At this time, T₁Cut off,
At the same time T_ThreeBecomes conductive and the differential amplifier circuit A₁Bias current
Supplied, non-inverting input voltage V_LVoltage proportional to
It is. Conversely, when the signal LM is at a low voltage (“0”)
Is T_ThreeIs cut off, and the bias current is
Will not be supplied. Therefore, the power supply voltage V_CCIs directly inside
It is output as the unit power supply voltage. Information during the information holding operation
The hold signal PD becomes high voltage (“1”). At this time,
Transistor T_TwoCuts off and supplies power to the circuit block 5d.
Stop paying. On the other hand, T_FourCut off the differential amplifier circuit
The value of the bias current of the resistor R_ThreeDepends on
You. The memorial array consumes in the information holding state
The current is very small and almost constant over time.
It can be regarded as a flow. Therefore, the differential amplifier circuit
The load drive capacity may be much smaller than during standard operation.
Operation even if the bias current is significantly reduced.
There is no. Also at the same time T_FiveAnd the feedback of the differential amplifier circuit
By increasing the amount, the internal power
Voltage is decreasing. This allows the chip
The current consumption of the body can be significantly reduced. In addition, this
In the example, V_L= 0.75V, R_Four= R₆= 3R_FiveAnd this
When V_CL2The value of is 1.5 V during standard operation and 1.
It becomes 0V. FIG. 3 (b) shows the power supply voltage V_CCAnd internal power supply voltage V_CL2And
And V_CL1Is shown as an example. In the figure, the horizontal axis is the power supply
Voltage V_CC, The vertical axis is the internal power supply voltage V_CLIt is. Here the second
As in the example of FIG.
Power supply voltage is 1-2V when switching between standard operation and information retention.
Reference voltage V for performing replacement_CXWas set to 2.5V. Mark
Internal power supply voltage V during quasi-operation_CL2And V_CL1Is 1.5V,
Internal power supply voltage V when information is retained_CL2Was 1V, but
The operating performance of the circuit must not exceed the power supply voltage V.
An appropriate voltage value can be set accordingly. In this LSI chip, the power supply voltage V_CCChanges over time
The internal power supply voltage V_CL2And V_CL1Two controls
FIG. 3 (c) shows an example of the time change of each of the signals LM and PD.
Show. Here, time t₀~ T_TwoOver the power supply voltage V_CCBut
3.3 to 2V, time t_Three~ T_FiveOver the power supply voltage V_CCBut
A case where the voltage rises to 2 to 3.3V is considered. Power supply voltage V_CCBut
A case where the voltage rises to 2 to 3.3V is considered. Power supply voltage V_CCIs V
_CXT becomes less than 2.5V₁~ T_FourSignal PD is high during
Pressure ("1"), and the chip enters an information holding state. Ma
In this time range, the power supply voltage V_CCIs more than 1.5V
The signal LM remains at high voltage (“1”)
is there. According to the above-described embodiment, during normal operation,
It operates quickly and requires minimal power when retaining information.
Static memory or information that can hold information
Implements an LSI that includes static memory as a part of it.
Can be In the above embodiment, a high resistance load is used.
Describes an example using static memory cells
However, in addition, for example, two CMOS inverters and two
CMOS type memory cell composed of selection transistors
Latch circuit using two NAND gates or NOR gates
The present invention is similarly applied to the case where a memory
Can be used. FIG. 4A shows the application of the present invention to a dynamic memory.
An example is shown. In the figure, 5e is a power supply of 1.5V or less
Dynamic memory that operates with voltage
The recell is an N-channel MOS-FET T₁₈And storage capacity C_S1
It consists of. 13 is a memory cell array, 14 is a row
C Address buffer, 15 is the column address buffer
16 is the row address strobe (RAS) input bus.
Buffer 17 with column address strobe (CAS)
Power buffer, 18 is a write enable (WE) input buffer
19, data input buffer, 20 is data output buffer
, 21 is the source of the row address strobe (RAS) signal
A clock generation circuit that generates a control clock at
Control strobe (CAS) signal based on the
Clock generation circuit that generates lock, 23 is write clock
24 is the refresh (RESH) signal generation circuit
Path, 25 is the refresh address generation circuit, 26 is the refresh address
Switch that switches between the flash address and the external input address.
It is a Luchiplexa. Storage capacity for dynamic memory
C_S1Information is stored by storing electric charges in
Therefore, even when information is held, the signal charge is read periodically.
So-called refresh operation,
And some peripheral circuits other than the memory cell array also operate.
It needs to be made. Also ensure sufficient noise margin
Therefore, when information is retained, the same signal as in standard operation is used.
It is necessary to secure the signal charge amount. So, in this example,
As shown in FIG. 4 (b), when information is held and during standard operation,
It does not change the internal power supply voltage and keeps it at 1.5V (constant).
When holding information, input / output with the outside of the chip is required
Therefore, all I / O buffers 14 to 20 are controlled by the signal PD.
Cut off. In addition, the signal PD
Control, and a refresh address is issued when information is held.
Switching to the address output by the raw circuit. Re
During the fresh operation, the signal RFSH goes high (“1”).
You. This signal is input / output to the refresh address generator.
The refresh address is sequentially incremented or decremented.
Let At the same time, RFSH starts the clock generation circuit 21 and resets it.
Generates the clock required for freshness. Internal power supply voltage
V_CLOperates as power supply voltage conversion circuit 6f and switch
P-channel MOS-FET T₁₄And supplied by Power supply
The voltage conversion circuit is a differential amplifier circuit A_TwoOperation of the differential amplifier circuit
Resistor R created to control current₉And three N
Channel MOS-FET T_Fifteen, T₁₆, T₁₇Inverting input of differential amplifier circuit
Two resistors R to control the amount of feedback to the terminal
_Ten, R₁₁It is composed of High power supply voltage, internal
Supply voltage to V_CCWhen descending from
The enable signal LM becomes high voltage ("1"). At this time, T₁₄
become. At this time, T₁₄Cuts off at the same time as T_FifteenBut
Conducted, differential amplifier circuit A_TwoBias current is supplied to
Inverting input voltage V_LIs output. This and
Conversely, when the signal LM is at a low voltage (“0”), T_FifteenBut
And the bias current is not supplied to the differential amplifier circuit.
Become. Therefore, the power supply voltage V_CCDirectly with the internal power supply voltage
And output. During the information holding operation, the information holding signal PD
High voltage (“1”). At this time, T₁₆Cut off
And the value of the bias current of the differential amplifier₉By
I have decided. In the information holding state and when peripheral circuits operate
The current consumption is small during the period when there is no current. Therefore, differential amplification
The load drive capability of the circuit is much smaller than in standard operation
Even if the bias current is significantly reduced,
There is no problem. During refresh operation, the signal RFSH is
Feedback to the conversion circuit 6 and T₁₇And the differential
Set the bias current of the amplifier circuit to the same value as during standard operation.
ing. By doing so, the refresh operation period
Power supply necessary for charging and discharging data lines and operating peripheral circuits.
A stream can be supplied. Therefore, when holding information
The overall chip without reducing the noise margin
The current consumption can be significantly reduced. Note that this example
Then V_L= 0.75V, R_Ten= R₁₁As V_CL= 1.5V
However, other combinations of voltage values and resistance values may be used. In this LSI chip, the power supply voltage V_CCChanges over time
The internal power supply voltage V_CL, Two control signals LM, P
D, refresh signal RSFH and differential amplifier circuit
FIG. 4 (b) shows an example of each time change of the ass current value.
Show. Here, time t₀~ T_TwoOver the power supply voltage V_CCBut
3.3 to 2V, time t_Three~ T_FiveOver the power supply voltage V_CCBut
A case where the voltage rises to 2 to 3.3V is considered. Power supply voltage V_CCIs V
_CXT becomes less than 2.5V₁~ T_FourSignal PD is high during
Pressure ("1"), and the chip enters an information holding state. Ma
In this time range, the power supply voltage V_CCIs less than 1.5V
Signal LM remains at high voltage ("1").
You. During the information retention period, during refresh operation, the standard operation
Bias current I about the same as when making_B1The rest, otherwise
Minute value I_B2Is flowing. In the example described above, row access is performed from the same address bus.
Capture by switching the address and column address temporally
Use the so-called address multiplexer method.
However, there is a general method to capture all addresses at the same time.
Even if it is used, the present invention can be similarly applied. Also, Japanese Patent Application No. 63-
148104 and Japanese Patent Application No. 63-222317.
Dyna to reduce data line voltage amplitude by driving rate
The use of memory allows for lower power consumption memory.
Moly can be realized. FIGS. 5 (a) and 5 (b) show riffs when information is held.
An example of the timing of the refresh signal RFSH is shown. This
Here, all memory arrays are refreshed in 4096 cycles.
FIG. Power supply voltage, for example, 1.5V
Power consumption of the entire memory
Large capacity of about 64Mb
Refresh cycle increased from 4096
This makes it easier to configure the system. Emotion
Transition to the information hold state and concentrated refresh in the first 4096 cycles.
, A relatively short period T_C1Generates signal RFSH
Let me. This is a refresh during normal operation
Control is independent of RFSH internal refresh
It is. By performing such initialization, the state changes.
The refresh cycle specification is not satisfied before and after the execution
Danger can be avoided. In FIG. 5 (a), the collection
After a medium refresh, a certain period T_C2Generates signal RFSH
Let me. On the other hand, in FIG._C3so
Intensive refresh that repeats intensive refresh
The period of the middle signal RFSH is the same as the first burst refresh
Value T_C1I have to. This can be any other value,
Although the same value is used for the configuration of the signal generation circuit, it is convenient.
No. FIG. 6 shows a refresh cycle for the example of FIG. 5 (a).
Period T_C21 shows an example of the chip temperature dependence of the above. Chips
The relationship between temperature and information retention time is, for example, IEE
・ E-Transactions on Electron De
Vices, Vol. 35, No. 8, pp. 1257-1263 (1987)
(IEEE Transactions on Electron Devices, Vol. 35, No.
8, pp. 1257-1263, August 1987)
You. According to this, the chip temperature changes from 0 to 100 ° C
The change in the information retention time is about three digits. Accordingly
And the refresh cycle T_C2Is changed as shown in FIG.
If this is the case, it can be adjusted to the actual information retention characteristics. information
In the holding state, the power consumption of the chip is extremely small
The difference between the ambient temperature and the chip temperature
No. Therefore, by using at low ambient temperature,
The refresh cycle can be extended to further reduce power consumption.
it can. As a result, portable electronic devices powered by batteries
Provide dynamic memory suitable for mounting in etc.
be able to. It has a temperature dependence as shown in FIG.
Such an oscillator circuit is described in JP-A-60-136088. FIG. 7 shows a refresh operation in the example of FIG. 5 (b).
An example when a defect occurs is shown. In the figure, horizontal
The axis is the refresh cycle, and the vertical axis is the cumulative failure frequency. Re
Fresh cycle T_C3Only one bit is defective
ing. If only a small part of the memory is bad,
Set a re-cell on a spare memory previously provided on the chip.
A so-called defect that is repaired by replacing it with a molycell
There are relief techniques. This technology is, for example,
ー E Journal of Solid State Services
-Kits, Vol. 16, No. 5, pp. 479-487 (1981) (IE
EE Journal of Solid-State Circuits, Vol. 16, No. 5, p
479-487, 1981). This technology
Is also suitable for refresh failures as shown in FIG.
Can be used. However, conventional defect relief technology requires
Since it requires a memory cell, it causes an increase in chip area.
There was a drawback. 8 (a), (b) and (c) show
The reason is that refresh failures without using spare memory cells
This is an example of a rescue technique. This is shown in FIG.
Cycle T_C3Only those memory cells that fail
Also a short period, for example T_C4Refreshing with
It is. This will be described below with reference to FIG. Fig. 8 (a)
When using this defect relief technology,
Shows an example of the timing of the refresh signal RFSH.
You. Here, if address 1 has a refresh failure,
I'm thinking As shown in the figure, one concentrated reflation
Cycle T during the next burst refresh from_C4Ad in
Refreshing Les 1 This way, all addresses
The short period T_C4Power consumption compared to refreshing with
The flow can be significantly reduced. Each refresh cycle
Between 4096 × T_C1≤T_C4≤T_C3Must be satisfied.
FIG. 8 (b) shows a refresh address and a refresh address.
An example of a circuit configuration for generating the reset signal RFSH is shown in FIG.
The operation timing of FIG. In FIG.
OSC is clock φ₀Oscillator, DV₁, DV_Four, DV_ThreeIs
Clock φ₀Clock φ having a period that is an integral multiple of₁,
φ_Four, Φ_ThreeFrequency divider, 30 is a 13-bit synchronous
Counter, 31 is a refresh address generator, 32
Is a refresh signal (RFSH) generation circuit, I₁Is Invar
G₁Is AND gate, G_TwoIndicates an OR gate, respectively.
You. The counter is clock φ₁Operates by the reset terminal.
High voltage (“1”) is applied and all counter outputs are low voltage
Counting starts from the state reset to “0”. Out
Output Q when force reaches 4097₁₂Becomes high voltage (“1”),
Stop the number. In the figure, e is a counter enable signal.
You. During the operation of the counter, e is at high voltage ("1").
Output of the refresh address generation circuit_r0~ A_r11To
Is the output Q of the counter₀~ Q₁₁Is output. Counter stops
After stopping, e becomes low voltage (“0”) and a_s0~ A_s11To
Bad address a_s0~ A_s11Is output. Similarly, count
Clock φ during operation₁However, after the counter stops, the clock
Φ_Four, Are output from the refresh signal generation circuit
Is done. As a result, during the operation of the counter, the period T_C1Tsu 4
Intensive refresh is performed 096 times, and after the counter stops, cycle T
_C4Can refresh only defective addresses
You. Here, only one defective address is repaired.
An example has been described, but when repairing multiple defective addresses
The present invention can be similarly applied to the case. According to the above-described embodiment, during normal operation,
It operates quickly and requires minimal power when retaining information.
A dynamic memory that can hold information
Implements LSIs that include dynamic memory as part of
Can be Furthermore, with conventional dynamic memory
Fig. 4 shows the problem of power supply voltage fluctuation.
As shown, the internal circuit is operated at a low voltage such as 1.5V.
The external power supply voltage changes greatly
Can also be operated stably. In the embodiment described so far, the standard operating state
Detection on the LSI chip to detect the difference between the information retention operation state
Operation status from outside the chip.
You can control it. FIG. 9 shows the information holding state
Another aspect of the present invention that controls the migration of
An example is shown. Among them, 4b is input from outside the chip
The information holding state signal 1B is the same as the LSI chip shown in FIG.
LSI chip with information storage function or information processing function
FAD3 is a bond for receiving the information holding state signal.
2 shows a padding. The LSI chip shown in Fig. 1
The difference from the chip is that the detection means and the information
There is no need to provide a means for generating a signal. This chip
The chip may be designed separately from the LSI chip of FIG.
Design of two chips, switching of bonding and aluminum
It may be divided by the master slice of the nickel wiring. FIG. 10 (a) shows the LSI chip of FIG.
FIG. The voltage value of the battery
Is distributed over a wide range, such as 1 to 3.6 V, depending on the type. But
To detect the transition to the information holding state by voltage change
The system can be controlled from outside compared to
Is convenient. FIG. 10 (b) shows the internal power supply voltage V_CLPower supply
Voltage V_CCShows the dependency on In this example,
The quasi power supply voltage range is 1 to 3.6V, and V is 1.5 to 3.6V.
_CLV when = 1 to 1.5V_CL= V_CCAnd do this
This allows for a wide power supply voltage range of 1 to 3.6V
Change in the internal power supply voltage can be kept small,
Power supply with operating performance such as operating speed, current consumption, and operating margin
An LSI having almost no pressure dependency can be realized.
In addition, without changing the power supply voltage,
System can be shifted to the
Operates on batteries, reducing unnecessary power consumption depending on conditions
The operation time of the electronic device can be extended. The battery backup circuit shown in FIGS.
And switch the power supply on the chip
FIG. 11A shows a configuration example of the LSI thus configured. This figure
1C has an information storage function like the LSI chip of FIG.
Or LSI chip with information processing function, 40 is power switch
Circuit, power supply drop detection circuit 41, S_L, S_BIs power drop detection
Switching signal generated by the circuit, SW_40a, SW_40bIs the switching signal
S_L, S_BSwitch to switch the power supply, and PAD4
Each bonding pad for applying the pond voltage
Is shown. In this way, the power supply can be switched on the chip
Battery backup to the system (board)
There is no need to mount a top-down circuit, reducing the number of parts.
And the manufacturing cost and packaging density can be improved. In addition, LSI
Since a power supply switching circuit according to the characteristics can be mounted,
The power supply voltage transient
Providing an easy-to-use chip without having to worry
Can be. FIG. 11 (b) shows a specific example of the power supply switching circuit 40.
2 shows a typical configuration example. In the figure, 42 and 43 are differential
Width circuit, 44, 45 is its output, T₁₉, T₂₀Is the power switch
A P-channel MOS-FET 46 corresponding to a switch for performing
This is the output of the source switching circuit. The operation of this circuit is described below.
explain. The non-inverting input and inverting input of the differential amplifier circuit 42
Each V_CCAnd V_BTVoltage γV proportional to_CCAnd γV_BTApply
You. Similarly, the non-inverting input and the inverting input of the differential amplifier circuit 4 are
Is V_BTAnd V_CCVoltage γV proportional to_BTAnd γV_CCApply
I do. Here, γ is a proportionality constant satisfying 0 ≦ γ ≦ 1.
Has sufficient voltage gain and output amplitude of the differential amplifier circuit
It is desirable to set such a value. The proportional voltage is the resistance
It can be obtained by dividing. Output of differential amplifier circuits 42 and 43
44 and 45 are T₁₉, T₂₀Is applied to the gates. Introduction V_CC
> V_BTConsider the case At this time, a high voltage (V
_CC), But a low voltage (~ γV_CC−V_r) Is output
And T₁₉Is non-conducting, T₂₀Becomes conductive. Consequently V_INT
As V_CCIs output. Similarly V_CC<V_BTIf, output 4
4 has a low voltage (~ γV_BT−V_T) But high voltage at output 45
(V_BT) Is output respectively, and T₁₉Is continuity, T₂₀Is non-conducting
State. As a result, V_INTAs V_BTIs output.
This circuit is V_CCOr V_BTOperates in the same way when one of the
Therefore, even when only one power supply is supplied,
The supplied voltage is output as it is as the power supply voltage for the internal circuit.
Is forced. FIG. 11 (c) shows V_INTV_CCV is an example of dependency_BT
= 1.5V. V_CC> 1.5V
Is V_INT= V_CC, V_CC<1.5V for V_INT= 1.5V
ing. As shown in the figure, V_INTChanges continuously
And kinks that adversely affect LSI operation occur.
I haven't. As shown in the above embodiment, it is relatively simple.
Since the power supply switching circuit can be configured with a simple circuit,
Even if mounted on one LSI, the increase in chip area is small
is there. Here, an example configured using a MOS-FET is shown.
However, even if other, for example, bipolar transistors are used,
It can be realized similarly. In the above embodiment, the main LSI circuit block is 1.5 V or less.
The basic concept of an LSI chip operating below has been described. Less than
Below, we mainly focus on dynamic memory, and more
Examples will be described. Generally, other logic LSIs and status
Dynamic memory operates at a lower voltage than memory
Has been difficult. The first reason is that storage voltage and
The amount of signal charge that can accumulate storage capacitance is reduced by lowering the voltage
However, this is because the signal-to-noise ratio decreases. for that reason,
Trace amounts of radioactive materials contained in packages, metal wiring, etc.
Noise generated by irradiation of alpha rays emitted from
Thermal and non-thermal leakage currents flowing into the load and memory cells
Noise margin for noise charge due to
It has been considered difficult. These problems are the following two
This can be solved by any of the methods. (1) Even at low power supply voltage (for example, 1.5V),
Memory cell storage signal voltage of the same level (for example, low voltage = 0
V, high voltage = 3V). this
In this case, the storage capacity of the memory cell is the same value as before (for example,
For example, 30-40 fF (femto farad) is good. (2) Instead of using the conventional circuit method, the memory cell
Is increased almost in inverse proportion to the power supply voltage. An example
For example, when the power supply voltage = 1.5V, the storage capacity of the memory cell is
60 to 80 fF. Of the above methods, for (1),
In addition to the word and data lines, drive the plate of the memory cell.
The signal amplitude larger than the amplitude of the data line
Japanese Patent Application No. 63-148104 and Japanese Patent Application No. 63-148104
No. 63-222317. Regarding (2),
Japanese Patent Application Shows Technology to Improve Dramatically Increased Capacity
60-267113 and Symposium on VSI
Technology, digest of technical pages
Topaz, pages 29-30 (1988) (1988 Symposium on VL)
SI Technology, Digest of Technical Papers, pp, 29-3
0,1988). Applying these technologies
And secure the accumulated signal charge necessary for stable operation.
Can be The second challenge for low voltage operation is high speed
It is to realize operation and low current consumption at the same time. Third
The challenge is that the low-voltage operation circuit and the high-voltage operation circuit are on the same chip
The realization of the element or the circuit which enables the accumulation in the memory.
The third problem is that the ratio of the voltage values of the high-voltage power supply and the low-voltage power supply
If it is more than twice, it becomes a particular problem. One chip
Forming two types of elements for high voltage and low voltage on top
Japanese Patent Application No. 56-57143 shows an example of solving the third problem
Have been. According to this technology, low voltage power supply and high voltage
The circuit can be configured with the optimal elements for each of the power supplies
However, there is a disadvantage in that the structure of the LSI is complicated.
The following embodiment overcomes the second problem and minimizes the power supply.
Means of operating at 1V pressure, and complicates the manufacturing process
A method for solving the third problem without any problem will be described.
Thus, the operating power supply voltage of the dynamic memory is
Voltage can be reduced to about 1.5V, with dynamic memory
LSI chips that include dynamic memory as part of
High integration, high speed, and low power consumption can be realized at the same time.
Also, battery operation or battery backup operation
Can meet the required specifications. First, means for overcoming the second problem will be described.
You. The following is a complementary MOS-FET (Complementary
MOS = CMOS), but the same effect can be obtained.
If so, bipolar transistors, junction FETs, or
Elements other than silicon may be used. Fig. 12 (a)
Is the gate-source voltage V of the N-channel MOS-FET_GSWhen
Drain current I_DShows the relationship. This relationship is
(I) I_DIs the square root of V_GSAnd the square root region that is approximately proportional to
(Ii) from V_GSI in a small area of_DIs V_GSProportional to the exponential of
Sub-threshold area. V in the figure_T1
Neglects the area of (ii) and approximates the current-voltage characteristics by the square root.
When it is possible to resemble, the drain current starts to flow.
This is the so-called gate threshold voltage. Also, V_T0Is a circuit
Gate threshold that allows drain current to be considered almost zero
Another definition of voltage. If the gate width is 10 microns
Come, V_GS= V_T1The drain current is about 10nA, V_GS= V
_T1In this case, the drain current is about 1 μA. V_T1And V
_T0Is approximately 0.2V (V_T1> V_T0). Actual MOS
-The current drive capability of the FET is V_GS−V_T1Related, waiting state
V for static current at_T0Is concerned. In the following example, LSI
The threshold voltage of the element used in the main circuit of_T1= 0.3V
(Hence V_T0Is set to about 0.1 V). This
As a result, at a voltage half the power supply voltage (for example, 0.5 V),
-Sense amplifiers and differential amplifiers that need to conduct FETs
The circuit can be operated, and all
The circuit can be operated. This also allows
The standby current of the entire chip can be suppressed to about 10μA.
You. Also, the threshold voltage may vary due to variations in various manufacturing processes.
Circuit operation at power supply voltage = 1 V even if the voltage fluctuates about ± 0.1 V
Operation, and the standby current of the entire chip is reduced to 100μ.
A or less. In addition, even if the power supply voltage = 1 V
Channel length = 0.3 micro
Ron. FIG. 12 (b) shows two N-channel MOS-Fs.
Gate threshold voltage V for ET (CaseI, CaseII)_T1of
This shows channel length dependence. Here, CaseI
Dynamic memory (hereinafter abbreviated as DRAM)
Conditions for applying substrate bias voltage, Case II
Corresponds to the conditions used in the light, with no substrate bias voltage applied
This shows the characteristics of the device. V in CaseI_BS= -1V and
In case II, V_BSGate threshold voltage V when = 0V
_T1Is set to 0.3V. The following are the elements for Case II
There are three problems. (1) Change in gate threshold voltage with respect to channel length variation
Short fluctuation due to large fluctuation and poor controllability compared to Case I
It is difficult to make a tunnel. (2) The substrate bias voltage is applied to the substrate bias provided on the chip.
It is created by the bias voltage generation circuit.
Variation due to fabrication variations and the number of operating circuits
Therefore, the value greatly fluctuates with time. Gate threshold
Value voltage is greatly modulated by the substrate bias voltage.
Gate threshold voltage required for low-voltage operation
Cannot be satisfied with high accuracy. (3) When the power is turned on, the substrate bias voltage is 0V.
Gate threshold voltage is lower than 0.3V due to substrate effect
Value, for example, 0V, and at the same time,
V_CCSubstrate by capacitive coupling with
Voltage rises transiently, gate threshold voltage is negative
Becomes As a result, the MOS-FET of the peripheral circuit becomes conductive
Therefore, a large transient current flows. In the present invention, the substrate voltage is set to V_SS= 0V fixed
Excellent controllability of gate threshold voltage and power on
LSI chips with small transient current can be provided
You. Furthermore, fluctuations in substrate voltage during circuit operation
Since it can be set to zero, capacitive coupling noise from the substrate voltage
Sound can be greatly reduced. Note that the threshold voltage
If other means to set the pressure accurately are used,
May be applied to the substrate bias voltage. Fig. 13 shows a dynamic operating even with a minimum supply voltage of 1V.
Gate oxide film pressure of the device used for the main circuit of the memory to
x, electrical channel length (effective channel length) L_eff, Game
Threshold voltage V_T1, V_T0Is shown. Where in parentheses
Indicates the range of variation due to manufacturing variations.
doing. FIG. 14 is a sectional view of the dynamic memory chip of the present invention.
Shows part of the structure. With conventional dynamic memory
The reason for applying the negative voltage to the substrate is as follows.
One. (1) External ringing to input or output
When a negative voltage is applied,
Electrons are injected into the substrate. These electrons diffuse through the substrate
Part of the charge reaches the charge storage area of the memory cell,
Worsen the brush characteristics. This minority carrier to the substrate
Prevent infusion. (2) By applying a negative voltage to the substrate, n
Reduce the junction capacitance between the diffusion layer and the p-substrate and reduce the load capacitance
Reduce. This allows high-speed operation and low power consumption of the circuit
Plan. (3) By applying a negative voltage to the substrate,
The depletion layer under the channel expands, and the potential of the channel
Are less susceptible to modulation by the substrate voltage. This allows
Gate threshold voltage is not affected by substrate voltage fluctuation
It becomes. In other words, the gate threshold voltage base
The plate effect count becomes smaller and some of the dynamic memory
It is convenient for the operation of the circuit. Of these, (3)
With the tendency of CMOS-LSI to have a double well structure,
The effect of applying the substrate voltage to the
You. Therefore, solving (1) and (2) is important.
It becomes important. Application of multiple substrate voltages in CMOS-LSI
A substrate structure that enables the above is disclosed in JP-A-62-119958.
You. Combining this structure with the low-voltage LSI according to the present invention
As a result, the above-mentioned object is achieved,
A low-voltage LSI with high speed and low power consumption can be configured.
Hereinafter, examples of the present invention will be described with reference to the cross-sectional views of the substrate structure of the present invention.
Will be described. In FIG. 14, the P-type silicon substrate
Pure substance concentration is about 1 × 10^Fifteencm⁺³It is. Two times in this substrate
Two types of N wells (N1, N1,
N2), and one type of P well is formed. Of each well
The impurity concentration is, for example, 1 × 10¹⁶cm⁺³, N1
5 × 10¹⁶cm⁺³To the extent, the dimensions of the element
These values may be changed according to. In the figure, 50
Is a thick oxide film to provide electrical isolation between active regions
Thickness is about 500 nm), 51 is the first for forming volumetric capacity
Polysilicon electrode, 52 is the gate electrode of the MOS-FET
The second polysilicon electrodes 53 and 54 have these thick oxide films and
Self-aligned using polysilicon electrode as mask
N-type impurity diffusion layer (impurity concentration is about 2 × 10²⁰cm⁺³),
55, 56 and 57 are P-type impurity diffusions formed in the same manner.
Layer (impurity concentration is about 2 × 10²⁰cm⁺³)
You. The P substrate is connected to the diffusion layer 56 and ground potential (V_SS)
I have. Storage capacity of memory cell and selection transistor T_N3, T
_N4Is a P-well electrically separated from the substrate by an N2 well
Form inside. The second substrate is formed in the P well by the diffusion layer 57.
Potential V_BP2Is applied. The N2 well also has electrical
N1 well and the diffusion layer 54 make contact with the second N well potential
V_BN2Is applied. Also V_BS= 0V peripheral circuits
N-channel MOS-FET T_N1Is a P channel MOS in a P substrate
−FET T_P1Are formed respectively in the N1 well. Also,
N-channel MOS-FET T of peripheral circuit_N2Is a memory cell array
In a P-well that is electrically separated from the P-substrate.
Has formed. By doing this, the input / output circuit
Whether the eggplant voltage or the voltage higher than the N-well voltage is external
Overshoot, if possible
Alternatively, an independent board power supply according to the amount of undershoot
Pressure can be applied. Thus, the memory cell address
The P well where the laser is formed is electrically separated from the P substrate
This has the following other effects. (1) Set the P well of the memory cell array to a negative potential.
This reduces data line capacity and reduces signal interference.
Sound ratio can be improved. (2) The N2 well covering the memory cell array
It becomes a barrier for the scattered minority carriers. This
Noise can be suppressed from being collected in the storage capacitor,
Is improved. As described above, FIG.
By using such a substrate structure, the memory cell array
Simultaneous stable operation and high speed and low power consumption of peripheral circuits
Can be realized. In the above description, the P substrate
Has been described, but the same applies when an N substrate is used.
Effect can be expected. However, the present invention is targeted
Battery operation or battery backup operation
Should not be used in environments where the power supply voltage fluctuates greatly.
I have to. When an N substrate is used, the N substrate
Maximum voltage V_CCIs applied. Therefore, the power supply voltage
If it fluctuates sharply, the potential of the N substrate also fluctuates,
Noise is induced in each part of the circuit by capacitive coupling. These logics
For this reason, the purpose of the present invention is to use the P substrate shown in FIG.
Suitable structure. FIG. 15 shows that the voltage can be further reduced by the present invention.
Shows an example of an LSI circuit with a possible information holding function.
You. FIG. 15A shows an example of a peripheral circuit. 60 in the figure
Source voltage V_CL1Circuit block that operates on 61, power supply voltage V_CL2
Circuit block operating on V_BP2Is the N chip of the circuit block 61
Channel bias voltage of channel MOS-FET, V_BN1Is a circuit block
The substrate bias voltage of the P-channel MOS-FET
Is shown. The circuit block 60 operates when information is held.
V when the information is held_CL1= 0V. Times
Road block 61 must be operated even when information is held
V in minutes_CL2Is constant regardless of the operating state. Power-supply voltage
= 0.5V to operate the circuit, the threshold voltage
Pressure V_T1Needs to be set to about 0 to 0.1V. At this time,
Even when the circuit does not operate and the gate-source voltage is 0V
A current of about 1μA flows through the MOS-FET, and the entire chip
It becomes a large current value of 10 mA. Current consumption when retaining information
To reduce this static current
is necessary. Generally, when information is retained, compared to standard operation
The operation speed may be slow. Therefore, in this example, the substrate voltage
Control the MOS-FET threshold when information is held.
Value voltage is less likely to conduct compared to standard operation (N channel
The threshold voltage of the channel MOS-FET is high, and the P-channel MOS-F
(The threshold voltage of the ET is low). Fig. 15
(B) is the substrate voltage V of the N-channel MOS-FET_BP1Generation circuit
FIG. 15 (c) is an operation timing diagram thereof.
You. Here, for convenience, V_CL2= 1.5V
As mentioned earlier, as mentioned earlier, a low power supply
It is particularly effective when pressure is applied. In FIG. 15 (b), 62
Is inverter I_Two~ I_ThreeAnd NAND gate G_ThreeReconfigured by
Oscillator 63, two MOS-FETs diode-connected
 T₄₀, T₄₁And capacity C_B1Charge pump times composed by
Road T₄₂, T₄₃Is an N-channel MOS-FET T₄₄Is a P-channel MOS
-FET is shown respectively. During standard operation, that is, PD
Is low voltage (“0”), the ring oscillator and charge
The pump circuit does not operate. At the same time, MOS-FET T₄₄Is conductive
And node N₁Is high voltage (“1”), so MOS-FET T₄₂
Becomes conductive and V_BP1Is at ground potential. On the other hand, when information is retained,
That is, when PD is at a high voltage (“1”), the MOS-FET T₄₃
Conducts and the node N₁Is V_BP1Because it has the same potential as
−FET T₄₂Cuts off. At the same time, with the ring oscillator
The charge pump circuit operates and V_BP1Has a negative voltage
Is output. Note that the memory cell array is always
The bias voltage is applied. As mentioned above, as mentioned above,
When operating with the lower low-voltage power supply, the substrate bias voltage is controlled.
Control to maintain high-speed information during standard operation.
Sometimes low power consumption can be achieved. In addition, here
Although the description is omitted, the present invention_BN1Circuit that generates
The same can be applied to In the following description, the low voltage using the substrate structure described earlier
A specific circuit configuration of the dynamic memory will be described.
You. FIG. 16 (a) shows a circuit configuration of a dynamic memory.
doing. In the figure, NA1 and NA2 are memory cell arrays, and DA1 is
Dummy cell array, W₀~ W_mIs the word line, D₀, D₀￣, D_n,
D_n￣ is the data line, DW₀, DW₁Is dummy word line, XD is word
Line selection circuit, DWD is a dummy word line selection circuit, T₅₂~ T
₅₅Is the left mat that controls the connection between the left mat MA1 and the sense amplifier.
The reset selection transistor, SHRL, has its selection signal, T₅₆~ T₅₉
Is the right mat that controls the connection between the right mat MA2 and the sense amplifier.
Select transistor, SHRR is its select signal, PR₀~ PR_nIs
A precharger that sets the data line voltage to potential P when not selected
Circuit, φ_{P ~}Is the precharge signal, SA₀~ SA_nIs data
Sense amplifier, CSN and CSP to amplify small signal voltage on line
Is the common source drive signal of the sense amplifier, and CD is the common source
Source drive circuit, YG₀~ YG_nIs the connection between the data line and the common I / O
Gate, YDEC, Y address selection circuit, YDEC₀~ Y_nIs
Y select signal and DiB drive common I / O line according to input data.
Data input buffer, DoB is the signal power of the common I / O line.
It is a data output buffer that amplifies and outputs a stream. Note
Recell storage capacity C_S2Is between 60 and 80f
The value of the data line capacitance is about 250 to 300 fF. This
As a result, the read signal when the data line amplitude is 1.5 V
Signal voltage is about 150mV, which is sufficient for the operation of the sense amplifier.
Signal voltage can be obtained. FIG. 16 (b) shows the power supply.
Voltage waveform of each part when reading data at 1.5V
Is shown. Note that in the following description, the
In the case of a read operation and the word line W₀If is selected
think of. Data line precharge voltage, cell storage capacity
Voltage of the opposite electrode (plate) is 0.75 which is half of the power supply voltage
V Thereby, (1) at the time of charging / discharging the data line
And capacitive coupling noise generated during precharge
And (2) the voltage applied to the insulating film forming the storage capacitor
Storage voltage by minimizing the voltage
The amount has been increased. High voltage (1.5V) for memory cells
To write the word line W₀And left mat select signal
2.2V is applied to SHRL and transistor T₅₀And T₅₂But
It operates in the unsaturated region. MOS of Y gate
− The common I / O line is set to 1.2 V to operate the FET in the saturation region.
I am trying to become. Operates at such low power supply voltage
Japanese Patent Application No. 63-141 as an amplifier for common I / O line signals
Suitable for current detection type as described in 703
I have. If this type of amplifier is used, (1) common I / O line
Voltage level near the power supply voltage.
And (2) reduce the signal amplitude of the common I / O line (for example,
50mV), the Y selection signal Y₀To read the signal.
It is possible to increase the operation margin at the time of delivery. Ma
In addition, when writing to the memory, the I / O lines are
Input buffer D₁This can be done by driving with B. Emotion
There is no need to read information externally when information is held
Therefore, the Y selection signal Y₀Is low voltage
(“0”). In addition, a Y address selection circuit,
Data input buffer, data output buffer, etc.
Need not be. In addition, the common source drive of the sense amplifier
The drive capability of the power circuit is reduced and the data line voltage changes over time.
The rate is decreasing. As a result, when information is retained
Reduces the value of the peak current accompanying the charging and discharging of the data line.
By performing such control, the internal
Even if a power supply with high impedance is used,
LSI can be prevented from malfunctioning due to transient drop.
You. The following describes such a low-voltage dynamic memory.
The following circuits important for realization are described. (1) 1/2 V_CLGenerator circuit. (2) Word line drive circuit. (3) Common source drive circuit. Fig. 17 (a) is 1 / 2V_CLThe circuit configuration of the generator is shown.
You. In the figure, T₆₀, T₆₂Is an N-channel MOS-FET, T₆₁, T₆₃Is
P-channel MOS-FET, R₂₀, R_{twenty one}Sets the bias current
Resistance for The resistance value of the resistor_Fourand
The power supply voltage of node P is V_CL2To be almost half of
Huh. Capacity C_D1~ C_D4Follows power supply voltage fluctuations
Speed-up capacitor
You. Between these values C_D1≒ C_D2, C_D3≒ C_D4Holds
ing. Connect the substrate and source of each transistor, substrate
Prevent the threshold voltage from increasing due to the bias effect
doing. At this time, the threshold voltage V of each transistor
_T1Is about 0.3V. If the board is not the source
When connected to the maximum voltage of the system,
Threshold voltage V_T1Since the absolute value of
Power supply voltage V_CL2It does not operate at 1V. Thus, low
In a circuit that operates with voltage, the method of applying the substrate voltage is the minimum power supply.
Specify the pressure. Using the substrate structure shown in FIG.
And the source can be easily connected. FIG. 17 (b) shows N channel
Flannel MOS-FET T₆₀, T₆₂2 shows the cross-sectional structure of the device. 65 is N
N ~ diffusion layer to give 2 well potentials, 66 is P well
P-diffusion layer for applying a potential of
These are nn diffusion layers serving as the source and drain of the S-FET.
P-diffusion layer 66 for applying MOS-FET substrate voltage by external wiring
Is connected to the source. N2 well has the highest voltage of the system,
Where V_CL2Is applied. As shown in this example, MO
Form S-FET in P-well electrically isolated from substrate
The effect of the substrate effect on the threshold voltage.
I do not receive. A circuit suitable for low-voltage operation can be configured.
Wear. It should be noted that the present invention is not limited to the example shown here,
To operate the other source at a higher voltage than the ground potential
The present embodiment can be applied to a line as a road. FIG. 18 (a) is a circuit configuration of a word line driving circuit, and FIG.
(B) shows the operation timing. In the figure, T
₈₂Is the memory cell transistor, C_S3Is the storage capacity, T₈₀, T
₈₁Is an N-channel MOS-FET. This circuit is generally self
It is called a boost (self-boost) circuit. S for word
A selection signal of the line selection circuit is input. This voltage level is
High voltage (eg 1.5V) when selected, low voltage when not selected
(0V). Therefore, node N₇At the time of selection
V_CL−V_T0(V_T0Is T₈₂Threshold voltage) when not selected
0V is applied. After the selection signal is determined, X
Make sure that the power supply voltage is
A higher pulse voltage (for example, 2.2 V) is applied. Unselected
Sometimes MOS-FET T₈₀Does not conduct, but when selected, T₈₀of
Node N₇Boosts to high voltage
(Boost). A pulse applied to X is applied to the word line.
To output the source voltage as it is, the node N₇The voltage of
A higher voltage than the pulse voltage applied to X, eg
For example, 2.2 + V_T1(V_T1Is T₈₀(Boost threshold voltage)
Strike). Ground potential of MOS-FET substrate
The threshold voltage increases due to the substrate effect.
Especially V_CLIs less than 1.5V,
It is difficult to obtain a constant amplitude. Here, the MOS-FET
To reduce the threshold voltage to a sufficiently low value, signal the substrate potential
Drain of the drive side (in this example, selection signal S and pulse voltage X)
(Where the drain is signal driven for convenience)
Is defined as a terminal to which is applied). Sectional structure of this MOS-FET
The drawing and its equivalent circuit are shown in Fig. 18 (c) and
(D). The cross-sectional structure of the device is shown in FIG.
It is exactly the same as the one, but the connection is different. P
Since the well potential matches the drain potential,
As shown on the left of FIG.
Bipolar transformer with base as source and emitter as source
This is equivalent to the connection of the resistor. In fact, this
The bipolar transistor is connected to the
The star operates as a diode and is shown on the right side of FIG.
It is represented by such an equivalent circuit. Therefore, the drain
When the source voltage is higher than the source voltage, the substrate voltage
MOS-FET and diode D positively biased_LAnd
Connected in parallel, conversely the drain is lower than the source voltage
Diode D_LIs reverse biased and cut off
The MOS-F with the substrate voltage connected to the drain on the low voltage side
Only ET works. Therefore, compared to the latter case,
In the former case, the threshold voltage is lower and the MOS-FET
Is easily conducted. At the same time, the drain and source voltages
When the difference is 0.7V or more, the diode conducts.
In the case of a person, the current flows more easily. Therefore,
In FIG. 18 (b), the MOS-F
ET T₈₀, T₈₁Can lower the threshold voltage of
The drive signal X to the word line even at a low power supply voltage.
It can be output as it is. Such asymmetric characteristics
Is particularly effective when applied to self-boosting circuits, etc.
But other, such as pass gate or substrate bias voltage
For rectifying circuits used in charge pump circuits of generator circuits, etc.
If applied, operation with a low-voltage power supply is likewise improved. FIGS. 19 (a) and (b) show common source
FIG. 3 is a diagram illustrating an example of a configuration of a drive circuit. FIG.
In, T₈₅, T₈₆Is the N channel that drives the common source
MOS-FET, G_FiveIs an AND gate. During normal operation,
Signal PD ~ becomes high voltage (“1”) and the common source drive signal
In synchronization with the input of φcs, T₈₅, T₈₆Are conducted together. one
On the other hand, when information is held, PD ~ becomes low voltage ("0"), and φcs
T for input₈₅Only conducts. Therefore, T₈₅When
T₈₆By selecting the conductance of
During quasi-operation, the operation speed is prioritized.
Instead of sacrificing power,
Wear. In FIG. 19 (b), T₉₀Drives common source
Operating N-channel MOS-FET, T₉₁, T₉₃, T₉₄Is N channel
MOS-FET T₉₂Is a P-channel MOS-FET, G₆Is a NAND game
C, G₇Is AND gate, R_{twenty five}Is T₉₄Supply bias current to
Resistances are shown. During normal operation,
Signal PD becomes low voltage ("0") and T₉₃Cuts off. φc
Synchronize with the input of s, the node N₈Voltage is V_CLBecome T₉₀To
Drive. When information is held, the signal PD becomes high voltage (“1”).
R₉₂Cuts off. T in synchronization with φcs input₉₃Is led
Through, node N₈Voltage is T₉₄Gate voltage.
At this time, T₉₀And T₉₄Form a current mirror circuit with
Therefore, the drive current of the common source is (V_CL−V_T1) / R_{twenty five}To
It becomes a proportional value. Where the proportionality factor is T₉₀And T₉₄Channel
It is determined by the ratio of conductance. Such a drive circuit
By using, when information is held, a certain controlled
Because it is driven by current, it will
Without causing a transient drop in power supply voltage.
Operation can be realized. The current shown here
Drive current can be controlled in addition to the mirror circuit when information is retained
For example, other means may be used. The substrate structure, element constants, and the like as described in the above embodiments,
Operation with the minimum power supply voltage = 1 V is guaranteed by the circuit configuration
Dynamic memory can be realized. Also,
Circuit configuration of I / O line and Y gate shown in FIG. 16 (a)
In addition, the common I / O
Provision of the O line enables read and write operations
Japanese Patent Laid-Open No. 61-142594 and
It is described in JP-A-61-170992. Apply this method
Therefore, even at a low power supply voltage of about 1 V,
Memory circuit that operates stably without being affected by
be able to. Above, the main operating at low internal power supply voltage of 1.5V or less
An example of the configuration of an LSI circuit block is explained using a memory as an example.
Have been. To realize an LSI chip as shown in Fig. 1
Other than this, high external power supply voltage (for example, 3-5V)
It is indispensable to realize a circuit that operates on the. In such a circuit
Has at least the following: (1) Reference voltage generation circuit (2) Voltage conversion (drop) circuit (3) Input circuit (4) Output circuit As shown in Fig. 13, low internal power supply voltage of 1.5V or less
The main LSI circuit block that operates on
For the purpose of maintaining, the latest processing technology (for example, gate length 0.
(Equivalent to 3 microns or less). Like this
For small devices, gate breakdown voltage and drain breakdown voltage are reduced.
And difficult to operate at high external power supply voltage (for example, 3-5V)
become. In this regard, for example, IEE
M Technical Digest, pp. 386-389
(1988), (IEDM Technical Digest, pp.386-389,198
It is described in 8). Consider long-term reliability
Then, the voltage that can be applied to the 10 nm gate oxide film is about 4V.
You. Therefore, the maximum electric field strength that can be applied to the gate oxide film
Degree E_maxIs about 4 MV / cm. Approximately E_maxThe value of
It does not depend on the gate oxide film thickness, and is considered to be almost unchanged.
(Actually, if the gate oxide film is thinned,
Tend to be). This value is used for the device shown in FIG.
Can be applied to the gate when it is applied to
The maximum operable voltage is 2.7V. Therefore, this device is
It is not possible to operate with external power supply voltage (for example, 3-5V)
I can't. There are two ways to solve this.
It is. (1) As mentioned in the previous explanation, use at the internal power supply voltage.
Thicker gate operating at external supply voltage
Elements having a gate oxide film are integrated on the same chip. (2) Consist of only elements used at internal power supply voltage
You. At this time, the external power supply voltage is directly applied to the element (1).
Make circuit ingenuity so that it does not occur. The method (1) is described in Japanese Patent Application No. 56-57143. I
However, this method complicates the LSI manufacturing process,
Manufacturing costs rise. In addition, the most important gate
Since many steps are inserted when forming the gate oxide film,
The probability of introducing an object or defect is high, and the reliability of the device is low.
There is a problem of lowering. The following is the method (2)
Example of realizing a circuit that operates with a higher external power supply voltage
State. In the following example, complementary MOS-FET (CMOS)
The following describes an example using
Even if a polar transistor or a junction transistor is used,
Alternatively, when these are used in combination with a MOS-FET,
Semiconductor materials such as gallium arsenide other than silicon
The same applies to the case of using. FIG. 20 (a) is a configuration example of an inverter circuit according to the present invention.
Is shown. In the figure, T₁₀₀, T₁₀₂Is an N-channel MOS-FE
T, T₁₀₁, T₁₀₃Is P-channel MOS-FET, in1, in2 are
The first and second in-phase input terminals, out1 and out2, respectively
First and second in-phase output terminals, Out is a third output terminal,
V_n, V_pAre N-channel and P-channel MOS-FETs respectively
Is shown. V_nAnd V_pIs an example
For example, there is an external power supply voltage dependency as shown in FIG.
I do. In this example, V_CCV when ≥2V_n= 2V, V_p= V_CC−
It becomes 2V. As a result, the voltage of the output terminal out1 is at most V_n
−V_TNThe transistor T₁₀₀Of gate oxide film
Maximum applied voltage is V_n−V_TNIs limited to Similarly,
Transistor T₁₀₁Voltage applied to the gate oxide film
Is V_CC−V_p− | V_TP| Where V_TNIs
T₁₀₂, V_TPIs T₁₀₃Is the gate threshold voltage. Two
The signal levels of the output terminals out1 and out2 are each 0 to V_n−V
_TN, V_CC−V_p− | V_TP｜ ~ V_CCThese are the next in
The inputs of the barter, in1 and in2, vibrate respectively. Also, the third
0 to V for output Out_CCThat is, output full amplitude.
Can be. This inverter forms an inverter train
Voltage of each node and gain of each transistor
The maximum voltage applied to the gate oxide film is shown in FIG.
It becomes like. With this circuit configuration, for example, V_n= V_p= 1 /
2V_CCThe gate of any transistor
The maximum voltage applied to the oxide film is 1 / 2V_CCAt the same time
Maximum voltage applied between rain and source is 1 / 2V_CC+
V_TNOr 1 / 2V_CC+ ｜ V_TP| actually
From the viewpoint of securing the operating margin of the inverter.
V where the source voltage is low_nAnd V_CC−V_pIs constant
Is preferred. Output voltage transients during switching
Large voltage between drain and source
So that it is not applied, T₁₀₂And T₁₀₃Channel conductor
Are T₁₀₀And T₁₀₁Channel Conductor
It is desirable to make it larger than As explained above
In addition, with this configuration, the power supply voltage is about twice the maximum voltage of the element.
Circuit that operates without deteriorating device characteristics up to
Can be In the example shown in FIG. 20 (a),
The substrate potential of the N-channel MOS-FET is the minimum voltage of the system, that is,
Chi V_SSIn addition, the substrate potential of the P-channel MOS-FET is
Pressure, ie V_CCConnected to the
To connect the substrate of each transistor using the structure to the source,
The fluctuation of the threshold voltage due to the substrate effect can be suppressed.
Realizing a circuit that operates with lower power supply voltage
Can be. Therefore, if the present invention is applied, about 6.5 nm
Power supply voltage = 5V only with MOS-FET using thin oxide film
However, it is possible to provide an LSI that operates stably. FIG. 21 (a) shows that the connection between the substrate and the source is low.
Connect multiple inverters with improved operating characteristics at power supply voltage
Configuration example of connected inverter train (inverter chain)
It is. As with conventional CMOS inverter arrays,
Without any level conversion circuit.
And it is possible. This allows, for example, output buffers
Driver circuits that require a large load drive capability, such as
Can be configured. Let n be an even number
And its input and output waveforms are as shown in FIG.
become. In this example, V_CC= 4V, V_n= 2V, V_p= 2V
You. In this circuit, the output signal that drives the next-stage inverter is
The signal amplitude is almost constant (1.7V) regardless of the power supply voltage.
You. For this reason, each gate of the next stage inverter is charged and discharged.
MOS-FET drive capability no longer depends on the power supply voltage,
Delay time from input to output (t₁−t₀) But the power supply voltage
It is almost constant regardless. Therefore, for example, a memory LSI
Access time is as wide as 1.5 to 5V
Since it hardly changes, it is a good
A convenient LSI chip can be provided. FIGS. 22 (a) and (b) show vias shown in FIG. 20 (b).
Voltage V_n, V_p5 is a configuration example of the generation circuit of FIG. In the figure, channel
T with bold line₁₁₄~ T₁₁₇Has high threshold voltage
N-channel MOS-FET, T₁₁₂, T₁₁₃Supplies the bias current.
MOS-FET to supply, 72 is T₁₁₂, T₁₁₃Generates the gate voltage of
Bias generation times to set optimal bias current
Road, C_N1, C_P1Is the decouple capacity. Bias current
Value is resistance R₃₀And T₁₁₃And T₁₁₂Channel Conductor
Set according to the ratio of N with high threshold voltage
After forming the gate oxide film, the channel MOS-FET
P-type impurity is introduced by ion implantation using the mask as a mask
It is formed by such means as performing. In this example, the threshold
The value of the pressure is 1V. Also, use the substrate structure shown above.
And by connecting the board to the source,
Eliminate voltage fluctuations due to substrate effects and increase setting accuracy
I have. Also, MOS-FET T₁₁₂, T₁₁₃Operates as current reduction
I do. With this configuration, the power supply voltage V_CCIs more than 2V
Is V_nIs approximately twice the value of the high threshold voltage (approximately 2
V) and V_CCIs less than 2V, the power supply voltage V_CCAlmost
Become equal. Similarly, the power supply voltage V_CCIs more than 2V
Is V_pIs approximately V_CC−2V, V_CCIs less than 2V
It becomes almost 0V at the time. FIG. 22 (b) shows the generation of bias voltage
13 is another configuration example of the circuit. Here, V_nOnly the generation circuit
Shows that V_pThe generation circuit can be similarly configured. In the figure,
T_{one two Three}Is an N-channel MOS-FET having a high threshold voltage,
T₁₂₁Is a P-channel MOS-FET that supplies bias current, T
₁₂₀And R₃₁Is T₁₂₁Gate voltage to generate the optimal bias voltage.
Bias generator for setting current, C_N1Is decup
Capacity, R₃₂, R₃₃Is resistance. T_{one two Three}Of the threshold voltage
Value V_TEThen V_nIs V_TE× (R₃₂+ R₃₃) / R₃₃When
Become. Therefore, R₃₂And R₃₃By changing the ratio of_nThe value of the
V_TEAny of the above values can be set. these
Generates a bias voltage having the characteristics shown in FIG. 20 (b).
Can live. The resistance shown in this example is MO
Distribution of S-FET channel, impurity diffusion layer, polysilicon, etc.
Any of a wire layer and the like may be used. By the way, in a normal LSI, after the final manufacturing process, the normal operation
Deliberately increase the voltage in each circuit in the circuit
Apply to the transistor and remove the gate oxide film
Early detection of transistors that are prone to failure
Jing tests are performed to ensure reliability. Fig. 23
(A) is a bias voltage suitable for this aging test.
V_n, V_pFIG. 7 is a diagram showing an example of how to give the symbols. In this example
Is V_nAnd V_pHigher power than where the magnitude relationship reverses
At the voltage (4V in this example), V_n= V_p= 1/2 V_CCToshii
You. In this way, during the aging test,
V in proportion to source voltage_nAnd V_pIs trying to increase. Ma
Also, by halving the value or the power supply voltage, for example,
The maximum voltage between the transistors shown in FIG.
Equalize the stress on some transistors
To prevent them from concentrating on FIG. 23 (b) shows the bias voltage V_n, V_pThe circuit that generates
1 shows an embodiment of the configuration. In the figure, 72 is two nodes
N₉And N_TenThe maximum value that compares the voltage of
Output circuit, T₁₄₀, T₁₄₁Is the N threshold having a high threshold voltage.
Channel MOS-FET, R₃₆Supplies bias current to MOS-FET
Resistance, R₃₈And R₃₉Divides the power supply voltage by 1 / 2V_CC
To get R₃₈≒ R₃₉It is. Also maximum
The value output circuit is a differential amplifier circuit A_TenAnd A₁₁, P-channel MOS-F
ET T₁₄₂, T₁₄₃, Node N₁₁Impedance to ground side
Resistance R is provided to prevent₃₇And to
It consists of. The operation of the maximum value output circuit is, for example,
IEE Journal of Solids
・ State Circuits, Vol. 23, No. 5, 1128-11
32 (1988) (IEEE Jounal of Solid-State Circuit)
s, Vol.23, No.5, pp.1128-1132, October 1988).
Have been. Node N₉Is almost constant regardless of the power supply voltage.
Pressure (2V in this example) is input. On the other hand, node N_TenTo
Is a value that is half the power supply voltage. Therefore, the power
When the voltage is 4V or less, the maximum value of these two voltages is
Some 2V is node N₁₁Output when the power supply voltage is 4V or more.
1 / 2V_CCIs output. Bias voltage V_pTimes of occurrence
Roads can be similarly configured. In this example,
Code N₉2V was considered as the voltage value of
Set an appropriate value according to the maximum applicable voltage of the film.
Is also good. Japanese Patent Application No. 63-125742 describes the difference in threshold voltage of MOS-FET.
Is shown in FIG. Figure 24
That is higher than the voltage that can be applied to the gate oxide film.
The configuration of the constant voltage generation circuit that operates even at the unit power supply voltage
An example is shown. 75 in the figure is newly added for this purpose.
Inserted part, T₁₅₁Is an N-channel MOS-FET, T₁₅₂
Is a P-channel MOS-FET. As a result,
As with inverters, which transistor in the circuit
However, the maximum applied voltage is reduced to about half of the external power supply voltage.
Can be lowered. The value of the constant voltage generated by this circuit
Are two as described in Japanese Patent Application No. 63-125742.
N-channel MOS-FET T₁₄₉And T₁₅₀Threshold voltage difference V
_T1(T₁₄₉) -V_T1(T₁₅₀)become. T₁₄₉Is shown in Figure 22
As in the case of transistors with a high threshold voltage,
is there. In this example, V_T1(T₁₄₉) = 1.05V, V_T1(T₁₅₀)
= 0.3V and output voltage V_ref= 0.75V is obtained. FIG. 25 shows a configuration example of a differential amplifier circuit according to the present invention.
ing. In the figure, T₁₆₁And T₁₆₂Input differential signal
Two N-channel MOS-FETs, T₁₆₀Is a differential amplifier circuit.
N-channel MOS-FET, B for supplying bias current₁Is
A signal for setting the bias current, T₁₆₃And T₁₆₄Is
Two P-channel MOs constituting a current mirror type load
S-FET. In a normal differential amplifier circuit, the node N₁₃And N
_Fifteen, Node N₁₄And output out2 are connected.
Add the circuit blocks indicated by 5 and 77 to the gate oxide film.
Operates with an external power supply voltage higher than the applicable voltage
I have to. In FIG. 25 (a), 76 is divided into two N channels.
MOS-FET T₁₆₅And T₁₆₆, And P-channel MOS-FET T₁₆₇
It is composed of Thereby, the transistor T
₁₆₁And T₁₆₂Drain (N₁₃, N₁₄)
V at most_n−V_TN1The transistor T₁₆₄The drain (ou
The voltage applied to t2) must be at least V_p+ ｜ V_TP1|
You. Where V_TN1And V_TP1Are N channel and
And the threshold voltage of the P-channel MOS-FET.
Note that V_nAnd V_pAs in the previous embodiment, FIG.
(It has the power supply voltage dependency shown in (b) and FIG. 23 (a).
Bias voltage can be used as it is. Now,
The differential amplifier circuit shown in FIG.
Operating at a large difference between the two input levels
Without transistor T₁₆₁And T₁₆₂Operate in the saturation region
The voltage at node 14 is approximately V_n−V_TN1Tona
You. Therefore, as shown in FIG.
T₁₆₇Omit transistor T₁₆₄Gate and Dray
There is no large voltage difference between the terminals. As a small signal amplifier circuit
When only the circuit is used, the circuit of FIG.
The method is suitable. The output out2 of these differential amplifier circuits
The signal level is the output ou of the inverter shown in FIG.
It is equal to the signal level of t2.
Data input in2 can be directly driven.
It is convenient to construct a circuit. The above differential amplifier circuit
In the configuration example, the voltage levels of the inputs In (+) and In (-) are
V_n−V_TN1A large voltage gain can be obtained when
There are characteristics. Conversely, V_p+ ｜ V_TP1｜ Higher entry
When operating at the input voltage level, configure the differential amplifier circuit.
N-channel MOS-FET to be formed into P-channel, P-channel
MOS-FETs are replaced with N-channels, respectively,
Voltage level (output ou of the inverter shown in FIG. 20 (a))
A configuration that obtains the output of (t1 signal level)
No. At this time, the same effect as in the case of the configuration is obtained.
It is. Next, this differential amplifier circuit is applied to the LSI chip circuit.
The following is an example. Fig. 26 shows the internal power supply voltage V_CLV that is the reference for_L(Reference
1 shows an example in which the present invention is applied to a pressure) generating circuit. 26th
In FIG. 8A, 80 is V corresponding to 9 in FIG._L(Standard
Voltage) generation circuit, A_FifteenIs the differential amplifier circuit, R₅₀, R₅₁Is
This is a resistor for setting the amplification factor. Also, V_LOccurrence times
The path is the constant voltage (V_ref) Generating circuit
81, during aging test
Aging voltage (V_A) Generated
Circuit 82, V_refAnd V_AAnd output the higher voltage
It comprises a maximum value output circuit 83 and a switch 84. information
When holding, voltage characteristics of aging test are required
The maximum value output circuit is disabled.
Then, close the switch and V_refIs output directly. Now,
In this example, V_ref= 0.75V, V_A= 1 / 5V_CCAnd the power supply voltage
Will be in the aging test state when is more than 3.75V
I'm trying. That is, when the power supply voltage is 3.75 V or less
Has V_L= 0.75V, V when 3.75V or more_L= 1 / 5V_CCIs output
Is done. Also, R₅₀= R₅₁Stop the amplification factor at 2
V when the source voltage is 3.75V or less_CL= 1.5V, 3.75V or more
V_L= 2 / 5V_CCIs applied to the circuit as the internal power supply voltage.
I am trying to. External power supply voltage V for each voltage_CCDependencies
This is shown in FIG. 26 (b). This allows the power supply voltage of the internal circuit to be
Then, in the standard operation state (for example, the power supply voltage is 3-3.6V)
1.5V, aging test state (for example, power supply voltage is 5.3V)
Will get 2.1V. FIG. 26 (c) shows V_L(Reference voltage)
3 shows a more detailed configuration example of a raw circuit. Smell
90 is the maximum value output circuit, T₁₇₃Works as a switch
This is an N-channel MOS-FET. The maximum value output circuit is the difference between the two
Dynamic amplification circuits 90a and 90b, output of each differential amplifier
P-channel MOS-FET T driven by₁₇₇, T₁₇₈, T
₁₇₇And T₁₇₈The voltage applied to the gate oxide film
P-channel MOS-FET T for₁₇₇, Output end N_{twenty two}To ground
N-channel MOS-FET T to lower impedance
₁₇₅It is composed of Here, two differential amplifiers 90a and 90a
And 90b are the same as those shown in FIG. 25 (a). Ma
The configuration of the maximum value output circuit is the same as that shown in FIG.
Basically the same. With this configuration, the gate oxide film
Operating at a power supply voltage higher than the maximum
A large value output circuit can be obtained. In addition, information holding state
Then transistor T₁₇₉And V_refAs is V_Lage
Output. Also, make the maximum value output circuit inoperative.
Thus, the current consumption is reduced. FIG. 27 (a) shows the limiter / decoder described in FIG.
3 shows a configuration of a enable signal (LM) generating circuit. Same figure
In, A₁₂And A₁₃Is the same as that shown in FIG.
Single-ended differential amplification circuit of configuration, 95 is differential amplification
Two outputs of the circuit as inputs, a magnitude equal to the power supply voltage difference
Shows a double-ended differential amplifier circuit that outputs
ing. Double-ended differential amplifier has two inputs
P-channel MOS-FET T driven respectively by₁₈₀When
T₁₈₁To reduce the voltage applied to the gate oxide film.
P-channel MOS-FET T for₁₈₄And T₁₈₅Cross-coupled
Two N-channel MOS-FET T₁₈₂And T₁₈₃, Its gate acid
N-channel MOS to relax the voltage applied to the oxide film
−FET T₁₈₆And T₁₈₇To accelerate the output reversing speed
Speed-up capacity C_C1And C_C2Composed by
I have. Among these, the speed-up capacity is the response speed of the circuit
The basics can be omitted depending on the application.
Operation is not impaired. Hereinafter, as shown in FIG.
The operation will be described with reference to the operation timing chart described above.
In the following description, the internal power supply voltage V
_CLIs 1.5V (V_L= 0.75V). As shown in the figure
External power supply voltage V_CCIf V drops from 4V to 1V, V_CC
Time t at which half of the voltage crosses 0.75V₀Differential increase in
Width circuit A₁₂And A₁₃Output (node N_{twenty five}And N₂₆)
The pressure reverses. Thereby, the transistor T₁₈₀Is cut
Off state, T₁₈₁Transitions to the ON state, and node N₂₈Voltage
Is V_CCTo rise. Node N synchronized with this₃₀Potential of
V_n−V_TN1(V_TN1Is T₁₈₇Threshold voltage), and
Code N₂₉And node N₂₇Potential to ground potential
You. This allows the output of the double-ended differential amplifier circuit
N₂₇And N₂₈Voltage is inverted, 0V and V_CC= 1
Become V FIG. 27 (b) schematically shows the operation.
However, in practice, these series of operations are based on the power supply voltage.
It takes place in a time sufficiently short compared to the change. Therefore,
Changes in the source voltage do not adversely affect circuit operation.
Also, consciously provide capacitance in the power supply wiring in the chip.
Controls the change in power supply voltage,
The effect can be kept lower. The above is the external power supply
The case where the pressure is reduced was described.
The same operation is performed when increasing the voltage. Now, other LSIs and semiconductor devices of the LSI chip according to the present invention
When configuring a system with
It is necessary to match the input and output levels of the signals exchanged.
You. For LSIs operating on a single power supply (generally 5V)
There are the following two standard input / output levels.
You. (A) TTL level (b) CMOS level At the TTL level, high voltage (“1”) output (V_OH)
Must be greater than or equal to 2.4V. Therefore, the power
Use CMOS level when using voltage below 2.4V
Alternatively, it is necessary to set a new input / output level standard. Obedience
When configuring a system with conventional LSI and TTL logic circuits, etc.
In this case, it is important to maintain compatibility with the input / output levels described above.
Element. Level conversion circuit by taking compatibility
Is unnecessary, the number of parts is reduced, and the cost of the system is reduced.
It leads to reduction. Also, circuit performance such as noise resistance and speed
Can improve and maximize performance
You. Therefore, in the following, compatibility with the conventional input / output level
Example of the present invention having an input / output circuit configuration that maintains
I do. According to the present invention, a design change can be made using one chip.
The following three product specifications can be realized without modification. (1) During standard operation (for example, power supply voltage V_CCIs 4.5-5.5V
Or 3 to 3.6V) input / output at TTL level. Must
V if necessary_CC(For example, the power supply voltage V_CCIs 1.0 to 2.5
V) etc. in the chip to retain information (battery battery
Do). (2) Power supply voltage V_CCOperates at 1.0-5.5V,
Power is at the CMOS level. V as required_CCDecline (for example,
Power supply voltage V_CC1.0-2.5V) in the chip
Or hold information by external control signal (battery
Backup). (3) Power supply voltage V_CCBut operates at 1. ~ 5.5V, for example,
The chip automatically switches the input / output level according to the voltage value.
Change. For example, when the power supply voltage V is 2.5 to 5.5 V, the TTL level
Level, CMOS level when power supply voltage is 1.0 ~ 2.5V
Do the force. FIG. 28 (a) shows wiring and bonding using one chip.
(1) and (2)
FIG. 28 (b) shows an example of realizing the two products
Automatically detects changes in pressure value and switches input / output levels
The example of the realization of the product which can be obtained is shown. Fig. 28 (a)
, 1 is an LSI chip, 5 is an internal power supply voltage (for example,
1.5V) operating LSI circuit block, PAD_TIs for TTL level
I / O pad, PAD_CIs the input / output pad for CMOS level,
IB₁And OB₁Are the input and output buffers for the TTL level.
Fa, IB_TwoAnd OB_TwoIs the input buffer and output for CMOS level.
Power buffer, SW_IIs the output of the two input buffers
Input to the low-voltage operation LSI circuit block
Switch for SW_OIs the output of the low-voltage operation LSI circuit block.
Choose which of the two output buffers the force is applied to
Are shown. This switching
The method of performing this in an actual LSI is to use aluminum
There is a master slice by wiring such as a system. This is al
When forming a wiring layer such as minium,
The mask for performing the transfer is set to 2 corresponding to the above switch.
Those who prepare according to the situation and use different masks according to the product
Is the law. Furthermore, two types of buttons corresponding to the input / output levels
The bonding pad is provided on the LSI, and one of
To make two products
Can be opened. Also, one bonding pad
In the case where the master
The connection to the input / output buffer can be switched by rice.
No. FIG. 28 (b) shows one input / output buffer each.
And the input / output level of the input / output buffer according to the value of the power supply voltage.
The method of switching the bell is shown. In the figure, PAD_XIs in
Output pad, IB_ThreeAnd OB_ThreeIs the input buffer and output buffer
96 indicates the input / output level of each buffer according to the power supply voltage.
The input / output level setting circuits to be controlled are shown.
Regarding this, a more specific configuration example will be described later.
With the above configuration, the above three product specifications can be
Can be realized by chip, product cost aspect
It is also convenient from the viewpoint of user convenience. What
In the above example, input and output are performed from the same terminal.
The example of the loose I / O common method has been described.
The present invention is the same for
Can be applied in any way. Below, output buffer, input buffer,
A specific configuration example of each of the input protection circuits will be described.
Note that, in the following embodiments, a thin (for example,
6.5nm) MOS-FET with gate oxide film
The case of configuration is explained, but it operates in one LSI chip
MOS-FET with two types of gate oxide films according to voltage
The present invention can be similarly applied to the case where it is used. When configuring the output buffer, the internal low signal amplitude
(Eg 1.5V) to external high signal amplitude (eg TTL level)
CMOS level when the bell is 2.4V and the power supply voltage is 5V5
It is necessary to convert the amplitude to V). First, the CMOS level
An example of a circuit configuration for obtaining a bell output signal will be described. Fig. 29
(A) receives the low signal amplitude in1 of the internal circuit as input and
Shows an example of the configuration of an amplitude conversion circuit that outputs a new signal amplitude Out.
ing. In the figure, reference numeral 98 denotes the invar shown in FIG.
Data circuit, N₃₁And N₃₂Are in2 in Fig. 20 (a), respectively.
And two inputs corresponding to in1, Out is the output of the inverter,
T₁₉₀Is N₃₂N-channel MOS-FET, T₁₉₁Is no
De N₃₂Limit the maximum voltage of T₁₉₀Applied to gate oxide film
N-channel MOS-FET, T to reduce the applied voltage₁₉₂Is the same
To node N₃₁P-channel MOS-FE that limits the minimum voltage of
T, R₆₅Indicates resistance. In this, Tran
Jista T₁₉₀And resistance R₆₅With the resistive load inverter circuit
Make up. By using a resistive load, the low-voltage side
Two outputs, low voltage side and high voltage side, are obtained from one input
Rukoto can. Next, referring to FIG.
The operation of the road will be described. In the following example, the power supply voltage is 5
V, bias voltage V_nAnd V_pAre both 2.5V
ing. When input in1 is 0V, transistor T₁₀₉Is
Off and node N₃₁Is the resistance R₆₅Power supply voltage to 5V
Up, also node N₃₂Is V_n(2.5V)
Lanista T₁₉₁Threshold voltage (for example, 0.5V)
It is the lower value (2V). Therefore, the inverter
The output voltage of 98 is 0V. Time t₀Input in1
Rises from 0V to 1.5V, the transistor T₁₉₀Is continuity
And node N₃₁Is V_p(2.5V) transistor T₁₉₂Noshiki
Value (3V) higher by the absolute value of the lower voltage (eg 0.5V)
And node N₃₂Is pulled down to 0V and the output Out rises to 5V
Ascend. Time t₁In, the input in1 falls from 1.5V to 0V
The output Out changes from 5V to 0V
You. Thus, with this circuit configuration, the 1.5V input signal
5V output signal required by output buffer for amplitude
Signal amplitude is obtained. Also, this circuit
Since only a maximum voltage of about 2.5 V is applied to the
MOS-FET using a large gate oxide film (for example, 6.5 nm)
A circuit that operates stably with a power supply voltage of 5 V can be configured.
You. FIG. 30 (a) shows the complementary low-amplitude signal in1 and
And in1 ~ as input and output with high signal amplitude Out
Another configuration example of the conversion circuit, FIG.
Is shown. In the figure, 102 is the one shown in FIG. 27 (a).
Double-ended input and double-ended output
The operational amplifier circuits, 100 and 101, are the same as those shown in FIG.
The same inverter circuit is shown. Dub used here
In a steady-state, the differential amplifier circuit with
Power consumption compared to the previous example
Circuit can be realized. Also, the inverter at the final output stage
The substrate (back gate) of each transistor that constitutes
In the channel, it is minus (-2V).
It is biased positive (7V) with respect to pressure (5V). This
As a result, for example,
Even if dark or overshoot appears in the output,
Prevents the PN junction from being forward biased
You. Therefore, minority carrier injection into the substrate (minority key)
When the carrier diffuses to the charge storage node of the memory cell,
Worsens the fresh characteristics), the parasitic thyristor turns on
Latch-up and the like can be prevented. The book
According to the invention, a low-amplitude signal (for example, 1.5 V) of the internal circuit
Circuit that outputs a CMOS-level high-amplitude signal (for example, 5V)
Can be easily configured. Generally, when configuring a system, one data
Connect the outputs of multiple LSIs to the output of the selected LSI.
I try to drive an injured bus. Such control is performed.
The output impedance of the unselected LSI
Is desirably set to infinity. In conventional LSI, the output
High and low voltages, and both
(The output impedance is infinite)
Output (tri-state) characteristics. like this
Drive the output (low impedance)
Dance) or not (infinite impedance)
It is necessary to take control. Is the signal for this control external?
Output enable signal (Output Enabl = OE)
And chip select signal (Chip Select = CS)
Generated from this. In conventional output circuits, these signals
And the output data, and the resulting signal
Driving the last transistor
Thus, a tri-state characteristic was realized. In the present invention
When configuring a similar output circuit with
Circuit that operates with the external power supply voltage
There may be a configuration that does not use roads. But on the spot
In the case, the amplitude conversion circuit between the logic circuit and the output
And the number of inverter stages increase, for example, from the OE signal to the output.
Delay time in the
Driving timing and driving low-voltage transistors
Timing, a large current flows transiently.
Disadvantage. On the other hand, the external power supply voltage
If a logic circuit can be configured, the degree of freedom in design will increase,
It is also preferable from the viewpoint of performance. The following discussion is based on the external power supply voltage.
An embodiment in which a logical circuit is configured will be described. Note that this logic
The circuit operates with an external power supply voltage in addition to the output buffer
It is also effective as a means for generating control signals for various circuits.
You. FIG. 31 shows a configuration example of a two-input NAND circuit according to the present invention.
doing. The A input in FIG. 31 (a) corresponds to in1A and
And in2A and B input correspond to in1B and in2B respectively.
You. Of each input signal, in1A and in2A, and in1B and in2B
Similar to in1 and in2 in FIG. 20 (a), they change in phase.
In FIG. 31 (b), the transistor T₂₀₀And T₂₀₁Is low
Driven by the input signals in1A and in1B on the
Jista T₂₀₂And T₂₀₃Are the input signals in2A and in2B on the high voltage side.
Driven by Transistor T₂₀₄And T₂₀₅Figure 20
(A) T₂₀₂And T₂₀₃As well as applicable to gate oxide
It is provided to operate at a voltage higher than the voltage.
You. With this configuration, when both inputs are high level
Only when the output is low,
It is. Thus, in addition to a normal CMOS NAND circuit, two
Just add a transistor, you can
Can be used at high power supply voltages. Here, 2
The input NAND circuit was explained as an example, but other examples
For example, NOR circuit, exclusive OR circuit, 3 or more inputs
Input of the output of multiple logic circuits
Composite gates that output various composite logics, and latches
Similarly for sequential circuits such as circuits and flip-flop circuits
The present invention is applicable. FIG. 32 (a) shows a tri-state using this logic circuit.
3 shows an example of the configuration of the output buffer. Fig. 32
(B) is a simplified version of this using logical symbols.
It is. In the figure, G₁₂Is a 2-input NAND circuit, G₁₃Is 2
Input NOR circuit, T₂₁₀And T₂₁₁Constitutes an output circuit
N-channel and P-channel MOS-FETs. Output
When enable signal OE is high, output D_OEnter
Force d_OData is output from the buffer and OE is low
In the case of, T regardless of the input data₂₁₀The gate is low
Voltage, T₂₁₁Is fixed to high voltage,
D_OIs floating (impedance is almost infinite)
Become. FIG. 32 (a) shows the withstand voltage lower than the value of the external power supply voltage.
Circuits that have the same function and are configured using elements with small pressure
It is a specific configuration example of a road. In the figure, 112 is NAND
Circuit, 113 is NOR circuit, 114 is output circuit, 110 and 111 are 30th
This is the same amplitude conversion circuit as 102 in FIG. Amplitude conversion
The path is a low-amplitude signal do1, o on the low supply voltage side from the internal circuit.
necessary to operate 112 and 113 based on e1, oe1 ~
Generates signals do2, oe2, oe2 ~ on the high power supply voltage side. here
As shown in the above, according to the present invention, using a fine element
Also operate with an external power supply voltage exceeding its withstand voltage
And delay time of tri-state output circuit etc.
Transient current can be reduced. Next, an example of a CMOS level input circuit will be described with reference to FIG.
You. In this figure, 115 is the same as that shown in FIG.
Same inverter, T₂₂₀And T₂₂₁Is a large signal swing at the input.
Transistor T even when width is applied₂₂₂And T₂₂₃Gate of
The voltage applied to the oxide film must be limited to the oxide film breakdown voltage or less.
X is an input signal. Smell this figure
Therefore, even if a high voltage (for example, 5 V) is applied to the input,
De N₄₀Voltage is V_n−V_T1(T₂₂₀), That is, about 2V
Is limited to Similarly, a low voltage (for example, 0
V) is applied, the node N₄₁The minimum value of the voltage applied to
It is about 3V, and the voltage applied to each transistor is
The voltage can be reduced to about half of the voltage. Also,
The signal amplitude of x1 ~, one of the outputs of this circuit, is about 2V.
Therefore, this is an internal circuit that operates at low power supply voltage
Can be input. In the above embodiment, the CMOS-level output circuit and the input
An example of a circuit has been described. Next, the value of the power supply voltage
Input circuit that switches between TTL level and CMOS level
FIG. 34 (a) shows an example of the output circuit. In the figure, PA
D_IIs the input pad, PAD_OIs an output pad, IPD is due to static electricity.
IB, input protection element to prevent junction and gate breakdown_Five
Is the input buffer, OB_FiveIndicates the output buffer respectively
I have. The input protection element will be described later in detail.
You. Input buffer IB_FiveIs a CMOS inverter 2
MOS-FET T_IN1And T_IP1, CMOS inverter power supply voltage
The bias voltage V_n1Limited to a certain value determined by
N-channel MOS-FET T for_IN2, CMOS inverter
An N channel for similarly limiting the input voltage to a predetermined value or less.
Flannel MOS-FET T_IN0, Consisting of In addition, output battery
Fa OB_FiveIs an invar similar to that shown in FIG.
116, a low-amplitude signal d from the internal circuit_outBased on
Amplitude conversion circuit 11 for generating data drive signals d1 and d2
7.Inverter output voltage is bias voltage V_n1Determined by
N-channel MOS-FET T for limiting to below a predetermined value
_ON2, Is composed of. The same as shown in FIG. 32
By taking the logic with the output enable signal,
Buffers with tri-state output characteristics can be configured
Needless to say. Now, in these circuits,
Ias voltage V_n1Value appropriately according to the power supply voltage.
TTL level at high power supply voltage, C at low power supply voltage
Input / output can be performed at the MOS level. Fig. 34
(B) is the bias power supply voltage V_n1Power supply voltage V_CCTo
An example of the dependency is shown. In the figure, V_OLAnd V_OH
Is the TTL output level corresponding to “0” and “1” respectively, V_IL
And V_IHIs the TTL input level corresponding to “0” and “1” respectively
Is shown. These TTL logic gates
The value is V_OL= 0.4V, V_OH2.4V, V_IL= 0.8V and V_IH= 2.
0V. Also, the bias power supply voltage V_n1The value of
3V when the voltage is 2.5V or more, and when the power supply voltage is 2.5V or less
T_IN0Operate in the unsaturated region, for example, V_CC+
It is controlled to be 0.5V. First, the output buffer
The operation of the circuit will be described. Node N₄₈The voltage is low voltage
0V and high voltage (“1”) when outputting (“0”)
When you do V_CCBecomes Therefore, at low voltage output
Is 0V is D regardless of the value of power supply voltage_outIs output to on the other hand,
D at high voltage output_outIs as shown in FIG. 34 (b).
Power supply voltage V_CCDepends on the value of_CCV when ≥3V_n1−V_T1
(T_ON2), V_CC<3V for V_CCbecome. This allows
Meets TTL level output characteristics when the power supply voltage is 3V or more
The output voltage amplitude can be obtained. It should be noted that
By limiting the input voltage to 2.5V or less,
Power supply current when charging and discharging
Can be reduced. Next, the operation of the input buffer circuit
Will be described. T_IN1And T_IP1CMOS inverter composed of
Power supply voltage is transistor T_IN1From the source terminal of
Be paid. Therefore, its value depends on the power supply voltage
Sometimes it becomes 2.5V, and when it is 3V or less, it becomes 0V. On the other hand,
When the voltage is 3V or more, the input voltage of the inverter is 2.5V or less
And D when the voltage is 3V or less_inEntered
The applied voltage is applied as it is. With this circuit configuration,
Even if the power supply voltage changes greatly from 1V to 5.5V, for example,
The power supply voltage of the inverter and the maximum amplitude of the input signal are almost equal
It becomes difficult. Of the two transistors that make up the inverter
If the channel conductance is set almost equal,
The logic threshold voltage of the inverter is half of the power supply voltage
Become. Therefore, the logic threshold when the power supply voltage is 3 V or more
The low threshold voltage is the logical threshold voltage when the voltage is
Pressure is V_CC/ 2, at a certain voltage (3V in this example)
TTL level at higher power supply voltage,
Provides input buffer that operates at CMOS level at power supply voltage
can do. As described above, according to the present invention,
For example, in an LSI having a wide operating power supply voltage range,
Operation at the optimal input / output level at the power supply voltage value is possible
And that. This reduces the maximum noise margin to the minimum.
It can be realized with power consumption. In the output buffer,
Three transistors T_ON0, T_ON1, T_ON2Each board (back
Gate). By doing this, the output
When a high voltage surge is applied to the terminals, the charge is
It can be discharged at a high speed by a large current. this
Is a clamp MOS-F in the input protection element described later.
Same as ET operation, breakdown increases substrate potential
When rising, the parasitic bipolar that exists between the ground potential
This is to make it easy to turn on the transistor. This
Even if a fine element is used, the output
Can be up. In the above embodiment, N
Substrate voltage V of channel MOS-FET_BP1The value of
PN junction in order when negative (undershoot)
Negative values (eg-
3V), but the flow of forward current is
If allowed, 0V is acceptable. Also, N-channel MOS-F
The ET may be formed in a P-type substrate or as shown in FIG.
Formed in a P well electrically insulated from the P substrate
You may. In the latter case, the resistance of the P-well is the resistance of the substrate
Lower, the parasitic bipolar transistor may turn on.
This has the effect of increasing the electrostatic breakdown voltage. In the above embodiment, the bias voltage V higher than the power supply voltage
_n1Need to occur. Such a bias voltage
An example of configuring an input buffer without using it is shown in FIG.
You. In the figure, the input buffer IB₆Is two circuit blocks
IB_6aAnd IB_6bIt is composed of IB_6aFigure 34
(A) Input buffer IB_FiveThe circuit configuration is the same as that of Ma
IB_6bIs IB_6aOutput is convenient for driving internal circuits.
It is a circuit that converts to a good voltage level. IB_6bAt
T₂₃₁And T₂₃₂Is the two MOS-FEs that make up the CMOS inverter
T, T₂₃₃Is d_inN is low when₅₂To the internal
Source voltage V_CLP-channel MOS-FET for pulling up to T
₂₃₀Is the node N₅₂Becomes high voltage, N₅₂To N₅₁What
N-channel MOS-FET to prevent current from flowing back
is there. Bias voltage V in this circuit configuration_n2Power supply
Pressure V_CCFIG. 35 (b) shows the dependence on. Power-supply voltage
3V (constant) when the power supply voltage is 3V or more, when the power supply voltage is 3V or less
Is the power supply voltage V_CCTo be equal to This time
The operation of the road will be described in two cases. Fig. 35 (c)
Is the power supply voltage V_CCIs 5V, internal power supply voltage V_CLIs 1.5V
5 shows operation waveforms of the unit. If the input voltage is low (for example,
0.4V), the node N₅₁Voltage is V_n2−V_T1(T
_IN5) (Eg 2.5V), node N₅₂Voltage is V_CL(1.5V)
Becomes d_inOutputs a low voltage (0 V). Input power
Voltage from low voltage (eg 0.4V) to high voltage (eg 2.4V)
Changes, node N₅₀Voltage rises accordingly
And node N₅₁Voltage to 0V. T₂₃₀Channel
Le conductance is T₂₃₃Set larger than that of
And node N₅₂Is also reduced to almost 0V, d_in
Is V_CL(1.5V). Conversely, the input
The voltage is changed from a high voltage (for example, 2.4 V) to a low voltage (for example, 0.4).
V) changes to node N₅₀Voltage follows it
Down, node N₅₁The voltage of V_n2−V_T1(T_IN5) (Eg 2.5
V). Thus, node N₅₂Voltage is V
_CL−V_T1(T₂₃₀) (For example, 1.2V) and d_in
To 0V. This gives T₂₃₃Turns on and the node
N₅₂The voltage of V_CL−V_T1(T₂₃₀) To V_CL(1.5V)
increase. Thus, T₂₃₃By node N₅₂Return to
Because N_{twenty two}Is the same as the power supply voltage, and T
₂₃₁And T₂₃₂Through current in the CMOS inverter composed of
It can be prevented from flowing. Next, FIG. 35 (d) shows the power supply voltage V_CCAnd internal power supply voltage V_CL
Shows the operation waveforms of the respective units when both are 1.5V. input
Is low (for example, 0V), the node N₅₁of
Voltage is V_n2−V_T1(T_IN5) (Eg 1.2V), node N₅₂of
Voltage is V_CL(1.5V) and d_inOutput low voltage (0V)
Is done. Input voltage is low (eg 0V) to high
(For example, 1.5V), the node N₅₀Voltage is V_n2−
V_T1(T_IN5) (Eg, 1.2V)₅₁No electricity
Reduce pressure to 0V. T₂₃₀The channel conductance of
T₂₃₃Node N₅₂of
The voltage is also reduced to almost 0V, d_inIs V_CL(1.5V)
To rise. Conversely, if the input voltage is high (for example,
From 1.5V to a low voltage (eg 0V)
N₅₀Voltage follows and drops to 0V, causing node N₅₁of
Voltage to V_n2−V_T1(T_IN5) (For example, 1.2V)
You. Thus, node N₅₂Voltage is V_CL−V_T1(T₂₃₀)
(For example, 1.2V), d_inTo 0V
You. This gives T₂₃₃Turns on and node N₅₂The voltage of V_CL−
V_T1(T₂₃₀) To V_CL(1.5V). like this
Power supply voltage is low and IB_6aOutput amplitude below the power supply voltage
Node N even if₅₂Voltage amplitude is the same as the power supply voltage
T₂₃₁And T₂₃₂CMOS inverter composed of
Does not flow through. As mentioned above, the power supply voltage
Even without using a higher bias voltage,
Input / output buffer that switches the signal according to the value of the power supply voltage.
Can be realized. Finally, in an LSI composed of fine elements,
Input protection element that protects internal circuit elements from input surge
FIG. 36 (a) shows a configuration example of the child. In the figure, PAD_I
Is an input pad for inputting signals, and 120 is formed in the semiconductor substrate.
Using punch-through between the formed impurity diffusion layers,
To release high voltage to ground potential
1 protection element, 121 is node N₆₀To a certain predetermined voltage.
Gate clamp element to limit the pressure below R₇₀Is pa
Absorbs the difference between the high voltage applied to the
Resistance for Gate clamp elements are connected in series
Two N-channel MOS-FET T_PD1And T_PD2, That
Bipolar transistor Q using parasitic elements₁And
It is composed of T_PD1The gate of the same
Like, bias voltage V_nAnd T_PD2Gate to drain
This prevents a voltage exceeding the oxide film breakdown voltage from being applied. T_PD2
Gate is grounded and, during normal operation, passes through two MOS-FETs.
To prevent current from flowing. Gate clamp element
FIG. 36 (b) shows the cross-sectional structure at A, A '
The structure is shown in FIG. 36 (c). In FIG. 36 (b)
Where 122 and 123 are electrically isolated from each other
Electrically active regions formed in the substrate, 124 and 125
Is a gate electrode made of polysilicon or the like, 126 to 1
Impurity diffusion formed in electrically active regions up to 30
Layer or gate electrode from the top metallization
Contour provided through insulating film to make connection
The holes 131 to 134 are made of aluminum, etc.
Metal wirings are shown. FIG. 36 (c)
In the figure, reference numeral 50 denotes a voltage between electrically active regions in a semiconductor substrate.
Thickness formed by oxidation of the substrate for gas insulation
Insulating films, 139 and 14 are polysilicon forming the gate electrode, 1
For 35 to 138, mask the above insulating film or gate electrode
Impurity diffusion layer formed in the substrate in a self-aligned
1 is a metal wiring located above the impurity diffusion layer or gate electrode.
Thick insulation formed to provide electrical insulation between lines
, Respectively. In the structure shown in FIG.
2 is a clamped terminal (node N₆₀), Wiring 133 and 1
34 has a ground terminal (V_SS), The bias voltage V
_nAre respectively applied. In FIG. 36 (c), the P group
Plate-based three NPN-type parasitic bipolar transformers
Jista Q_1a, Q_1bAnd Q_1cExists. Fig. 36 (a)
Q₁Are representative of these. Then this
The operation of the device will be described. Node N₆₀Voltage applied to
PN junction formed between the impurity diffusion layer 136 and the substrate
Above the reverse breakdown voltage of
The potential of the plate is raised, and the parasitic bipolar transistor
Turn on. As a result, the impurity diffusion layers 136 and 135,
Or 138, a large collector current flows and the node N
₆₀Is extracted and its potential is clamped. these
Q out of_1bAnd Q_1cAre connected in series, so Q_1aCompared to
The collector current decreases. Therefore, in effect,
Breakdown occurs first, turns on parasitic bipolar transistor
This is done by the MOS-FET, then the large collector
The current flows through the parasitic bipolar transistor Q_1aDo
U. Thus, node N₆₀Near the transistor
Provide an impurity diffusion layer separate from the pure diffusion layer and ground it.
The collector of the parasitic bipolar transistor
To reduce the effective distance between the
Increase the collector current when the transistor operates
I can do it. In this way, the connection near the terminal to be clamped
The arrangement of the grounded impurity diffusion layer is
Not only that, it can also be applied as an output protection element. Also,
In this example, the gate clamp element was formed in the P substrate
However, it has a structure as shown in FIG. 14 and is electrically separated from the substrate.
May be formed in the formed P well. By doing this
The resistance of the base and P-well increases,
Roller transistor is easily turned on, and the effect of clamping
Can be further enhanced. In addition, P board or P
Well bias voltage V_BP1Is a negative value (for example,
-3V), but undershoot of input
If the forward current is allowed to flow through the
I do not care. In this embodiment, an example using a P substrate is described.
As described above, even if an N substrate is used,
The present invention can be similarly applied if a child is formed. As described above, the details of the present invention have been described with reference to the embodiments.
The scope of the present invention is not limited to this. An example
For example, here we mainly describe memory circuits,
As mentioned at the beginning of the specification, memory LSI, logic LSI,
Or a composite LSI combining these, or other L
Applicable to all SIs. Also, depending on the type of element used
Also, L using both p-type and n-type MOS transistors
SI, LSI using bipolar transistor, junction type FET
LSI, CMOS transistor and bipolar transistor
BiCMOS-type LSI with a combination of capacitors, and other than silicon
Device on a substrate such as gallium arsenide
The same can be applied to LSIs and the like.

【The invention's effect】

According to the present invention described above, a high integration that can operate at a low power consumption and at a high speed, and can also perform a battery operation and an information holding operation by switching operation states, utilizing the characteristics of the element by the latest microfabrication technology. LSI can be provided.

[Brief description of the drawings]

1 and 2 show an embodiment for explaining the basic concept of the present invention, FIG. 3 shows an embodiment in which the present invention is applied to a static memory, and FIGS. 4 to 8 show an embodiment in which the present invention is applied to a dynamic memory. Embodiments, FIGS. 9 to 11 show other embodiments for explaining the basic concept of the present invention, FIGS. 12 and 13 show specific embodiments of the elements constituting the present invention, and FIG. 14 shows the present invention. FIG. 15 is a specific embodiment for reducing power consumption when information is retained, and FIGS. 16 to 19 are specific embodiments of a dynamic memory operating at a low voltage. Example, 20th
FIGS. To 27 are specific examples of various circuits operated at a voltage higher than the gate breakdown voltage of a fine element, FIG. 28 is an example showing the basic concept of the configuration of an input / output circuit, and FIGS. 29 to 32 33 is a specific embodiment of an output circuit, FIGS. 33 to 35 are drawings of a specific embodiment of an input circuit, and FIG. 36 is a drawing of a specific embodiment of an input holding element. DESCRIPTION OF SYMBOLS 1 ... LSI chip, 5 ... Internal circuit section, 6 ... Voltage conversion circuit,
7 input / output circuit, 8 information holding state detection circuit, 9 reference voltage generation circuit, 10 limiter enable signal generation circuit,
11: External I / O bus, 12: Internal I / O bus.

────────────────────────────────────────────────── (5) Continuation of the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 27/04 27/108 (56) References A) JP-A-2-71491 (JP, A) JP-A-62-163563 (JP, A) JP-A-1-129769 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) ) G11C 11/407

Claims (4)

(57) [Claims] A first node supplied with a first voltage; a reference voltage generating circuit for generating a reference voltage; and an internal voltage output from a second node in response to the first voltage supplied to the first node. And a circuit block that operates by receiving the internal voltage, wherein the semiconductor device performs a first operation in accordance with a voltage of the first voltage.
A power supply voltage range and a second power supply voltage range smaller than the first power supply voltage range.
A power supply voltage range, wherein the voltage conversion circuit comprises: a first voltage conversion circuit for forming the internal voltage based on the reference voltage in the first power supply voltage range; A second for forming the internal voltage based on a reference voltage;
A semiconductor device comprising: a voltage conversion circuit; and switch means for short-circuiting the first node and the second node when the first voltage falls below a predetermined voltage within the second power supply voltage range. apparatus. 2. The semiconductor device according to claim 1, wherein said reference voltage is substantially constant regardless of a change in said first voltage. 3. The information storage circuit according to claim 1, wherein the circuit block is an information storage circuit having a plurality of memory cells, and the first power supply voltage range is a power supply voltage at which the information storage circuit operates normally. 2. The semiconductor device according to claim 1, wherein the power supply voltage range is a power supply voltage at which the information storage circuit performs an information holding operation for holding the stored information. 4. The semiconductor device according to claim 1, wherein said circuit block consumes less current in said second power supply voltage range than in said first power supply voltage range.