JP3460713B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a highly integrated semiconductor device composed of fine elements capable of supporting a wide range of power supply voltages and power supply types.

[0002]

2. Description of the Related Art In recent years, it has been used for portable electronic information devices typified by laptop personal computers and electronic notebooks, solid-state recorders for recording voices without using a magnetic medium, solid-state cameras (electronic still cameras) for recording images, and the like. Representative portable electronic media devices are beginning to appear on the market. In order for these portable electronic devices to spread widely, the key is to realize an ultra-high integrated circuit (hereinafter abbreviated as ULSI) capable of battery operation or battery information retention operation (battery backup). On the other hand, as a large-capacity auxiliary storage device for realizing a higher-performance electronic computer, there is an increasing need for a semiconductor disk that can be accessed at a higher speed than a magnetic disk. A semiconductor disk requires an ultra-large-capacity memory LSI capable of holding information by a battery.

The following are required for ULSIs used for these purposes. (1) Wide power supply voltage range (1 to 5.5
V) operation. As a result, various types of power supplies, for example, the standard power supply voltage of the current TTL compatible digital LSI 5
V, or 3.3V, which is one of the standard power supply voltage candidates for future TTL compatible digital LSIs, and 3 to 3.6V, which is a typical output voltage of a primary battery using lithium or the like,
One chip can handle 1.2V, which is a typical output voltage of a secondary battery using cadmium and nickel. (2) Responding to changes in the power supply voltage over time (short-term or long-term). As a result, there is no fear of causing a malfunction even if the battery voltage is changed with time or the voltage is changed due to power supply switching at the time of transition between the standard operation and the battery backup operation. (3) Reduction of power consumption during operation or battery backup operation. As a result, even a small battery can be operated for a long time. (4) Reduction of transient current. As a result, transient fluctuations in the battery voltage can be reduced and malfunctions can be prevented.

An example of a microprocessor product that operates in a wide power supply voltage range is described on page 148 of NEC Corporation 4-bit Microprocessor Handbook. The product model name is μPD7507SC. The operating power supply voltage range of this microprocessor is 2.2 to 6.0V. Further, the information in the data memory can be held at a minimum of 2V. Similarly, in static memory,
Generally, the recommended operating power supply voltage is 5V, and 2V when information is retained (retention).

As a dynamic memory for backing up a battery, an example in which the current consumption during information retention (refresh) is reduced is shown in I.E.E.Journal of Solid State Circuits, Vol. 23, Vol. 1
Issue, pp. 12-18 (1988) (IEEE Jounal
of Solid-State Circuits, Vol.23, No.1, pp.12
-18, February 1988). In this case, the standard operating power supply voltage and the power supply voltage for holding information are both 5V.

[0006]

Although the microprocessor and the static memory described above have a wide operating power supply voltage range of 2 to 5 V, the power supply voltage =
Since it is designed around 5V, for operation outside the allowable power supply voltage fluctuation range (usually ± 10%),
The operating speed (maximum clock frequency in the case of a microprocessor, access time in the case of a static memory) is not guaranteed, and the operating speed is usually remarkably reduced especially at a low power supply voltage. Also, the power supply voltage dependency of the operating speed varies depending on the product,
It is necessary to match the slowest operation speed among the LSIs constituting the system, and operation at a voltage other than 5V does not provide the required performance or makes system design at a low power supply voltage extremely difficult. In addition, these LSI
Since the minimum operating power supply voltage is 2.2V, it is not possible to support all of the various power supplies described above, and the system configuration is restricted.

Considering the case where the above-mentioned dynamic memory is incorporated into a system, the minimum power supply voltage becomes 4.5 V, which makes it more difficult to deal with the various power supplies described above. In particular, since there is no difference between the standard operating power supply voltage and the power supply voltage at the time of holding information, the configuration of the power supply switching circuit becomes very complicated, making it difficult to hold information.

The miniaturization of semiconductor devices is rapidly progressing, and if a processing technique of 0.5 micron or less is used, some systems are integrated on one chip. It has become possible to configure a so-called system LSI. In such a system LSI, each LS that constitutes it is
It is required that the operating power supply voltage range and operating speed of the I block are matched. However, as mentioned above, such a system LSI can be obtained by simply combining conventional LSIs.
Could not be configured.

One of the objects of the present invention is to cope with various power supply voltages, consume a small amount of power, and utilize the device performance suitable for fine processing.

[0010]

The above object has a low power consumption mode suitable for battery backup and has a minimum voltage of 1V.
LSI circuit block that operates even with a low power supply voltage,
This can be achieved by configuring the device with a power supply voltage conversion circuit that provides the LSI with an optimum internal power supply environment for the operation mode and an input / output circuit that converts the signal amplitude.

Main LSI for storing and processing information
By operating the block at a substantially constant low voltage regardless of the value of the external power supply voltage, it is possible to obtain substantially constant speed performance over a wide power supply voltage range. In addition, since the external power supply voltage can be reduced to the operating voltage of the LSI block as needed, the power consumption at the time of holding information can be reduced to the minimum necessary value, and at the same time, the battery backup circuit can have a simple configuration. be able to. Moreover,
Since the optimum operating voltage corresponding to the characteristics of the fine elements that form the main LSI block can be set independently of the value of the external power supply voltage, high integration, high speed, and low power consumption can be simultaneously achieved.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment for explaining the basic concept of an LSI chip according to the present invention. In the figure, 1 is an LSI
Chip refers to an LSI chip that generally has an information storage function or an information processing function, and is a dynamic type or static type random access memory (RAM).
Alternatively, a memory LSI such as a serial access memory (SAM) or a read-only memory (ROM), a microprocessor (MPU), a memory management unit (MMU), a floating point arithmetic unit (F)
PU) such as a logic LSI, and further, a system LSI in which a plurality of such LSIs are integrated.
It may be an I-chip. The constituent elements may be bipolar transistors, MIS transistors, combinations of these elements, or elements other than silicon, such as gallium arsenide elements. Reference numeral 2 is an example of a power supply circuit that detects a drop in the external power supply voltage and shifts to a backup state using a battery. With such a power supply circuit, it is possible to prevent the necessary information stored in the LSI chip from being lost even if VEXT drops due to a momentary interruption of the commercial power supply. Among these, 3 is a power supply voltage drop detection circuit, SW is a switch for preventing a current from flowing from the battery to the external power supply terminal when holding information, 4 is a switch control signal, B is a battery, and VBT is its voltage. In the information holding mode, the entire chip operates with this battery as a power source. D is a diode for preventing current from flowing into the battery during normal operation. With this power supply circuit, VEXT is the power supply terminal (PAD) of the chip in the normal operation, and VBT is the data hold.
1) is applied.

In this example, the difference between the normal operation and the information holding operation is detected by the detecting means on the LSI chip.
Here, 5a and 5b are main circuit blocks, 5 is a set of them, and 6 is a power supply voltage conversion circuit for converting the power supply voltage Vcc input from the outside of the chip into the power supply voltages VCL1 and VCLn of each circuit block. In FIG. 6, 6a and 6c are conversion circuits for normal operation, and 6b and 6d are conversion circuits for holding information. Generally, since the operating voltage and the operating current of the circuit are smaller when the information is held than when the normal operation is performed, there is no problem even if the current consumption of the voltage conversion circuit that supplies the power supply voltage is reduced to lower the driving ability. . As a result, in combination with the low current consumption of the main circuit block,
It becomes possible to significantly reduce the current consumption of the entire SI chip. In this example, the method of switching between the two voltage conversion circuits is shown, but the number of conversion circuits may be three or more. Further, the output voltage and the consumption current may be changed by using one voltage conversion circuit. SW
6a and SW6c are switches for directly applying the power supply voltage Vcc to the circuit block when Vcc drops to a value substantially equal to Vcl1 or Vcln. By using the switch, the voltage conversion circuit can be turned off and the current consumption can be further reduced. In the above example, the power supply voltage conversion circuit is configured by the switch and the plurality of voltage conversion circuits. However, if a similar effect is obtained,
One voltage conversion circuit may be used. Further, reference numeral 9 in the figure is a circuit for generating the reference voltage VL. Based on this voltage, the internal power supply voltages VCL1 and VCLn are generated. Reference numeral 8 is a circuit for generating a signal PD indicating that the information holding operation is being performed. P
Although several methods of generating D can be considered, here, a method of comparing the power supply voltage VCC and the reference voltage VCX and outputting PD when the former is smaller than the latter is used. Reference numeral 10 is a generator circuit for the limiter enable signal LM. When the power supply voltage is higher than the internal power supply voltage and the voltage conversion circuit (voltage limiter) is operated, the high voltage (“1”) is set, and when the external power supply voltage is reduced to the same level as the internal power supply voltage, the low voltage (“1”) is set. ) Are output respectively. In the latter case, the power supply voltage is directly applied to the circuit block, and at the same time, the voltage conversion circuit is not operated, and the current consumption is suppressed to be small. In the example shown in the figure, the power supply voltage VCC
And the reference voltage VLX are compared, and LM is output when the former is larger than the latter. The output voltage and current consumption of the power supply voltage conversion circuit can be switched by the two signals PD and LM. In the figure, 7 is an input / output buffer, 1
Reference numeral 1 is an input / output bus for exchanging control signals and data with the outside of the chip, and 12 is an internal bus inside the chip for exchanging control signals and data between circuit blocks. The input / output buffer also serves as a level conversion circuit, and can transfer control signals and data even if the internal logic signal amplitude and the external logic signal amplitude do not match. Further, in the information holding operation state, it is not necessary to transfer control signals or data between the outside and the inside of the chip, so the input / output buffer is turned off by the information holding state signal PD.

FIG. 2 is a diagram showing an example of the relationship between the power supply voltage VCC and the internal power supply voltage VCL. In the figure, the horizontal axis is the power supply voltage V
CC, the vertical axis corresponds to the internal power supply voltage VCL. Here, the standard power supply voltage is 3 to 3.6 V, and the power supply voltage for holding information is 1
.About.2V, the reference voltage VCX for switching between the standard operation and the information holding is set to 2.5V.
x) and the reference voltage VCX, as long as the relationship of VBT (max) <VCX <VCC (min) is established, the value shown here is not necessary. Further, although the internal power supply voltage VCL in the standard operation is set to 1.5V, it may be set to an appropriate voltage value according to the operating performance of the circuit within a range not exceeding the power supply voltage VCC. Further, in this example, the value of VLX is set to 1.5V because the power supply voltage VCC is directly applied to the internal circuit at a power supply voltage of 1.5V or less.

In this LSI chip, the power supply voltage VCC
3 shows an example of changes over time of the internal power supply voltage VCL, the two control signals LM, and PD in the case where changes with time. Here, it is assumed that the power supply voltage VCC drops to 3.5V to 1V from time t0 to t3 and the power supply voltage VCC rises to 1 to 3.5V from time t4 to t7.
Power supply voltage VCC becomes smaller than VCX = 2.5V t1 to t
During the period of 6, the signal PD is at a high voltage (“1”), and the chip is in the information holding state. Further, the power supply voltage VCC is VLX =
During the period from t2 to t5 which is smaller than 1.5V, the signal LM is at a low voltage ("0"), and the power supply voltage Vcc is directly applied to the chip. Note that the voltage values shown here are only examples, and other voltage combinations can be similarly applied.

FIGS. 4 and 5 show an example of a method and a circuit configuration for generating the limiter enable signal LM. The signal LM may be changed from the high voltage (“1”) to the low voltage (“0”) at the place where it becomes equal to the internal power supply voltage VCL for the first time when the power supply voltage VCC is lowered. In this example, the voltage β proportional to the power supply voltage Vcc
Vcc (0 ≦ β ≦ 1) and the reference voltage VL are compared by a comparison circuit, and a high voltage (“1”) is output when the former is large, and a low voltage (“0”) is output when the former is small. . By thus inputting a voltage between the high voltage and the low voltage using a voltage proportional to the power supply voltage Vcc, the voltage amplification factor of the comparison circuit can be increased, which is convenient for the circuit operation. . For example, when β = 0.5 and VL = 0.75V,
VLX = 1.5V, and the limiter enable signal LM is high voltage (“1”) when the power supply voltage Vcc is 1.5V or higher.
And the voltage conversion circuit operates. Here, the power supply voltage V
The voltage proportional to CC can be generated by resistance division.

The information holding state signal P is shown in FIGS. 6 and 7.
An example of a method of generating D and a circuit configuration is shown. Basically, a circuit similar to the LM generation circuit described above can be used. In this case, the voltage α × VCC that is proportional to the power supply voltage VCC
(0 ≦ α ≦ 1) is input to the inverting input terminal of the comparison circuit.
For example, when α = 0.5 and VL = 0.75V, VCX = 2.
When the power supply voltage Vcc is 2.5 V or less, the information holding state signal PD becomes a high voltage ("1") and the information holding state is set. Here, the voltage proportional to the power supply voltage Vcc is generated by the resistance division of the resistors R1 and R2. The resistors R1 and R2 may be formed using any of an impurity diffusion layer formed in a semiconductor substrate, polysilicon, and a channel resistance of MIS-FET.

FIG. 8 shows an embodiment in which the present invention is applied to an LSI including a static memory as a part thereof.
In the figure, 5c is a memory cell array of static memory,
Reference numeral 5d is a circuit block such as a logic circuit that does not need to hold information, and the respective power supply voltages are VCL2 and VCL1. The memory cells are four N-channel MOS-FETs T6 to T9.
And two resistance elements R7 and R8. When the resistance value is R, the value of the current flowing through one memory cell is VCL2 / R. Therefore, it is desirable to reduce the voltage value as much as possible within the range where the noise margin can be secured when the information is held. As shown in FIG. 9, in this example, VCL2 in the standard operation is set to 1.5V, and VCL2 in the information holding example is set to 1V. The logic circuit block 5d is composed of an inverter and a logic gate. In the figure,
The arrows T11 and T13 indicate P-channel MOS-FETs, and the other T10 and T12 indicate N-channel MOS-FETs.
At the time of holding information, these logic circuits do not need to be operated, so that it is not necessary to supply a power supply voltage. Therefore,
Here, VCL1 in standard operation is 1.5V, and VCL in data retention
CL1 is set to 0V. Internal power supply voltage VCL2 and VCL1
Are supplied by the power supply voltage conversion circuit 6e or the P-channel MOS-FET T1 which operates as a switch. The power supply voltage conversion circuit includes a differential amplifier circuit A1, a resistor R3 provided to control an operating current of the differential amplifier circuit, two N-channel MOS-FETs T3 and T4, and an inverting input terminal of the differential amplifier circuit. It is composed of three resistors R4 to R6 provided to control the amount of feedback of P, a P channel MOS-FET T5, and a P channel MOS-FET T2 which operates as a switch. When the power supply voltage is high and the internal power supply voltage is lowered from Vcc, the limiter enable signal LM becomes a high voltage ("1"). At this time, T1 is cut off, and at the same time, T3 becomes conductive, a bias current is supplied to the differential amplification circuit A1, and a voltage proportional to the non-inverting input voltage VL is output. On the contrary, when the signal LM has a low voltage (“0”), T3 is cut off, and the bias current is not supplied to the differential amplifier circuit. Therefore, the power supply voltage Vcc is directly output as the internal power supply voltage. During the information holding operation, the information holding signal PD becomes a high voltage (“1”). At this time, the transistor T2 is cut off and the power supply to the circuit block 5d is stopped. On the other hand, T4 is cut off, and the value of the bias current of the differential amplifier circuit is determined by the resistor R3. The current consumed by the memory cell array in the information holding state is very small and can be regarded as a direct current which is substantially constant over time. Therefore,
The load drive capability of the differential amplifier circuit may be remarkably smaller than that in standard operation, and even if the bias current is significantly reduced, there is no problem in operation. At the same time, make T5 conductive,
By increasing the feedback amount of the differential amplifier circuit, the internal power supply voltage during the information holding operation is lowered. This makes it possible to significantly reduce the current consumption of the entire chip when holding information. In this example, VL = 0.75V, R4 =
R6 = 3R5. At this time, the value of VCL2 is 1.5 V in standard operation and 1.0 V in holding information.

FIG. 9 shows the power supply voltage VCC and the internal power supply voltage VCL2.
And VCL1 is shown as an example. In the figure, the horizontal axis represents the power supply voltage VCC and the vertical axis represents the internal power supply voltage VCL. Here, as in the example of FIG. 2, the standard power supply voltage is 3 to 3.6 V, the power supply voltage during information retention is 1 to 2 V, and the reference voltage VCX for switching between standard operation and information retention is 2.5 V. And Internal power supply voltage VCL2 and VCL1 during standard operation
Is 1.5V, and the internal power supply voltage VCL2 at the time of holding information is 1V. However, each may be set to an appropriate voltage value according to the operating performance of the circuit within a range not exceeding the power supply voltage VCC.

In this LSI chip, the power supply voltage VCC
FIG. 10 shows an example of the changes over time of the internal power supply voltages VCL2 and VCL1, and the two control signals LM and PD, respectively, in the case where changes with time. Here, the power supply voltage Vcc drops to 3.3 to 2 V from time t0 to t2, and time t3.
It is assumed that the power supply voltage Vcc rises to 2 to 3.3V from t5 to t5. During the period of t1 to t4 in which the power supply voltage Vcc becomes smaller than Vcx = 2.5V, the signal PD is at the high voltage ("1") and the chip is in the information holding state. In addition, since the power supply voltage Vcc does not become lower than 1.5 V in this time range, the signal LM remains at the high voltage ("1").

According to the above-described embodiment, a static memory that operates at high speed during standard operation and can hold information with a minimum required power when holding information, or a part of a static memory. L included in
SI can be realized. In the above embodiments, an example in which a static memory cell with a high resistance load is used has been described. However, in addition to this, for example, two CMOs are used.
CM consisting of S inverter and two selection transistors
OS type memory cell, two NAND gates or N
The present invention can be similarly applied to the case where the memory circuit is configured by a latch circuit using an OR gate.

FIG. 11 shows an embodiment in which the present invention is applied to a dynamic memory. In the figure, 5e is 1.5V
It is a dynamic memory that operates with the following power supply voltage,
One memory cell is composed of an N-channel MOS-FET T18 and a storage capacitor CS1. 13 is a memory cell array, 14 is a row address buffer, 15 is a column address buffer, 16 is a row address strobe (RAS) input buffer, 17 is a column address strobe (CAS) input buffer, and 18 is A write enable (WE) input buffer, 19 is a data input buffer, 20 is a data output buffer, 21 is a clock generation circuit that generates a control clock based on a row address strobe (RAS) signal, and 22 is a column address. A clock generation circuit for generating a control clock based on a strobe (CAS) signal, 23 a write clock generation circuit, 24 a refresh (RFSH) signal generation circuit, 25 a refresh address generation circuit, 26 a refresh address and external input The address switching It is a mux. Since information is stored in the dynamic memory by storing charges in the storage capacitor CS1, a so-called refresh operation of periodically reading the signal charges and rewriting is required even when the information is held, and other than the memory cell array. It is also necessary to operate some peripheral circuits. Further, in order to secure a sufficient noise margin, it is necessary to secure a signal charge amount equivalent to that in the standard operation even when the information is held. So in this example,
As shown in FIG. 12, the internal power supply voltage at the time of holding information and the standard operation is not changed and is set to 1.5 V (constant). Since it is not necessary to perform input / output with the outside of the chip at the time of holding information, all the input / output buffers 14 to 20 have the signal PD.
Is cut off by. Further, the multiplexer is controlled by the signal PD, and when the information is held, the address is switched to the address output by the refresh address generation circuit. During the refresh operation, the signal RFSH becomes a high voltage (“1”). This signal is input to the refresh address generation circuit to sequentially increase or decrease the refresh address. At the same time, RFSH activates the clock generation circuit 21 to generate the clock required for refresh. The internal power supply voltage VCL is supplied by the power supply voltage conversion circuit 6f and the P-channel MOS-FET T14 which operates as a switch. The power supply voltage conversion circuit includes a differential amplification circuit A2, a resistor R9 provided to control the operating current of the differential amplification circuit, and three N-channel MOS-FETs T15 and T1.
6, T17, and two resistors R10 and R11 provided to control the amount of feedback to the inverting input terminal of the differential amplifier circuit. When the power supply voltage is high and the internal power supply voltage is lowered from Vcc, the limiter enable signal LM becomes a high voltage ("1"). At this time, T14 is cut off, and at the same time, T15 becomes conductive, a bias current is supplied to the differential amplifier circuit A2, and a voltage proportional to the non-inverting input voltage VL is output. On the contrary, when the signal LM has a low voltage (“0”), T15 is cut off, and the bias current is not supplied to the differential amplifier circuit. Therefore, the power supply voltage Vcc is directly output as the internal power supply voltage. During the information holding operation, the information holding signal PD becomes a high voltage (“1”). At this time, T16 is cut off, and the value of the bias current of the differential amplifier circuit is determined by the resistor R9. The current consumption is small while the information is held and the peripheral circuits are not operating. Therefore, the load drive capability of the differential amplifier circuit may be remarkably smaller than that in the standard operation, and even if the bias current is remarkably reduced, there is no operational problem. During the refresh operation, the signal RFSH is fed back to the voltage conversion circuit 6 to make T17 conductive, and the bias current of the differential amplifier circuit is set to a value similar to that in the standard operation. By doing so, it is possible to supply the power supply current necessary for charging / discharging the data lines and operating the peripheral circuits during the refresh operation period. Therefore, even when the information is held, the current consumption of the entire chip can be significantly reduced without reducing the noise margin. In this example, VL = 0.
Although VCL = 1.5V is obtained with 75V and R10 = R11, other combinations of voltage values and resistance values may be used.

In this LSI chip, the power supply voltage VCC
12 shows an example of changes over time of the internal power supply voltage VCL, the two control signals LM, PD, the refresh signal RFSH, and the bias current value of the differential amplifier circuit when changes occur over time. Here, the power supply voltage Vcc drops to 3.3 to 2 V from time t0 to t2, and time t3 to t.
It is considered that the power supply voltage Vcc rises to 2 to 3.3V over the period of 5. During the period of t1 to t4 in which the power supply voltage Vcc becomes smaller than Vcx = 2.5V, the signal PD is at the high voltage ("1") and the chip is in the information holding state. In addition, since the power supply voltage Vcc does not become lower than 1.5 V in this time range, the signal LM remains at the high voltage ("1"). During the information holding period, during the refresh operation, the bias current IB1 that is substantially the same as that during the standard operation is supplied, and otherwise, a sufficiently small value IB2 is supplied.

In the example described above, the row address and the column address are temporally switched from the same address bus. Although the so-called address multiplex method is used, the present invention can be similarly applied by using a general method of simultaneously capturing all addresses. Also,
Japanese Patent Application 63-148104 and Japanese Patent Application 63-223317
By using a dynamic memory that drives the plate to reduce the voltage amplitude of the data line, as described in (1), a memory with lower power consumption can be realized.

FIGS. 13A and 13B show an example of the timing of the refresh signal RFSH when holding information. Here, an example in which all memory arrays are refreshed in 4096 cycles is shown. By reducing the power supply voltage to, for example, 1.5 V or less, the current consumption of the entire memory can be significantly reduced. Therefore, even if the memory has a large capacity of about 64 Mb, it is necessary to increase the refresh cycle from 4096. It becomes easy to configure the system. In the first 4096 cycles after the shift to the information holding state, intensive refresh, that is, the signal RFSH is generated in a relatively short cycle TC1. This is because the refresh control during standard operation is R
This is because it has nothing to do with internal refresh by FSH. By performing such initialization, it is possible to avoid the risk that the specifications of the refresh cycle will not be satisfied before and after the state transition. In FIG. 13A, after the concentrated refresh, the signal RFSH is generated at a constant cycle TC2. On the other hand, in FIG. 9B, the period of the signal RFSH during the concentrated refresh in which the concentrated refresh is repeated at the period TC3 is set to the same value TC1 as that of the first concentrated refresh. This value may be any other value, but it is convenient to use the same value in terms of the configuration of the signal generating circuit.

FIG. 14 shows an example of the chip temperature dependence of the refresh cycle TC2 for the example of FIG. 13 (a). The relationship between chip temperature and information retention time is
EE Transactions on Electron Devices, Vol. 35, No. 8, 1257-
1263 (1987) (IEEE Transactions on
Electron Devices, Vol.35, No.8, pp.1257-1
263, August 1987).
According to this, the change of the information holding time when the chip temperature changes from 0 to 100 ° C. is about three digits. Therefore, by changing the refresh cycle TC2 as shown in FIG. 14, it is possible to match the actual information holding characteristic. Since the power consumption of the chip is extremely small in the information holding state, there is almost no difference between the ambient temperature and the chip temperature. Therefore, by using at low ambient temperature,
The refresh cycle can be extended and the power consumption can be further reduced. This makes it possible to provide a dynamic memory suitable for mounting on a portable electronic device or the like that uses a battery as a power source. An oscillator circuit having temperature dependence as shown in FIG. 14 is described in Japanese Patent Laid-Open No. 136088/1985.

FIG. 15 shows an example when a refresh failure occurs in the example of FIG. 13 (b). In the figure, the horizontal axis represents the refresh cycle and the vertical axis represents the cumulative defect frequency. Only one bit is defective with respect to the refresh cycle TC3. If only a small part of the memory is defective,
There is a so-called defect relief technique in which a defective memory cell is repaired by replacing it with a spare memory cell provided on a chip in advance. This technology, for example,
EE Journal of Solid State Circuits, Vol. 16, No. 5, 479-48
Page 7 (1981) (IEEE Journal of Solid-State
Circuits, Vol.16, No.5, pp.479-487, 19
81). This technique can be similarly applied to the refresh failure as shown in FIG. However, the conventional defect relief technique has a drawback in that it requires a spare memory cell, which causes an increase in chip area. FIG. 16, FIG. 17, and FIG. 18 show examples of refresh failure relief techniques that do not use spare memory cells. This is to refresh only the memory cells that become defective in the refresh cycle TC3 in FIG. 15 in a cycle shorter than that, for example, TC4. Hereinafter, description will be made with reference to FIGS. FIG. 16 shows an example of the timing of the refresh signal RFSH at the time of holding information when this defect relief technique is used. Here, it is considered that the address 1 has a defective refresh. As shown in the figure, the address 1 is refreshed at the cycle TC4 from one centralized refresh to the next centralized refresh. This makes it possible to significantly reduce current consumption as compared with the case where all addresses are refreshed in a short cycle TC4. It is necessary to satisfy 4096 × TC1 ≦ TC4 ≦ TC3 during each refresh cycle. FIG. 17 shows the refresh address and the refresh signal R.
FIG. 18 shows an example of a circuit configuration for generating FSH, and its operation timing. In FIG. 17, OSC is an oscillator that generates a clock φ0, and DV1, DV4, and DV3 are clocks φ1, φ4, which have a cycle of an integral multiple of the clock φ0.
A frequency divider that generates φ3, 30 is a 13-bit synchronous counter, 31 is a refresh address generation circuit,
32 is a refresh signal (RFSH) generation circuit, I1 is an inverter, G1 is an AND gate, and G2 is an OR gate. The counter operates by the clock φ1, a high voltage (“1”) is applied to the Reset terminal, and counting starts from a state where all the counter outputs are reset to the low voltage (“0”). When output becomes 4097, output Q12
Becomes a high voltage (“1”), and counting is stopped. E in the figure
Is the counter enable signal. Since e is a high voltage ("1") during the operation of the counter, the outputs Q0 to Q11 of the counter are output to the outputs ar0 to ar11 of the refresh address generating circuit. After the counter is stopped, e becomes a low voltage (“0”), and defective addresses aS0 to aS11 are output to ar0 to ar11. Similarly, when the counter is operating, the clock φ1 is
Are output from the refresh signal generating circuit.
As a result, during the operation of the counter, concentrated refresh can be performed 4096 times in the cycle TC1, and only the defective address can be refreshed in the cycle TC4 after the counter is stopped. Although an example of relieving only one defective address has been described here, the present invention can be similarly applied to the case of relieving a plurality of defective addresses.

According to the embodiment described above, a dynamic memory that operates at high speed during standard operation and can hold information with a minimum required power during information holding, or a part of a dynamic memory. L included in
SI can be realized. Further, as for the fluctuation of the power supply voltage which has been a problem in the conventional dynamic memory, as shown in FIGS. 11 and 12, by operating the internal circuit at a low voltage such as 1.5 V, the external power supply voltage is changed. Even if it changes greatly, it can be operated stably.

In the embodiments described so far, the difference between the standard operating state and the information holding operating state is detected by the detecting means provided on the LSI chip, but the operating state may be controlled from outside the chip. Absent. FIG. 19 shows another embodiment of the present invention for externally controlling the transition to the information holding state. Among these, 4b is an information holding state signal inputted from the outside of the chip, 1B is an LSI chip having an information storing function or an information processing function like the LSI chip of FIG. 1, and PAD 3 is for receiving the information holding state signal. The bonding pads are shown respectively. The difference from the LSI chip of FIG. 1 is that it is not necessary to provide a detecting means and an information holding state signal generating means on the chip. This chip may be designed separately from the LSI chip of FIG. 1, or one chip may be designed and divided by switching of bonding or master slice of aluminum wiring.

FIG. 20 shows a case where the LSI chip of FIG. 19 is operated by using the battery B as a power source. The voltage value of the battery is distributed in a wide range such as 1 to 3.6 V depending on its type. Therefore, it is more convenient that the system can be controlled externally as compared with the method of detecting the transition to the information holding state by the voltage change. FIG. 21 shows the dependency of the internal power supply voltage VCL on the power supply voltage VCC. In this example, the standard power supply voltage range is set to 1 to 3.6 V and 1.5 to 3.
When 6V, VCL = 1.5V, and when 1 to 1.5V, VCL = VCC. By doing this, 1-3.
A change in the internal power supply voltage can be suppressed over a wide power supply voltage range of 6 V, and an LSI having almost no power supply voltage dependency of operating performance such as operating speed, current consumption, and operating margin can be realized. In addition, since it is possible to shift to the information holding state as needed without changing the power supply voltage, unnecessary power consumption can be suppressed according to the system state, and the operating time of battery-operated electronic devices can be extended. can do.

FIG. 22 shows a configuration example of an LSI in which the battery backup circuit shown in FIGS. 1 and 19 is incorporated in a chip and the power supply is switched on the chip. In this figure, 1C is an LSI chip having an information storage function or an information processing function, like the LSI chip of FIG. 1, 40 is a power supply switching circuit, 41 is a power supply drop detection circuit, SL, SB
Is a switching signal generated by the power drop detection circuit, SW40
Reference characters a and SW40b denote switches for switching the power source by switching signals SL and SB, and PAD4 denotes a bonding pad for applying the voltage of the battery. Thus, by switching the power supply on the chip, it is not necessary to mount a battery backup circuit on the system (board), the number of components can be reduced, and the manufacturing cost and the mounting density can be improved. Further, since the power supply switching circuit according to the characteristics of the LSI can be mounted, the user does not have to worry about the transient fluctuation of the power supply voltage which is a problem when switching the power supply, and it is possible to provide an easy-to-use chip. FIG. 23
Shows a specific configuration example of the power supply switching circuit 40. In the figure, 42 and 43 are differential amplifier circuits, and 44 and 45.
The outputs T19 and T20 are P-channel MOS-FETs corresponding to the switches for switching the power supply, and 46 is the output of the power supply switching circuit. The operation of this circuit will be described below.
Voltages γVCC and γVBT proportional to VCC and VBT are applied to the non-inverting input and inverting input of the differential amplifier circuit 42, respectively.
Similarly, voltages γVBT and γVCC which are proportional to VBT and VCC are applied to the non-inverting input and the inverting input of the differential amplifier circuit 43, respectively. Here, γ is a proportional constant that satisfies 0 ≦ γ ≦ 1, but it is desirable to set the voltage gain and output amplitude of the differential amplifier circuit to values that are sufficient. The proportional voltage can be obtained by resistance division. The outputs 44 and 45 of the differential amplifier circuits 42 and 43 are applied to the gates of T19 and T20. First, consider the case of VCC> VBT. At this time, output 44
Has a high voltage (VCC), and output 45 has a low voltage (~ γV).
CC-VT) is output, T19 becomes non-conductive, and T20 becomes conductive. Therefore, VCC is output as VINT. Similarly, when Vcc <VBT, a low voltage (~ γV) is applied to the output 44.
BT-VT) and the high voltage (VBT) are output to the output 45, respectively, and T19 becomes conductive and T20 becomes non-conductive. As a result, VBT is output as VINT. This circuit is VCC
Since the same operation is performed even when one of VBT and VBT is 0 V, the supplied voltage is directly output as the power supply voltage of the internal circuit even when only one of the power supplies is supplied.
FIG. 24 shows an example of VINT dependency of VINT for the case of VBT = 1.5V. When VCC> 1.5V, VINT
= Vcc, Vcc <1.5V, VINT = 1.5V is obtained. As shown in the figure, VINT continuously changes, and no kink that adversely affects the operation of the LSI occurs. As shown in the above examples,
Since the power supply switching circuit can be configured with a relatively simple circuit, even if it is mounted on one LSI, the increase in chip area is slight. Although an example in which the MOS-FET is used is shown here, the present invention can be similarly realized by using another, for example, a bipolar transistor.

In the above embodiments, the basic concept of the LSI chip in which the main LSI circuit block operates at 1.5 V or less has been described. In the following, a dynamic memory will be mainly taken up and a more detailed embodiment will be described. Generally, it has been considered that the low voltage operation of the dynamic memory is difficult as compared with other logic LSIs and static memories. The first reason is that the amount of signal charges that can be accumulated by the accumulated voltage and the accumulated capacitance is reduced by lowering the voltage, and the signal-to-noise ratio is reduced. Therefore, noise margin is generated against noise charge generated by irradiation of alpha rays emitted from a small amount of radioactive material contained in the package or metal wiring, and noise charge due to thermal or non-thermal leak current flowing into the memory cell. It has been considered difficult to secure a (margin). These problems can be solved by either of the following two methods. (1) Use a circuit that can obtain a memory cell storage signal voltage (for example, low voltage = 0V, high voltage = 3V) that is comparable to the conventional one, even at a low power supply voltage (for example, 1.5V). In this case, the storage capacity of the memory cell has a value similar to the conventional one (for example, 30 to 40 fF (femto farad)).
Good. (2) Instead of keeping the circuit system as it is, the storage capacity of the memory cell is increased almost in inverse proportion to the power supply voltage. For example, when the power supply voltage is 1.5 V, the storage capacity of the memory cell is 60 to 80 fF. Regarding the method (1) among the above methods, a method of storing a signal amplitude larger than the amplitude of the data line in the memory cell by driving the plate of the memory cell in addition to the word line and the data line is disclosed in Japanese Patent Application No. 63
-148104 and Japanese Patent Application No. 63-222317. With regard to (2), the technologies for dramatically increasing the storage capacity compared to the conventional technology are Japanese Patent Application No. 60-267113, Symposium on Bryer S.I. Technology, Digest of Technical Papers, No. 29-.
Page 30 (1988) (1988 Symposium on VLSI
Technology, Digest of Technical Papers, pp.29-
30, 1988). By applying these techniques, it is possible to secure the accumulated signal charge necessary for stable operation. The second problem for low voltage operation is to simultaneously realize high speed operation and low current consumption. A third problem is to realize an element or a circuit that enables integration of a low voltage operating circuit and a high voltage operating circuit on the same chip. The third problem becomes particularly problematic when the ratio of the voltage values of the high-voltage power supply and the low-voltage power supply is double or more. An example of solving the third problem by forming two types of elements for high voltage and low voltage on one chip is Japanese Patent Application No. Sho 56-56.
-57143. According to this technique, the circuit can be configured with the optimum elements for the low-voltage power supply and the high-voltage power supply, but there is a drawback that the manufacturing process of the LSI becomes complicated. In the following embodiments, means for overcoming the second problem and operating even when the minimum power supply voltage is 1 V, and a method for solving the third problem without complicating the manufacturing process will be described. With these, the operating power supply voltage of the dynamic memory can be lowered to about 1 to 1.5 V, and high integration, high speed, and low power consumption of the dynamic memory or an LSI chip including the dynamic memory as a part thereof can be realized at the same time. it can. In addition, the specifications required in the battery operation or the battery backup operation can be satisfied.

First, a means for overcoming the second problem will be described. The complementary MOS-FET (Complem
Although an example of using entary MOS = CMOS) is shown, a bipolar transistor, a junction FET, or an element other than silicon may be used as long as the same effect can be obtained. FIG. 25A shows the relationship between the N-channel MOS-FET gate-source voltage VGS and the drain current ID. This relationship is divided into (i) a square root region where the square root of ID is approximately proportional to VGS, and (ii) a subthreshold region where ID is proportional to the exponential function of VGS in a region where VGS is smaller than that. In the figure, VT1 is a so-called gate threshold voltage at which a drain current starts to flow when the region (ii) is ignored and the current-voltage characteristic can be approximated by a square root. Further, VT0 is another definition of the gate threshold voltage at which the drain current can be regarded as almost zero in terms of circuit operation. Gate width is 1
When 0 micron is set, the drain current when VGS = VT0 is about 10 nA, and the drain current when VGS = VT1 is about 1 μA. The difference between VT1 and VT0 is about 0.2V
(VT1> VT0). VGS-VT1 is related to the current drive capability of the actual MOS-FET, and VT0 is related to the static current in the standby state. In the following example, the threshold voltage of the element used in the main circuit of the LSI is set to VT1 = 0.3V (thus VT0 is about 0.1V). This allows the MOS-FET to operate at half the power supply voltage (eg 0.5V).
It is possible to operate a sense amplifier or a differential amplifier circuit that needs to be turned on, and it is possible to operate all circuits up to a power supply voltage = 1V. Further, this makes it possible to suppress the standby current of the entire chip to about 10 μA.
Also, even if the threshold voltage varies by about ± 0.1V due to variations in various manufacturing processes, circuit operation is realized at a power supply voltage of 1V, and the standby current of the entire chip is reduced to 10
It can be suppressed to 0 μA or less. Power supply voltage = 1V
However, the channel length =
It was set to 0.3 micron. Figure 25 (b) shows two N channels
It shows the channel length dependence of the gate threshold voltage VT1 for MOS-FETs (Case I, Case II). Where Case
I is a general condition of a conventional dynamic memory (hereinafter abbreviated as DRAM) when applying a substrate bias voltage, Ca
seII represents the characteristics of the element used in the present invention, which corresponds to the condition that the substrate bias voltage is not applied. Case I is V
When BS = −1V, in Case II, the gate threshold voltage VT1 is set to 0.3V when VBS = 0V. The Case II element has the following three problems. (1) The fluctuation of the gate threshold voltage with respect to the fluctuation of the channel length is large, and the controllability is inferior to Case I, so that it is difficult to shorten the channel. (2) The substrate bias voltage is generated by the substrate bias voltage generating circuit provided on the chip, and its voltage value varies due to manufacturing variations, and its value greatly fluctuates with time depending on the number of operating circuits. Since the gate threshold voltage is largely modulated by the substrate bias voltage, the specifications of the gate threshold voltage required for low voltage operation cannot be accurately met. (3) Since the substrate bias voltage is 0 V when the power is turned on, the gate threshold voltage is lower than 0.3 V, for example, 0 V due to the substrate effect. At the same time, since the substrate is in a substantially floating state, the substrate voltage transiently rises due to capacitive coupling with VCC, and the gate threshold voltage becomes negative. Therefore, the MOS-FET of the peripheral circuit becomes conductive, and a large transient current flows. According to the present invention, since the substrate voltage is fixed at VSS = 0V, it is possible to provide an LSI chip having excellent controllability of the gate threshold voltage and a small transient current when the power is turned on. Furthermore, since the fluctuation of the substrate voltage during the circuit operation can be made almost zero, the capacitive coupling noise from the substrate voltage can be significantly reduced. It should be noted that the substrate bias voltage may be applied as in the conventional case by using another means for setting the threshold voltage with high accuracy.

FIG. 26 shows the gate oxide film thickness tox, the electrical channel length (effective channel length) Leff, the gate threshold voltage VT1, of the element used in the main circuit of the dynamic memory which operates even at the minimum power supply voltage of 1V. VT0 is shown. Here, the values shown in parentheses indicate the range of fluctuation due to manufacturing variations and the like.

FIG. 27 shows a part of the sectional structure of the dynamic memory chip of the present invention. There are three reasons for applying a negative voltage to the substrate in the conventional dynamic memory. (1) When a negative voltage due to ringing or the like is applied to the input or output from the outside, electrons which are minority carriers are injected into the substrate. The electrons diffuse in the substrate, and some of them reach the charge storage portion of the memory cell, which deteriorates the refresh characteristic. The injection of minority carriers into the substrate is prevented. (2) By applying a negative voltage to the substrate,
-Reduce the load capacitance by reducing the junction capacitance between the diffusion layer and the p-substrate. As a result, high-speed operation and low power consumption of the circuit are achieved. (3) By applying a negative voltage to the substrate, the depletion layer under the channel spreads, and the potential of the channel portion is less likely to be modulated by the substrate voltage. This allows
The gate threshold voltage is less likely to be affected by changes in the substrate voltage. In other words, the substrate effect coefficient of the gate threshold voltage becomes small, which is convenient for the operation of some circuits of the dynamic memory. Of these, regarding (3), the effect of applying the substrate voltage is fading along with the tendency of the CMOS-LSI to have a double well structure. Therefore, solving (1) and (2)
It becomes important. In a CMOS-LSI, a substrate structure capable of applying a plurality of substrate voltages is disclosed in JP-A-62-1199.
It is shown at 58. By combining this structure with the low-voltage LSI according to the present invention, the above-mentioned object is achieved,
It is possible to configure a low-voltage LSI having excellent noise resistance, high speed, and low power consumption. Examples will be described below with reference to sectional views of the substrate structure of the present invention. In FIG. 27, P
The shape of the silicon substrate has an impurity concentration of about 1 × 10 15 cm +3. In this substrate, two types of N wells (N1, N2) and one type of P well formed by two different steps are formed. The impurity concentration of each well is, for example, N2
Well 1 × 10 16 cm + 3, N 1 well and P well 5 ×
Although it is about 1016 cm + 3, these values may be changed according to the dimensions of the element. In the figure, 50 is a thick oxide film (about 500 n thick) for electrical isolation between active regions.
m), 51 is a first polysilicon electrode for forming a storage capacitor, 52 is a second polysilicon electrode that serves as a gate electrode of a MOS-FET, and 53 and 54 are masks for these thick oxide films and polysilicon electrodes. N-type impurity diffusion layer formed in a self-aligned manner (impurity concentration is about 2 × 10 20 cm + 3), 5
Reference numerals 5, 56 and 57 respectively denote P-type impurity diffusion layers (impurity concentration of about 2 × 10 20 cm + 3) formed in the same manner. The P substrate is grounded (VSS) by the diffusion layer 56.
It is fixed to. The storage capacity of the memory cell and the selection transistors TN3 and TN4 are formed in a P well electrically isolated from the substrate by the N2 well. Diffusion layer 57 in P well
Thus, the second substrate potential VBP2 is applied. In addition, the N2 well and the diffusion layer 54 which are in electrical contact with the N2 well.
Thus, the second N well potential VBN2 is applied. Also VBS
N-channel MOS-FET TN1 of peripheral circuit operated at = 0V
Is formed in the P substrate, and the P channel MOS-FET TP1 is formed in the N1 well. In addition, N-channel MO of peripheral circuits
The S-FET TN2 is formed in a P well that is electrically separated from the P substrate, separately from the memory cell array. By doing so, when there is a possibility that a negative voltage such as in an input / output circuit or a voltage higher than the voltage of the N well is input from the outside, an independent substrate voltage corresponding to the amount of overshoot or undershoot is applied. Can be applied. In this way, electrically separating the P well in which the memory cell array is formed from the P substrate has the following effects. (1) By biasing the P well of the memory cell array to a negative potential, the data line capacitance can be reduced and the signal-to-noise ratio can be improved. (2) The N2 well covering the memory cell array serves as a barrier for minority carriers that diffuse in the substrate. As a result, noise charge can be suppressed from being collected in the storage capacitor section, and the noise resistance is improved. As described above, by using the substrate structure as shown in FIG. 27, stable operation of the memory cell array and speedup and power consumption reduction of peripheral circuits can be realized at the same time. In the above description, the case where the P substrate is used has been described, but the same effect can be expected even when the N substrate is used. However, in the battery operation and the battery backup operation targeted by the present invention, it is necessary to consider the use in an environment where the power supply voltage fluctuates greatly.
When the N substrate is used, the maximum voltage VCC of the system is applied to the N substrate. Therefore, when the power supply voltage fluctuates greatly, the potential of the N substrate also fluctuates, and noise is induced in each part of the circuit due to capacitive coupling with the N substrate. For these reasons, the structure using the P substrate shown in FIG. 27 is suitable for the purpose of the present invention.

28 to 30 show examples of an LSI circuit having an information holding function capable of further lowering the voltage according to the present invention. FIG. 28 is an example of the peripheral circuit.
In the figure, 60 is a circuit block that operates at the power supply voltage VCL1, 6
Reference numeral 1 denotes a circuit block which operates at the power supply voltage VCL2, VBP1 denotes the substrate bias voltage of the N-channel MOS-FET of the circuit block 61, and VBN1 denotes the substrate bias voltage of the P-channel MOS-FET of the circuit block 61. The circuit block 60 is a portion that does not need to be operated when holding information, and VCL1 = 0V when holding information. The circuit block 61 is a portion that needs to be operated even when holding information, and the value of VCL2 is constant regardless of the operating state. In order to operate the circuit up to a power supply voltage of about 0.5 V, the threshold voltage VT1 is set to 0
It is necessary to set it to about 0.1V. The threshold voltage
Considering including the sign, the threshold voltage VT1 is 0 to 0.1.
About V is the gate threshold of N-channel MOS-FET
Voltage, gate threshold voltage of P-channel MOS-FET
Then, it becomes about -0.1 to 0V. At this time, the circuit does not operate and the N-channel MOS-FET or P-channel of the CMOS circuit is
When the gate-source voltage of either one of the channel MOS-FET is 0V, the gate width is set to 10 microns and one
The MOS-FET has a current of about 1 μA (one MOS-FET gates
When converted to a width of 1 micron, about 0.1 μA) flows, and the entire chip has a large current value of 10 mA. That is, in this state, it is a CMOS circuit.
Even if the gate-source voltage is set to 0V, the circuit
Drain current that can be regarded as almost zero in operation (1 MOS-FE
Approximately 1 nA when converted per 1 micron of gate width with T
Static current that is greater than the degree). It is necessary to reduce this static current in order to reduce current consumption when holding information. Generally, the operation speed may be slower at the time of holding information than at the time of standard operation. Therefore, in this example, by controlling the substrate voltage, the MOS-FE for holding information is
The threshold voltage of T is changed in the direction in which it is more difficult to conduct than in the standard operation (the threshold voltage of the N-channel MOS-FET is high and the threshold voltage of the P-channel MOS-FET is low). FIG. 29 is a configuration example of the generation circuit of the substrate voltage VBP1 of the N channel MOS-FET, and FIG. 30 is its operation timing chart.
Although a case of VCL2 = 1.5V is described here for convenience, it is particularly effective when the power source voltage is as low as about 0.5 to 1V as described above. In FIG. 29, 62
Is a ring oscillator composed of the inverters I2 to I3 and the NAND gate G3, 63 is a charge pump circuit composed of two diode-connected MOS-FETs T40 and T41 and a capacitor CB1, and T42 and T43 are N-channel MOS-FET T4.
Reference numerals 4 indicate P-channel MOS-FETs, respectively. During standard operation, that is, when PD is at a low voltage (“0”), the ring oscillator and the charge pump circuit do not operate. MO at the same time
S-FET T44 becomes conductive and node N1 is at high voltage (“1”)
Therefore, the MOS-FET T42 becomes conductive and VBP1 becomes the ground potential. On the other hand, when the information is held, that is, when PD is at a high voltage ("1"), the MOS-FET T43 becomes conductive and the node N1 has the same potential as VBP1, so the MOS-FET T42 is cut off. At the same time, the ring oscillator and the charge pump circuit operate, and a negative voltage is output to VBP1. The substrate bias voltage is always applied to the memory cell array. As described above, by controlling the substrate bias voltage when operating with a low-voltage power supply of 1 V or less, it is possible to realize high speed during standard operation and low power consumption during information retention. Although not described here, the present invention can be similarly applied to a circuit for generating VBN1.

In the following description, a specific circuit configuration of the low voltage operation dynamic memory using the above-mentioned substrate structure will be described. FIG. 31 shows the circuit configuration of the dynamic memory. In the figure, MA1 and MA2 are memory cell arrays, DA1 is a dummy cell array, W0 to Wm are word lines,
D0, D0-, Dn, Dn- are data lines, DW0, DW1 are dummy word lines, XD is a word line selection circuit, DWD is a dummy word line selection circuit, and T52 to T55 control the connection between the left mat MA1 and the sense amplifier. Left mat select transistor, SHRL is the select signal, T56 to T59 are right mat M
A right mat select transistor for controlling the connection between A2 and the sense amplifier, SHRR is its select signal, PR0 to PRn are precharge circuits that set the voltage of the data line to the potential P when not selected, φP- is a precharge signal, and SA0 to SAn is a sense amplifier that amplifies a minute signal voltage on the data line, CS
N and CSP are common source drive signals of the sense amplifier, C
D is a common source drive circuit, YG0 to YGn are Y gates for connecting data lines and common I / O lines, YDEC is a Y address selection circuit, Y0 to Yn are Y selection signals, and DiB is a common I according to input data. A data input buffer that drives the / O line, and DoB is a data output buffer that amplifies and outputs the signal current of the common I / O line. As described above, the storage capacitance CS2 of the memory cell is about 60 to 80 fF, and the data line capacitance is about 250 to 300 fF. As a result, the read signal voltage becomes about 150 mV when the amplitude of the data line is set to 1.5 V, and a signal voltage sufficient for the operation of the sense amplifier can be obtained.

FIG. 32 shows the voltage waveform of each part at the time of data reading when the power supply voltage is 1.5V. In addition,
In the following explanation, in the case of the read operation from the memory cell,
Also, consider the case where the word line W0 is selected. The precharge voltage of the data line and the voltage of the counter electrode (plate) of the cell storage capacitance are set to 0.75V which is half the power supply voltage.
As a result, (1) capacitive coupling noise generated at the time of charging / discharging or precharging the data line is minimized,
(2) The storage capacitor is increased by minimizing the voltage applied to the insulating film forming the storage capacitor and making it thinner. In order to write a high voltage (1.5 V) to the memory cell, the word line W0 and the left mat select signal SHR
Applying 2.2V to L, transistors T50 and T5
2 is working in the unsaturated region. M of Y gate
The common I / O line is set to 1.2V so that the OS-FET operates in the saturation region. A current detection type amplifier as described in Japanese Patent Application No. 63-141703 is suitable as an amplifier for a signal of a common I / O line that operates even at such a low power supply voltage. By using this type of amplifier, (1) the voltage level of the common I / O line can be increased to near the power supply voltage, and (2) the signal amplitude of the common I / O line can be reduced (for example, 50 mV). , Y
It is possible to increase the operation margin when applying the selection signal Y0 and reading the signal. In addition, as for writing to the memory, the I / O line is connected to the data input buffer DiB as in the conventional case.
It can be done by driving with. Since it is not necessary to read the information to the outside when the information is held, the Y selection signal Y0 remains at the low voltage (“0”) as indicated by the broken line in the figure. Further, it is not necessary to operate the Y address selection circuit, the data input buffer, the data output buffer and the like.
Further, the drive capability of the common source drive circuit of the sense amplifier is reduced, and the time rate of change of the data line voltage is reduced. As a result, the value of the peak current accompanying the charging / discharging of the data line is reduced when the information is held. By performing such control, even when a power source having a high internal impedance such as a battery is used, it is possible to prevent the LSI from malfunctioning due to a transient drop in the power source voltage. Below,
The following circuit important for realizing such a low voltage dynamic memory will be described.

(1) 1/2 VCL generation circuit.

(2) Word line drive circuit.

(3) Common source drive circuit.

FIG. 33A shows the circuit configuration of the 1/2 VCL generation circuit. In the figure, T60 and T62 are N-channel MOS-
FETs, T61 and T63 are P-channel MOS-FETs, and R20 and R21 are resistors for setting a bias current. The ratio of the resistance values is chosen so that the voltage at node N4 and node P is approximately half of VCL2. The capacitors CD1 to CD4 are speed-up capacitors provided so as to follow the fluctuation of the power supply voltage. CD1 ≈ CD between these values
2, CD3≈CD4 is established. The substrate and the source of each transistor are connected to prevent the threshold voltage from increasing due to the substrate bias effect. The absolute value of the threshold voltage VT1 of each transistor at this time is about 0.3V. If the substrate is connected not to the source but to the highest voltage of the system, the absolute value of the threshold voltage VT1 becomes larger than 0.5V due to the substrate bias effect, so the power supply voltage VCL2 = 1V.
Will stop working. Thus, in a circuit that operates at a low voltage, the method of applying the substrate voltage defines the minimum power supply voltage. The substrate structure shown in FIG. 27 can be used to easily connect the substrate and the source. FIG. 33 (b) shows an N-channel MOS-FET T60,
The cross-section figure of T62 is shown. Reference numeral 65 is an n-diffusion layer for applying an N2 well potential, 66 is a p-diffusion layer for applying a P well potential, and 67 and 68 are N-channel MOS-Fs.
It is an n-diffusion layer that serves as the source and drain of ET. A p-diffusion layer 66 that gives the substrate voltage of the MOS-FET by external wiring
Is connected to the source. The maximum voltage of the system, here VCL2, is applied to the N2 well. As shown in this example, since the MOS-FET can be formed in the P-well electrically isolated from the substrate, it is suitable for low-voltage operation without being affected by the substrate effect of the threshold voltage. A circuit can be constructed. Note that the present embodiment is not limited to the example shown here, and the present embodiment can be similarly applied to a circuit for operating a source such as a differential amplifier circuit at a voltage higher than the ground potential.

FIG. 34 (a) shows the circuit configuration of the word line drive circuit, and FIG. 34 (b) shows its operation timing. In the figure, T82 is a memory cell transistor, CS3 is a storage capacity,
T80 and T81 are N-channel MOS-FETs. This circuit is generally called a self boosting circuit. A selection signal of the word line selection circuit is input to S. This voltage level is a high voltage (for example, 1.5 V) when selected and a low voltage (0 V) when not selected. Therefore, node N7
Is applied with VCL-VT0 (VT0 is the threshold voltage of T81), and 0V is applied when it is not selected. After the selection signal is fixed, a pulse voltage (for example, 2.2 V) higher than the power supply voltage is applied to X so that the memory cell transistor can be sufficiently turned on. The MOS-FET T80 does not conduct when not selected, but due to the coupling of the gate capacitance of T80 when selected
The node N7 is boosted to a high voltage. In order to directly output the pulse voltage applied to X to the word line, the voltage of the node N7 is higher than the pulse voltage applied to X, for example, 2.2 + VT1 (VT1
Needs to be boosted to the threshold voltage of T80). When the substrate potential of the MOS-FET is set to the ground potential, the threshold voltage rises due to the substrate effect. Therefore, it is difficult to obtain a predetermined amplitude on the word line especially with a low voltage power supply whose VCL is 1.5 V or less. Here, in order to make the threshold voltage of the MOS-FET sufficiently low, the substrate potential is connected to the drain of the signal drive side (select signal S or pulse voltage X in this example) (here, for convenience, The drain is defined as the terminal to which the signal drive is applied). A cross-sectional structure diagram of this MOS-FET,
The equivalent circuits are shown in FIGS. 35 (a) and 35 (b), respectively. The cross-sectional structure of the element is exactly the same as that shown in FIG. 33 (b), but the connection is different. Since the potential of the P well matches the potential of the drain, it is equivalent to connecting a bipolar transistor having the drain as the collector and the base and the source as the emitter, as shown on the left side of FIG. 35 (b). . In reality, since the collector and the base are connected, the bipolar transistor operates as a diode and is represented by an equivalent circuit as shown on the right side of FIG. 35 (b). Therefore, when the drain is higher than the source voltage, the MOS-FET whose substrate voltage is positively biased with respect to the source and the diode DL are connected in parallel. Conversely, when the drain is lower than the source voltage, the diode DL is connected. Is reverse-biased and cut off, and only the MOS-FET connected to the drain on the low voltage side of the substrate operates. Therefore, the threshold voltage in the former case becomes lower than that in the latter case, and the MOS-FET becomes easy to conduct. At the same time, when the voltage difference between the drain and source is 0.7 V or more, the diode conducts, so in the former case,
Further, the current easily flows. Therefore, in FIG. 34 (b), the MOS-FETs T80 and T8 when driving the word line are
The threshold voltage of 1 can be set to a low value, and the drive signal X can be directly output to the word line even at a low power supply voltage. Such an asymmetrical characteristic is particularly effective when applied to a self-boosting circuit or the like, but is also applied to other rectifying circuits used for a charge pump circuit of a pass gate or a substrate bias voltage generating circuit, for example.
Similarly, operation with low voltage power supplies is improved.

FIGS. 36 (a) and 36 (b) are diagrams showing an example of the configuration of the common source drive circuit. Same figure
In (a), T85 and T86 are N driving the common source.
The channel MOS-FET and G5 are AND gates. At the time of standard operation, the signal PD becomes high voltage (“1”), and both T85 and T86 become conductive in synchronization with the input of the common source drive signal φCS. On the other hand, at the time of holding information, PD_ becomes a low voltage (“0”), and only T85 becomes conductive with respect to the input of φCS. Therefore, by appropriately selecting the conductances of T85 and T86, it is possible to give priority to the operating speed during the standard operation and reduce the peak current at the time of holding the information, at the expense of the operating speed. In FIG. 36 (b),
T90 is an N-channel MOS-FET that drives a common source, T9
1, T93, T94 is N channel MOS-FET, T92 is P channel
MOS-FET, G6 is NAND gate, G7 is AND gate,
R25 represents a resistor for supplying a bias current to T94. In the standard operation, the signal PD becomes a low voltage (“0”) and T93 is cut off. In synchronization with the input of φCS, the voltage of the node N8 becomes VCL and drives T90. When the information is held, the signal PD becomes a high voltage ("1") and T92 is cut off. T93 is turned on in synchronization with the input of φCS, and the voltage of the node N8 matches the gate voltage of T94. At this time, since the current mirror circuit is composed of T90 and T94, the drive current of the common source is (VCL-VT1).
It becomes a value proportional to / R25. Here, the proportional coefficient is determined by the ratio of the channel conductances of T90 and T94. By using such a drive circuit, it is driven with a constant controlled current when holding information, so stable operation is realized without causing a transient drop in the power supply voltage due to the internal impedance of the battery. can do. In addition to the current mirror circuit shown here, other means may be used as long as the drive current can be controlled at the time of holding information.

With the substrate structure, element constants, and circuit configuration as described in the above embodiments, it is possible to realize a dynamic memory that guarantees operation at the minimum power supply voltage = 1V. Further, in addition to the circuit configuration of the I / O line and the Y gate shown in FIG. 31, a common I / O line is separately provided for reading and writing to further increase the operating margin for reading and writing. A method for improving is Japanese Patent Laid-Open No. Sho 6
1-142594 and JP-A-61-170992. By applying this method, it is possible to realize a memory circuit that operates stably without being affected by element variations even with a power supply voltage as low as about 1V.

The configuration example of the main LSI circuit block operating at a low internal power supply voltage of 1.5 V or less has been described above by taking the memory as an example. In addition to this, in order to realize the LSI chip as shown in FIG. 1, it is essential to realize a circuit that operates with a high external power supply voltage (for example, 3 to 5 V). Such circuits include at least the following:
(1) Reference voltage generation circuit, (2) voltage conversion (drop) circuit, (3) input circuit, (4) output circuit.

As shown in FIG. 26, in the main LSI circuit block which operates at a low internal power supply voltage of 1.5 V or less, the most advanced processing technology (for example, gate length 0.3) is provided for the purpose of ensuring the operation speed. Element (corresponding to micron or less) is used. In such a fine element, the gate breakdown voltage and drain breakdown voltage are lowered, and a high external power supply voltage (for example, 3 to 5) is generated.
V) becomes difficult to operate. In this regard, for example, the IDM Technical Digest,
386 to 389 (1988), (IEDM Te
chnical Digest, pp.386-389, 1988). 1 considering long-term reliability
The voltage that can be applied to the 0 nm gate oxide film is about 4V. Therefore, it can be applied to the gate oxide film. The maximum electric field strength Emax is about 4 MV / cm. Approximately Em
It can be considered that the value of ax does not depend on the gate oxide film thickness and does not substantially change (actually, when the gate oxide film is thin, it tends to be slightly larger). When this value is applied to the device shown in FIG. 26 (gate oxide film thickness tox = 6.5 nm),
The maximum voltage that can be applied to the gate is 2.7V. Therefore, this device is connected to a high external power supply voltage (for example, 3 to 5V).
Can not be operated with. The following two can be considered as means for solving this. (1) As mentioned in the above description, in addition to the element used at the internal power supply voltage, the element having a thicker gate oxide film which operates at the external power supply voltage is integrated on the same chip. (2) Consists of only elements used at the internal power supply voltage. At this time, a circuit is devised so that the external power supply voltage is not directly applied to the element. The method of (1) is Japanese Patent Application Sho 56
-57143. However, this method increases the manufacturing cost because the LSI manufacturing process is complicated. In addition, since many steps are inserted during the formation of the gate oxide film, which is the most important factor for forming the device, there is a problem that the probability of introducing impurities and defects becomes high and the reliability of the device is lowered. An example of realizing a circuit that operates with a high external power supply voltage by the method (2) will be described below. In the following examples, complementary MOS-FETs (CMOS) are used. However, other bipolar transistors, junction transistors, or a combination of these and MOS-FETs may be used. In that case, the same applies to the case of using a semiconductor material such as gallium arsenide other than silicon.

FIG. 37 (a) shows a configuration example of the inverter circuit according to the present invention. In the figure, T100 and T102 are N-channel MOS-FETs, T101 and T103 are P-channel MOS-FETs, in1,
in2 is the first and second in-phase input terminals, out1 and out, respectively
Reference numeral 2 is the first and second in-phase output terminals, Out is the third output terminal, and Vn and Vp are the bias power supply voltages for the N-channel and P-channel MOS-FETs, respectively. Vn and Vp have an external power supply voltage dependency as shown in FIG. 37 (b), for example. In this example, Vn when Vcc ≧ 2V
= 2V and Vp = VCC-2V. This allows the output terminal o
Since the voltage of ut1 is Vn−VTN at the maximum, the maximum voltage applied to the gate oxide film of the transistor T100 is Vn−VTN.
Limited to VTN. Similarly, the maximum voltage applied to the gate oxide film of the transistor T101 is VCC-Vp- | VTP |
Limited to. Here, VTN is the gate threshold voltage of T102 and VTP is the gate threshold voltage of T103. Two output terminals out1, out2
Signal levels of 0 to Vn-VTN, VCC-Vp- |
VTP | to Vcc, and these become the input of the next inverter in
Drive 1 and in 2 respectively. Further, 0 to Vcc, that is, full amplitude can be output to the third output Out.

The voltage of each node and the maximum voltage applied to the gate oxide film of each transistor when the inverter array is formed by this inverter are as shown in FIG. 38 (b). With this circuit configuration, for example, Vn = Vp = 1
In the case of / 2Vcc, the maximum voltage applied to the gate oxide film is 1 / 2Vcc and the maximum voltage applied between the drain and the source is 1 / V in any transistor.
Limited to 2Vcc + VTN or 1 / 2Vcc + | VTP |. Actually, from the viewpoint of ensuring the operating margin of the inverter, Vn and Vcc− at low power supply voltage
Vp is preferably constant. Further, it is desirable that the channel conductances of T102 and T103 be larger than the channel conductances of T100 and T101, respectively, so that a large voltage is not applied between the drain and the source even when the output voltage changes transiently during switching. .

As described above, with this configuration, it is possible to realize a circuit that operates up to a power supply voltage that is about twice the maximum voltage of the device without degrading the device characteristics. In addition,
In the example shown in FIG. 37 (a), the substrate potential of the N-channel MOS-FET is the lowest voltage of the system, that is, VSS, and P-channel MOS-FET.
The substrate potential of the FET is connected to the highest voltage of the system, that is, Vcc, but if the substrate of each transistor is connected to the source using the above-mentioned substrate structure, the fluctuation of the threshold voltage due to the substrate effect is suppressed. Therefore, a circuit which operates with a lower power supply voltage can be realized. Therefore, by applying the present invention, it is possible to provide an LSI that operates stably even with only a MOS-FET using a thin oxide film of about 6.5 nm or with a power supply voltage of 5V.

FIG. 39 (a) shows an inverter array (inverter chain) in which a plurality of inverters are connected in which the substrate and the source are connected and the operating characteristics are improved at a low power supply voltage.
It is a configuration example of. Like a conventional CMOS inverter array,
It is possible to connect them as they are without placing a level conversion circuit between the inverters. As a result, it is possible to configure a driver circuit that requires a large load driving capability, such as an output buffer. If the number of stages n is an even number, the input and output waveforms are as shown in FIG. 39 (b). In this example, Vcc = 4V, Vn = 2V,
Vp = 2V. In this circuit, the amplitude of the output signal for driving the next-stage inverter is almost constant (1.7 V) regardless of the power supply voltage. For this reason, the drive capability of the MOS-FET that charges and discharges the gate capacitance of the next-stage inverter does not depend on the power supply voltage, and the delay time from the input to the output (t
1-t0) is almost constant regardless of the power supply voltage. Therefore, for example, the access time of the memory LSI is 1.5 to 5
Since there is almost no change even in a wide power supply voltage range of V, it is possible to provide an LSI chip that is convenient in configuring the system.

FIGS. 40 (a) and 40 (b) show a configuration example of the bias voltage Vn, Vp generation circuit shown in FIG. 37 (b). In the figure, T114 to T117 whose channel portions are indicated by thick lines are N-channel MOS-FETs having a high threshold voltage, T112 and T113 are MOS-FETs for supplying a bias current, and 72 is a gate voltage of T112 and T113. The bias generators CN1 and CP1 for setting the optimum bias current are decoupling capacitors.
The value of the bias current is set by resistors R30 and the ratio of the channel conductances of T113 and T112. The N-channel MOS-FET having a high threshold voltage is formed by forming a gate oxide film and then introducing P-type impurities by ion implantation using a resist as a mask. In this example, the threshold voltage value is 1V. Further, by using the substrate structure shown above and connecting the substrate to the source, the fluctuation of the threshold voltage due to the substrate effect is eliminated and the setting accuracy is improved. In addition, MOS-FET T112, T
113 operates as a current source. With this configuration, when the power supply voltage Vcc is 2 V or higher, the value of Vn is approximately twice the high threshold voltage (about 2 V), and when Vcc is 2 V or lower, it is almost equal to the power supply voltage Vcc. Similarly,
When the power supply voltage Vcc is 2V or higher, the value of Vp is approximately Vcc-2V, and when Vcc is 2V or lower, it is almost 0V.
become.

FIG. 40B shows another example of the structure of the bias voltage generating circuit. Although only the Vn generating circuit is shown here, the Vp generating circuit can be similarly configured. In the figure, T123 is an N-channel MOS-FET having a high threshold voltage, T121 is a P-channel MOS-FET which supplies a bias current, and T120 and R.
Reference numeral 31 is a bias generation circuit for generating a gate voltage of T121 and setting an optimum bias current, CN1 is a decoupling capacitor, and R32 and R33 are resistors. When the threshold voltage value of T123 is VTE, the value of Vn is VTE × (R32 + R33) /
It becomes R33. Therefore, the value of Vn can be set to an arbitrary value equal to or higher than VTE by changing the ratio of R32 and R33. By these, a bias voltage having the characteristic of FIG. 37 (b) can be generated. Note that any of a channel of a MOS-FET, an impurity diffusion layer, a wiring layer of polysilicon, or the like may be used for the resistor shown in this example.

In a normal LSI, after the final manufacturing process, a voltage higher than the voltage used in normal operation is intentionally applied to each transistor in the circuit, and a transistor which is liable to cause a failure due to a defective gate oxide film or the like. The aging test is conducted to find the initial value, and the reliability is guaranteed. FIG. 41 (a) is a diagram showing an embodiment of how to apply the bias voltages Vn and Vp suitable for this aging test.
In this example, Vn = Vp = 1 at a power supply voltage (4V in this example) higher than where the magnitude relationship between Vn and Vp is reversed.
/ 2 VCC. By doing so, Vn and Vp are increased in proportion to the power supply voltage during the aging test. Further, by making the value half the power supply voltage, for example, the maximum voltage is made substantially equal among the transistors shown in FIG. 38 (a), and stress is prevented from concentrating on some transistors. There is.

FIG. 41 (b) shows an embodiment of the structure of the circuit for generating the bias voltages Vn and Vp. In the figure, 72 is a maximum value output circuit that compares the voltages of two nodes N9 and N10 and outputs the maximum value, T140 and T141 are N-channel MOS-FETs having a high threshold voltage, and R36 is a MOS-FET. R38 and R39 are resistors for supplying bias current to R3 and R39 to divide the power supply voltage to obtain 1/2 VCC, and R36≈
It is R39. The maximum value output circuit is a differential amplifier circuit A10.
And A11, P-channel MOS-FET T142, T143, node N1
The resistor R37 is provided to prevent the impedance of 1 to the ground side from becoming infinite. The operation of the maximum value output circuit is described in, for example, IEE Journal of Solid State Circuits, Vol. 23, No. 5, pp. 1128-1132 (19).
88) (IEEE Jounal of Solid-State Circuits,
Vol.23, No.5, pp.1128-1132, October
1988). A substantially constant voltage (2V in this example) is input to the node N9 regardless of the power supply voltage. On the other hand, half the power supply voltage is input to the node N10. Therefore, when the power supply voltage is 4V or less, 2V which is the maximum value of these two voltages is output to the node N11, and when the power supply voltage is 4V or more, 1 / 2Vcc is output. The generation circuit of the bias voltage Vp can be similarly configured. In this example, the case where the voltage value of the node N9 is 2 V is considered, but it may be set to an appropriate value in accordance with the maximum applicable voltage of the gate oxide film.

Japanese Patent Application No. 63-125742 has a MOS-FET.
A constant voltage generating circuit utilizing the difference in the threshold voltage of is shown. FIG. 42 shows an example of the constitution of a constant voltage generating circuit which is improved to operate at an external power supply voltage higher than the voltage that can be applied to the gate oxide film. In the figure, 75 is a part newly inserted for this purpose, and T151 is N
The channel MOS-FET, T152 is a P-channel MOS-FET.
This allows the maximum applied voltage of any of the transistors in the circuit to be reduced to about half the external power supply voltage, like the inverter described above. The value of the constant voltage generated in this circuit is two N-channel MOS-FETs as described in Japanese Patent Application No. 63-125742.
Difference in threshold voltage between T149 and T150 VT1 (T149) -VT1
(T150). T149 is a transistor having a high threshold voltage similarly to that shown in FIG. In this example, VT1 (T149) = 1.05V, VT1 (T150) = 0.3
As V, the output voltage Vref = 0.75V is obtained.

FIG. 43 shows a configuration example of the differential amplifier circuit according to the present invention. In the figure, T161 and T162 are two N-channel MOS-FETs for inputting differential signals, and T160 is an N-channel MO for supplying a bias current to the differential amplifier circuit.
S-FET and B1 are signals for setting the bias current,
T163 and T164 are two P-channel MOS-FETs forming a current mirror type load. In a normal differential amplifier circuit, the nodes N13 and N15 are connected, and the node N14 and the output out2 are connected. Here, however, the circuit blocks indicated by 76 and 77 in the figure are added, and an external voltage higher than the voltage that can be applied to the gate oxide film is added. It is designed to work with power supply voltage.

In FIG. 43 (a), reference numeral 76 denotes two N channels M
OS-FET T165 and T166, and P-channel MOS-FET T1
It consists of 67 and. This allows the transistor
The maximum voltage applied to the drains (N13, N14) of T161 and T162 is Vn-VTN1, and the minimum voltage applied to the drain (out2) of the transistor T164 is Vp.
Limit to + | VTP1 |. Here, VTN1 and VTP1 represent the threshold voltages of the N-channel and P-channel MOS-FETs, respectively. As Vn and Vp, the bias voltage having the power supply voltage dependency shown in FIGS. 37 (b) and 41 (a) can be used as it is, as in the previous embodiment. Now, when the differential amplifier circuit shown in FIG. 43 (a) operates as a small signal amplifier circuit, that is, when there is no large difference between the two input levels and the transistors T161 and T162 both operate in the saturation region, The voltage value of the node 14 becomes approximately Vn-VTN1. Therefore, even if the transistor T167 is omitted as shown in FIG.
There is no large voltage difference between the gate and drain of T164. When used only as a small signal amplifier circuit, the circuit system of FIG. 43 (b), which has a simple configuration, is suitable. The signal level of the output out2 of these differential amplifier circuits is equal to the signal level of the output out2 of the inverter shown in FIG. 37 (a), and the output of the differential amplifier circuit can directly drive the input in2 of the inverter. It is convenient to combine them to form a circuit. In the above configuration example of the differential amplifier circuit, the input In
There is a characteristic that a large voltage gain can be obtained when the voltage levels of (+) and In (-) are Vn-VTN1 or less. On the contrary, when operating at an input voltage level higher than Vp + | VTP1 |, the N-channel MOS-FET and the P-channel MOS-FET forming the differential amplifier circuit are set to P-channel and N-channel, respectively.
Replace each channel with a low voltage level (signal level of the output out1 of the inverter shown in FIG. 37 (a))
It may be configured to obtain the output of. Also at this time,
The same effect as in the case of the above configuration can be obtained. Next, an example in which this differential amplifier circuit is applied to an LSI chip circuit will be described.

44 to 46 show an example in which the present invention is applied to a VL (reference voltage) generating circuit serving as a reference of the internal power supply voltage VCL. In FIG. 44, 80 is a VL (reference voltage) generation circuit corresponding to 9 of FIG. 1, A15 is a differential amplifier circuit,
R50 and R51 are resistors for setting the amplification factor. The VL generating circuit includes a constant voltage (Vref) generating circuit 81 described in FIG. 42, an aging voltage (VA) generating circuit 82 for generating a voltage higher than the voltage during the standard operation during an aging test, A maximum value output circuit 83 that compares Vref and VA and outputs the larger voltage,
The switch 84. Since the voltage characteristic of the aging test is not necessary when the information is held, the maximum value output circuit is set in the non-operating state, and the switch is closed to directly output Vref. Now, in this example, Vr
ef = 0.75V, VA = 1 / 5Vcc, power supply voltage is 3.
When the voltage is 75V or higher, the aging test is performed. That is, when the power supply voltage is 3.75V or lower, VL = 0.75V, and when it is 3.75V or higher, VL =
1 / 5Vcc is output. When R50 = R51, the amplification factor is set to 2, and when the power supply voltage is 3.75V or less, VC
When L = 1.5V, 3.75V or higher, VL = 2 / 5Vcc
Is applied to the circuit as an internal power supply voltage.

FIG. 45 shows the dependency of each voltage on the external power supply voltage VCC.
Shown in. As a result, the power supply voltage of the internal circuit is 1.5 V in the standard operating state (for example, the power supply voltage is 3 to 3.6 V),
In the aging test state (for example, the power supply voltage is 5.3V), 2.1V is obtained. FIG. 46 shows a more detailed configuration example of the VL (reference voltage) generation circuit. 9 in the figure
0 is a maximum value output circuit, and T179 is an N-channel MOS-FET that operates as a switch. The maximum value output circuit is composed of two differential amplifier circuits 90a and 90b, P-channel MOS-FETs T177 and T1 driven by the outputs of the respective differential amplifiers.
P-channel MOS-FET T177 for relaxing the voltage applied to the gate oxide film of 78, T177 and T178, N-channel MOS-for lowering the grounding impedance of the output terminal N22-
Composed of FET T175. Here, the two differential amplifiers 90a and 90b are the same as those shown in FIG. 43 (a). The configuration of the maximum value output circuit is also basically the same as that shown in FIG. 41 (b). With this configuration, it is possible to obtain a maximum value output circuit that operates at a power supply voltage higher than the maximum applicable voltage of the gate oxide film. In the information holding state, the transistor T179 is turned on and Vref is output as it is as VL. In addition, the maximum value output circuit is made inoperative to reduce current consumption.

FIG. 47 shows the limiter shown in FIG.
The structure of an enable signal (LM) generation circuit is shown.
In the figure, A12 and A13 are single-ended differential amplifier circuits having the same configuration as shown in FIG. It shows a double-ended differential amplifier circuit that outputs a signal. The double-ended type differential amplifier circuit is a P-channel MOS-FET T180 driven by two inputs.
And T181, P-channel MOS-FETs T184 and T185 for relaxing the voltage applied to the gate oxide film, two cross-coupled N-channel MOS-FETs T182 and T183, and the voltage applied to the gate oxide film. N-channel MOS-FETs T186 and T187 for alleviating the above, and speed-up capacitors CC1 and CC2 provided for accelerating the speed at which the output is inverted. Of these, the speed-up capacitor determines the response speed of the circuit, and even if omitted, the basic operation is not impaired even if omitted depending on the application.

The operation will be described below with reference to the operation timing chart shown in FIG. In the following explanation, when the internal power supply voltage VCL in the standard operating state is 1.5V (VL
= 0.75V). As shown in the figure, if the external power supply voltage Vcc drops from 4V to 1V, the voltage of the outputs (nodes N25 and N26) of the differential amplifier circuits A12 and A13 at time t0 when half the voltage of Vcc crosses 0.75V. Is reversed. As a result, the transistor T180 shifts to the cut-off state and T181 shifts to the on-state, and the node N28
Voltage rises to Vcc. Node N3 is synchronized with this
The potential of 0 is Vn-VTN1 (VTN1 is the threshold voltage of T187)
And the potentials of the node N29 and the node N27 are pulled down to the ground potential. As a result, the voltages at the outputs N27 and N28 of the double end type differential amplifier circuit are inverted and become 0V and VCC = 1V, respectively. Although FIG. 48 schematically shows the operation, actually, a series of these operations are performed in a time sufficiently shorter than the change of the power supply voltage. Therefore, the change in the power supply voltage does not adversely affect the circuit operation. Further, by intentionally providing a capacitor in the power supply wiring in the chip, it is possible to control the change in the power supply voltage and further suppress the influence on the circuit operation. Although the above description has been made on the case of lowering the external power supply voltage, conversely, the operation is similarly performed when increasing the external power supply voltage.

Now, the LSI chip according to the present invention is
When a system is constructed using SI and semiconductor elements, it is necessary to match the input / output levels of signals exchanged between them. There are the following two standard input / output levels in an LSI that operates with a single power supply (generally 5 V). (A) TTL level, (b) C
MOS level.

Among these, at the TTL level, the value of the high voltage (“1”) output (VOH) must be 2.4 V or more. Therefore, when the power supply voltage is used at 2.4 V or less, it is necessary to use the CMOS level or to newly set the input / output level standard. Conventional LSI and T
When configuring a system with a TL logic circuit and the like, compatibility with the above-mentioned input / output level is an important factor. The compatibility eliminates the need for a level conversion circuit, reduces the number of parts, and leads to system cost reduction. Also, circuit performance such as noise resistance and speed is improved,
Maximum performance can be demonstrated. Therefore, an embodiment of the present invention having an input / output circuit configuration that maintains compatibility with conventional input / output levels will be described below. According to the present invention, the following three product specifications can be realized using one chip without changing the design. (1) During standard operation (for example, the power supply voltage Vcc is 4.5 to 5.5)
V or 3 to 3.6V), input / output is performed at the TTL level. If necessary, a decrease in Vcc (for example, the power supply voltage Vcc is 1.0 to 2.5 V) is detected in the chip and information is retained (battery backup). (2) The power supply voltage Vcc operates at, for example, 1.0 to 5.5 V, and the input / output is performed at the CMOS level. Vcc as required
(For example, the power supply voltage Vcc is 1.0 to 2.5 V) is detected in the chip, or information is retained (battery backup) by a control signal from the outside. (3) The power supply voltage Vcc operates at, for example, 1.0 to 5.5 V, and the chip automatically switches the input / output level according to the value of the power supply voltage. For example, the power supply voltage Vcc is 2.5 to 5.5.
Input and output are performed at the TTL level when the voltage is V and at the CMOS level when the power supply voltage is 1.0 to 2.5V.

In FIG. 49 (a), switching is performed by wiring or bonding using one chip, and the above (1)
An example of realizing two products of (2) and (2) is
It shows examples of products that automatically detect changes in the value of the power supply voltage and switch the input and output levels. FIG. 49
In (a), 1 is an LSI chip, 5 is an LSI circuit block that operates with an internal power supply voltage (for example, 1.5 V), and PA
DT is an input / output pad for TTL level, PADC is CMO
I / O pads for S level, IB1 and OB1 are TTL
Level input buffer and output buffer, IB2 and OB2 are CMOS level input buffer and output buffer, and SW1 is for selecting either of the outputs of the two input buffers to be input to the low voltage operation LSI circuit block. A switch SW0 is a switch for selecting which of the two output buffers the output of the low-voltage operation LSI circuit block is input to. As a method of performing this switching in an actual LSI, there is a master slice using wiring such as aluminum. This is a method in which when forming a wiring layer such as aluminum, two masks for transferring the wiring pattern are prepared corresponding to the above switches, and the mask is used properly according to the product. Further, two kinds of bonding pads corresponding to the input / output levels are provided on the LSI, and one of the bonding pads is bonded to the two products, so that two products can be produced separately. Alternatively, one bonding pad may be provided and the connection with the input / output buffer may be switched by a master slice formed of a wiring such as aluminum.

FIG. 49 (b) shows a method of switching the input / output levels of one input / output buffer. In the figure, PADX is an input / output pad, IB3 and OB3 are input buffers and output buffers, and 96 is an input / output level setting circuit for controlling the input / output level of each buffer according to the power supply voltage. A more specific configuration example will be described later. With the above configuration, the three product specifications described above can be realized by one chip, which is convenient in terms of product cost and usability. In the above example, the so-called I / O common system in which the same input and output terminals are used has been described. However, in addition to this, the present invention can be applied to both input only and output only. Can be similarly applied. Hereinafter, specific configuration examples of the output buffer, the input buffer, and the input protection circuit will be described. In the following embodiments, a case will be described in which a circuit is configured by a MOS-FET having a thin (for example, 6.5 nm) gate oxide film used for an internal circuit. The present invention can be similarly applied to the case of using a MOS-FET having different kinds of gate oxide films.

When constructing the output buffer, an internal low signal amplitude (for example, 1.5 V) to an external high signal amplitude (for example, TTL level of 2.4 V, and CMOS level of 5 V when the power supply voltage is 5 V are used. ) Need to be converted to amplitude. First, an example of a circuit configuration for obtaining a CMOS level output signal will be described. FIG. 50 (a) shows a configuration example of an amplitude conversion circuit that inputs a low signal amplitude in1 of the internal circuit and outputs a high signal amplitude Out. In the figure, 98
Is the inverter circuit N31 and N32 shown in FIG.
Is two inputs corresponding to in2 and in1 of FIG. 37 (a), Out is the output of the inverter, T190 is an N-channel MOS-FET driving N32, T191 is the gate of T190 by limiting the maximum voltage of the node N32. An N-channel MOS-FET that relaxes the voltage applied to the oxide film, T192 similarly indicates a P-channel MOS-FET that limits the minimum voltage of the node N31, and R65 indicates a resistance. Among them, the transistor T190 and the resistor R65 form an inverter circuit of a resistive load.
By using a resistive load, it is possible to obtain two outputs on the low voltage side and the high voltage side from one input on the low voltage side.

Next, the operation of this circuit will be described with reference to FIG. In the following example, it is assumed that the power supply voltage is 5V and the bias voltages Vn and Vp are both 2.5V. When the input in1 is 0V, the transistor T190 is cut off, and the node N31 is pulled up to the power supply voltage 5V by the resistor R65. The node N32 is Vn (2.
It is a value (2V) lower than the threshold voltage of the transistor T191 (for example, 0.5V) from 5V. Therefore, the voltage of the output Out of the inverter 98 is 0V. When the input in1 rises from 0V to 1.5V at time t0, the transistor T190 becomes conductive and the node N31
Is a value (3V) higher than Vp (2.5V) by the absolute value (for example, 0.5V) of the threshold voltage of the transistor T192,
The node N32 is pulled down to 0V and the output Out rises to 5V. At time t1, input in1 goes from 1.5V to 0
When the voltage goes down to V, the output Out similarly changes from 5V to 0V. Thus, with this circuit configuration,
For an input signal amplitude of 1.5V, the output signal amplitude of 5V required by the output buffer is obtained. Also, in this circuit, since only a maximum voltage of about 2.5V is applied to any transistor, even a MOS-FET using a thin gate oxide film (for example, 6.5 nm) should operate stably with a power supply voltage of 5V. Can be configured.

FIG. 51 (a) shows another example of the configuration of the amplitude conversion circuit which inputs the complementary low amplitude signals in1 and in1 and outputs the high signal amplitude Out, and FIG. 51 (b) shows its operation timing. ing. In the figure, 102 is a double-ended input / double-ended output differential amplifier circuit having the same configuration as that shown in FIG. 47, and 100 and 101 are shown in FIG. 37 (a).
It shows the same inverter circuit as shown in. Since the double-ended output differential amplifier circuit used here does not flow current in a steady state, a circuit with lower power consumption can be realized as compared with the above-described example. Further, the substrate (back gate) of each transistor constituting the inverter of the final output stage is biased to minus (-2V) in the N channel and plus (7V) with respect to the power supply voltage (5V) in the P channel. Thereby, for example, even if an undershoot or an overshoot due to impedance mismatch appears in the output, the PN junction can be prevented from being biased in the forward direction. Therefore, it is possible to prevent injection of minority carriers into the substrate (deterioration of refresh characteristics when minority carriers diffuse to the charge storage node of the memory cell) and latch-up caused by turning on the parasitic thyristor. As described above, according to the present invention, it is possible to easily configure a circuit that outputs a CMOS-level high-amplitude signal (for example, 5 V) from a low-amplitude signal (for example, 1.5 V) of an internal circuit.

Generally, when configuring a system, the outputs of a plurality of LSIs are connected to one data bus, and only the outputs of the selected LSI drive the bus.
In order to perform such control, it is desirable to make the output impedance of the unselected LSI infinite. A conventional LSI has three output (tri-state) characteristics as an output level, that is, high voltage, low voltage, and neither drive (infinite output impedance). In order to obtain such characteristics, it is necessary to control whether the output is driven (low impedance) or not (infinite impedance). The signal for this control is generated from either an output enable signal (Out put Enable = OE) or a chip select signal (Chip Select = CS) input from the outside. In the conventional output circuit, the tri-state characteristic is realized by taking the logic of these signals and the output data and driving the final stage transistor by the signal obtained as a result. In the case of configuring the same output circuit in the present invention, there may be a configuration in which the logic circuit is operated with a low power supply voltage and the logic circuit is not used in the circuit which operates with the external power supply voltage. However, in that case, the number of stages of the amplitude conversion circuit and the inverter that are inserted between the logic circuit and the output increases, and for example, the delay time from the OE signal to the output increases or the timing of driving the high-voltage side transistor. There is a disadvantage that a large current transiently flows due to a difference in the timing of driving the transistor on the low voltage side. On the other hand, if the logic circuit can be configured with the external power supply voltage, the degree of freedom in design is further increased, which is preferable in terms of circuit performance. An embodiment in which a logic circuit is configured with an external power supply voltage will be described below. In addition to the output buffer, this logic circuit is also effective as a means for generating control signals for various circuits operating with an external power supply voltage.

FIG. 52 shows a configuration example of a 2-input NAND circuit according to the present invention. The input A of FIG. 52 (a) is the same as that of FIG. 52 (b).
In1A and in2A, B input is in1B and in2B
Respectively correspond to. Of each input signal, in1A and in2
A, in1B and in2B are in1 and in2 in FIG. 37 (a).
Like, changes in phase. In FIG. 52 (b), transistors T200 and T201 are the input signals in1A and
Driven by in1B, transistors T202 and T203 are driven by input signals in2A and in2B on the high voltage side. Transistors T204 and T205 are T202 and T in FIG. 37 (a).
Similar to 203, it is provided to operate at a voltage higher than the voltage that can be applied to the gate oxide film. With this configuration, the function of the NAND gate is obtained in which the output becomes the low level only when the two inputs are both at the high level. As described above, a fine transistor can be used with a high power supply voltage only by adding two transistors in addition to the normal CMOS NAND circuit. It should be noted that although a 2-input NAND circuit has been described as an example here, other
For example, a NOR circuit, an exclusive OR circuit, the above-mentioned logic circuit having three or more inputs, a composite gate which outputs various composite logics by using outputs of a plurality of logic circuits as inputs, and further,
The present invention can be similarly applied to a sequential circuit such as a latch circuit or a flip-flop circuit.

FIG. 53 (a) shows an example of the structure of a tri-state output buffer using this logic circuit. FIG. 53 (b) shows it in a simplified manner with logical symbols. In the figure, G12 is a 2-input NAND circuit,
G13 is a 2-input NOR circuit, and T210 and T211 are N-channel and P-channel MOS-FETs that constitute an output circuit. When the output enable signal OE is high voltage, the same data as the input do is output from the buffer to the output Do, and when the OE is low voltage, the gate of T210 is low voltage and the gate of T211 is irrespective of the input data. Is fixed to a high voltage, the output Do becomes floating (impedance is almost infinite). FIG. 53 (a) is a specific configuration example of a circuit having the same function, which is configured by using fine elements having a breakdown voltage lower than the value of the external power supply voltage. In the figure, 112 is a NAND circuit, 113 is N
An OR circuit, 114 is an output circuit, and 110 and 111 are shown in FIG.
This is the same amplitude conversion circuit as 102 in (a). The amplitude conversion circuit is a low-amplitude signal do1, oe on the low power supply voltage side from the internal circuit.
Based on 1 and oe1 —, signals do2, oe2, and oe2 — on the high power supply voltage side necessary for operating 112 and 113 are generated. As shown here, according to the present invention, it is possible to configure a logic circuit that operates with an external power supply voltage exceeding its withstand voltage even if a fine element is used, and reduce delay time and transient current of a tri-state output circuit or the like. can do.

Next, an example of a CMOS level input circuit is shown in FIG.
4 will be described. In the figure, reference numeral 115 indicates FIG. 37 (a).
The same inverters as shown in T220 and T221 are used for the transistor T22 even if a large signal amplitude is applied to the input.
2 and a transistor X for limiting the voltage applied to the gate oxide film of T223 to the oxide film breakdown voltage or less, and X is an input signal. In this figure, a high voltage (eg 5
V) is applied, the voltage applied to the node N40 is Vn−
It is limited to VT1 (T220), that is, about 2V. Similarly, even if a low voltage (for example, 0V) is applied to the input, the minimum voltage applied to the node N41 is about 3V, and the voltage applied to each transistor should be reduced to about half the power supply voltage. You can Further, since the signal amplitude of x1 — which is one of the outputs of this circuit is about 2 V, this can be directly used as the input of the internal circuit operating at the low power supply voltage.

In the above embodiments, examples of CMOS level output circuits and input circuits have been described. Next, FIG. 55 shows an example of an input circuit and an output circuit that automatically switch between the TTL level and the CMOS level according to the value of the power supply voltage.
In the figure, PADI is an input pad, PAD0 is an output pad, IPD is an input protection element for preventing junction and gate destruction due to static electricity, IB5 is an input buffer, and OB5 is an output buffer. The input protection element will be described later in detail. The input buffer IB5 is
Two MOS-FETs TIN1 and TIP1 forming a CMOS inverter, an N-channel MOS-FET TIN2 for limiting the power supply voltage of the CMOS inverter to a predetermined value or less determined by the bias voltage Vn1, and an input voltage of the CMOS inverter are also predetermined. N-channel MOS-FE for limiting below the value of
It consists of T TIN0. Also, the output buffer OB5
Is an inverter 116 similar to that shown in FIG.
Amplitude conversion circuit 11 for generating drive signals d1 and d2 for the inverter based on the low amplitude signal dout from the internal circuit
7. N-channel MOS-FET for limiting the output voltage of the inverter to a predetermined value or less determined by the bias voltage Vnt
It consists of TON2. It goes without saying that a buffer having a tri-state output characteristic can be configured by taking the logic of the output enable signal as in the case shown in FIG. In these circuits, if the value of the bias voltage Vn1 is appropriately changed according to the power supply voltage, input / output can be performed at the TTL level at a high power supply voltage and at the CMOS level at a low power supply voltage.

FIG. 56 shows an example of the dependence of the value of the bias voltage Vn1 on the power supply voltage VCC. In the figure, VOL and VOH are T corresponding to "0" and "1", respectively.
The output level of TL, VIL and VIH indicate the input level of TTL corresponding to "0" and "1", respectively. These values in a normal TTL logic gate are
0.4V, VOH = 2.4V, VIL = 0.8V, and VIH
= 2.0V. The value of the bias voltage Vn1 is 3 V when the power supply voltage is 2.5 V or more, and the power supply voltage is 2.5 V.
When it is lower than V, TIN0 is controlled to operate in a non-saturation region, for example, Vcc + 0.5V.
First, the operation of the output buffer circuit will be described. The voltage of the node N48 is 0 when a low voltage (“0”) is output.
When outputting V and high voltage ("1"), it becomes Vcc.
Therefore, at low voltage output, it is 0 regardless of the value of the power supply voltage.
V is output to Dout. On the other hand, the voltage value of Dout at the time of high voltage output depends on the value of the power supply voltage VCC as shown in FIG.
When Vcc ≧ 3V, Vn1−VT1 (TON2), Vcc <3
When it is V, it becomes Vcc. As a result, the power supply voltage is 3V
With the above, an output voltage amplitude satisfying the TTL level output characteristic can be obtained. By limiting the output voltage to 2.5 V or less, the power supply current when charging and discharging a large load capacity can be reduced to the necessary minimum.

Next, the operation of the input buffer circuit will be described. The power supply voltage of the CMOS inverter constituted by TIN1 and TIP1 is supplied from the source terminal of the transistor TIN2. Therefore, the value is 2.5 V when the power supply voltage is 3 V or higher and 0 V when the power supply voltage is 3 V or lower.
On the other hand, when the power supply voltage is 3 V or higher, the input voltage of the inverter is limited to 2.5 V or lower, and when it is 3 V or lower, the voltage input to Din is applied as it is.
With this circuit configuration, the power supply voltage is from 1 V to 5.5, for example.
Even if it greatly changes to V, the power supply voltage of the inverter and the maximum amplitude of the input signal become substantially equal. If the channel conductances of the two transistors forming the inverter are set to be substantially equal to each other, the logical threshold voltage of the inverter becomes one half of the power supply voltage. Therefore, when the power supply voltage is 3 V or higher, the logical threshold voltage is about 1.25.
The logic threshold voltage when V is 3 V or less is Vcc / 2, and a certain voltage (3 V in this example) is used as a boundary, and a TTL level is used when the power supply voltage is higher than that and a CMOS level is used when the power supply voltage is lower than that. An input buffer can be provided that As described above, according to the present invention, an LSI having a wide operating power supply voltage range can operate at an optimum input / output level at the power supply voltage value. As a result, the maximum noise margin can be realized with the minimum power consumption. In the output buffer, the substrates (back gates) of the three transistors TON0, TON1 and TON2 are common. By doing this,
When a high voltage surge is applied to the output terminal, the electric charge can be discharged at high speed by a large current. This is a clamp MOS-
This is because it is the same as the operation of the FET, and when the substrate potential rises due to the breakdown, it is easy to turn on the parasitic bipolar transistor existing between it and the ground potential. As a result, the electrostatic breakdown voltage of the output terminal can be improved even if a fine element is used. In the above embodiment, N
The value of the substrate voltage VBP1 of the channel MOS-FET is usually set to a negative value (for example, -3V) so that the PN junction is not biased in the forward direction when the input voltage becomes negative (undershoot). However, 0 V may be used as long as the forward current is allowed to flow. Further, the N-channel MOS-FET may be formed in the P-type substrate or in the P-well electrically insulated from the P-substrate as shown in FIG. In the latter case, the resistance of the P well is lower than the resistance of the substrate, so that the parasitic bipolar transistor is easily turned on, and the electrostatic breakdown voltage is increased.

In the above embodiment, it is necessary to generate the bias voltage Vn1 higher than the power supply voltage. FIG. 57 shows an example of configuring an input buffer without using such a bias voltage.
Shown in. In the figure, the input buffer IB6 is composed of two circuit blocks, IB6a and IB6b. I
B6a has the same circuit configuration as the input buffer IB5 of FIG. The IB6b is a circuit for converting the output of the IB6a into a voltage level convenient for driving the internal circuit. I
In B6b, T231 and T232 are two MOS-FETs forming a CMOS inverter, T232 is a P-channel MOS-FET for raising the potential of the node N52 to the internal power supply voltage VCL when din is a low voltage, and T230 is a node N52. It is an N-channel MOS-FET for preventing current from flowing back from N52 to N51 when the voltage becomes high. FIG. 58 shows the dependence of the bias voltage Vn2 on the power supply voltage Vcc in this circuit configuration. 3V when the power supply voltage is 3V or higher
(Constant), power supply voltage VCC when power supply voltage is 3V or less
Is equal to. The operation of this circuit will be described in two cases. In FIG. 59, the power supply voltage Vcc is 5
The operation waveforms of each part when V and the internal power supply voltage VCL are 1.5V are shown. Input voltage is low voltage (eg 0.4
V), the voltage of the node N51 is Vn2-VT1 (TIN
5) (for example, 2.5 V), the voltage of the node N52 is VCL (1.
5V), and a low voltage (0V) is output to din.
When the input voltage changes from a low voltage (for example, 0.4V) to a high voltage (for example, 2.4V), the voltage of the node N50 rises following it, and the voltage of the node N51 drops to 0V. The channel conductance of T230 is set larger than that of T233, and the voltage of node N52 is almost zero.
It is pulled down to V and the value of din rises to VCL (1.5V). Conversely, if the input voltage is high (for example, 2.
When the voltage changes from 4V) to a low voltage (for example, 0.4V), the voltage of the node N50 drops accordingly, and the voltage of the node N51 decreases.
Voltage of Vn2-VT1 (TIN5) (for example, 2.5V). As a result, the voltage of the node N52 becomes VCL-VT.
It is pulled up to 1 (T230) (eg 1.2V) and din
To 0V. This turns on T233 and changes the voltage of the node N52 from VCL-VT1 (T230) to VCL (1.5V).
Up to. Thus, the node N52 by T232
The voltage amplitude of N52 becomes the same as the power supply voltage because it is fed back to, and the through current can be prevented from flowing in the CMOS inverter composed of T231 and T232.

Next, FIG. 60 shows the operation waveform of each part when both the power supply voltage VCC and the internal power supply voltage VCL are 1.5V. When the input voltage is low (for example, 0V),
The voltage of the node N51 is Vn2-VT1 (TIN5) (for example, 1.
2V), the voltage of the node N52 becomes VCL (1.5V),
A low voltage (0V) is output to din. When the input voltage changes from a low voltage (for example, 0V) to a high voltage (for example, 1.5V), the voltage of the node N50 is Vn2-VT1 (TIN5).
(For example, 1.2V), the voltage of the node N51 becomes 0
Withdraw to V. Channel conductance of T230 is T233
The voltage at node N52 is also reduced to almost 0V, and the value of din is VCL (1.5
V). On the contrary, when the input voltage changes from a high voltage (for example, 1.5V) to a low voltage (for example, 0V), the voltage of the node N50 drops to 0V following the voltage, and the voltage of the node N51 becomes Vn2-VT1. Pull up to (TIN5) (eg 1.2V). As a result, the node N52
Is raised to VCL-VT1 (T230) (for example, 1.2V), and din is dropped to 0V. This makes T233
Turns on and raises the voltage of the node N52 from VCL-VT1 (T230) to VCL (1.5V). As described above, even when the power supply voltage is low and the output amplitude of IB6a is equal to or lower than the power supply voltage, the voltage amplitude of the node N52 is the same as the power supply voltage. Therefore, the CMOS inverter composed of T231 and T232 penetrates. No current flows. As described above, it is possible to realize an input / output buffer that switches its input / output level according to the value of the power supply voltage without using a bias voltage higher than the power supply voltage.

Finally, the LS composed of fine elements
FIG. 61 shows a configuration example of an input protection element that protects the elements of the internal circuit from the surge of the input in I. In the figure, PADI is an input pad for inputting a signal, and 120 is a first protection element for releasing a high voltage due to a surge to a ground potential by utilizing punch-through between impurity diffusion layers formed in a semiconductor substrate. , 121 are gate clamp elements for limiting the voltage of the node N60 to a certain predetermined voltage or less, and R70 is a resistor for absorbing the difference between the high voltage applied to the pad and the clamp voltage. The gate clamp element is composed of two N-channel MOS-FETs T connected in series.
It is composed of PD1 and TPD2, and a bipolar transistor Q1 using a parasitic element. A bias voltage Vn is applied to the gate of TPD1 in the same manner as in the circuit described above to prevent a voltage exceeding the gate oxide film breakdown voltage from being applied to the drain of TPD2. The gate of TPD2 is grounded so that current does not flow through the two MOS-FETs during normal operation.

The planar structure of the gate clamp element is shown in FIG.
63 shows the cross-sectional structures at A and A ', respectively. In FIG. 62, 122 and 123 are electrically isolated regions electrically insulated from each other and formed in the semiconductor substrate, 124 and 125 are gate electrodes made of polysilicon or the like, and 126 to 130 are electrically The impurity diffusion layer formed in the active region, or the contact hole formed through the insulating film for electrically connecting the upper metal wiring to the gate electrode, and aluminum for 131 to 134 The metal wirings are shown respectively. Further, in FIG. 63, 50 is a thick insulating film formed by oxidation of the substrate to electrically insulate electrically active regions in the semiconductor substrate, and 1
39 and 140 are polysilicon forming the gate electrode, 135
To 138 are impurity diffusion layers formed in the substrate in a self-aligned manner using the insulating film or the gate electrode as a mask,
Reference numeral 141 denotes an impurity diffusion layer or a thick insulating film formed for electrical insulation between the gate electrode and the metal wiring located above. In the structure shown in the figure, the terminal (node N60) clamped to the wiring 132, the wiring 1
A ground terminal (VSS) is applied to 33 and 134, and a bias voltage Vn is applied to the wiring 133, respectively. In FIG. 63, there are three NPN-type parasitic bipolar transistors Q1a, Q1b, and Q1c based on the P substrate. The symbol Q1 in FIG. 61 is representative of these. Next, the operation of this element will be described. When the voltage applied to the node N60 exceeds the reverse breakdown voltage of the PN junction formed between the impurity diffusion layer 136 and the substrate, the current due to the breakdown of the junction raises the potential of the P substrate, and the parasitic bipolar Turn on the transistor. As a result, a large collector current flows between the impurity diffusion layers 136 and 135, or 138, the charge of the node N60 is extracted, and the potential thereof is clamped. Of these, Q1b and Q1c are connected in series, so that the collector current becomes smaller than that of Q1a. Therefore, effectively, the MOS-FET turns on the parasitic bipolar transistor first, and the parasitic bipolar transistor Q1a turns on the large collector current. Thus, by disposing the impurity diffusion layer different from the impurity diffusion layer of the transistor near the node N60 and grounding it, the effective distance between the collector and the emitter of the parasitic bipolar transistor is shortened, and the parasitic bipolar transistor is shortened. A large collector current can be obtained when the transistor operates. As described above, the structure in which the grounded impurity diffusion layer is arranged near the terminal to be clamped can be applied not only as the input protection element but also as the output protection element. Further, in this example, the gate clamp element is formed in the P substrate, but it may be formed in the P well electrically isolated from the substrate in the structure shown in FIG. By doing so, the resistance values of the base and P well are increased, the parasitic bipolar transistor is easily turned on, and the effect of clamping can be further enhanced. The value of the bias voltage VBP1 of the P substrate or the P well is usually a negative value (for example, -3V). It may be 0V. In addition, although the example using the P substrate is described in this embodiment, the present invention can be similarly applied to the case where the N substrate is used as long as the same element is formed in the P well.

Although the details of the present invention have been described with reference to the respective embodiments, the scope of application of the present invention is not limited to these. For example, although the memory circuit is mainly described here, as described at the beginning of this specification, the memory LS
I, logic LSI, or composite LS combining these
It is applicable to I or all other LSIs. Also, regarding the types of elements used, both p-type and n-type M
LSI using OS transistor, LSI using bipolar transistor, LS using junction type FET
I, BiCMOS type LSI in which a CMOS transistor and a bipolar transistor are combined, and further, a material other than silicon, for example, an LSI in which elements are formed on a substrate such as gallium arsenide, can be applied as it is.

[0082]

According to the present invention described above, the characteristics of the element by the latest microfabrication technology are utilized to operate at low power consumption and high speed, and the operation state is switched and the information is retained by switching the operating state. A highly integrated LSI that can also operate can be provided.

[Brief description of drawings]

FIG. 1 is a diagram of an embodiment for explaining the basic concept of the present invention.

FIG. 2 is a diagram of an embodiment for explaining the basic concept of the present invention.

FIG. 3 is a diagram of an embodiment for explaining the basic concept of the present invention.

FIG. 4 is a diagram of an embodiment for explaining the basic concept of the present invention.

FIG. 5 is a diagram of an example for explaining the basic concept of the present invention.

FIG. 6 is a diagram of an embodiment for explaining the basic concept of the present invention.

FIG. 7 is a diagram of an example for explaining the basic concept of the present invention.

FIG. 8 is a diagram of an embodiment in which the present invention is applied to a static memory.

FIG. 9 is a diagram of an embodiment in which the present invention is applied to a static memory.

FIG. 10 is a diagram of an embodiment in which the present invention is applied to a static memory.

FIG. 11 is a diagram of an embodiment in which the present invention is applied to a dynamic memory.

FIG. 12 is a diagram of an embodiment in which the present invention is applied to a dynamic memory.

FIG. 13 is a diagram of an embodiment in which the present invention is applied to a dynamic memory.

FIG. 14 is a diagram of an embodiment in which the present invention is applied to a dynamic memory.

FIG. 15 is a diagram of an embodiment in which the present invention is applied to a dynamic memory.

FIG. 16 is a diagram of an embodiment in which the present invention is applied to a dynamic memory.

FIG. 17 is a diagram of an embodiment in which the present invention is applied to a dynamic memory.

FIG. 18 is a diagram of an embodiment in which the present invention is applied to a dynamic memory.

FIG. 19 is a diagram of another embodiment for explaining the basic concept of the present invention.

FIG. 20 is a diagram of another embodiment for explaining the basic concept of the present invention.

FIG. 21 is a diagram of another embodiment for explaining the basic concept of the present invention.

FIG. 22 is a diagram of another embodiment for explaining the basic concept of the present invention.

FIG. 23 is a diagram of another embodiment for explaining the basic concept of the present invention.

FIG. 24 is a diagram of another embodiment for explaining the basic concept of the present invention.

FIG. 25 is a diagram of a specific example of an element constituting the present invention.

FIG. 26 is a diagram of a specific example of an element constituting the present invention.

FIG. 27 is a diagram of a specific example of a semiconductor substrate that constitutes the present invention.

FIG. 28 is a diagram of a specific example for reducing power consumption when holding information.

FIG. 29 is a diagram of a specific example for reducing power consumption when holding information.

FIG. 30 is a diagram of a specific example for reducing the power consumption when holding information.

FIG. 31 is a diagram of a specific example of a dynamic memory operating at a low voltage.

FIG. 32 is a diagram of a specific example of a dynamic memory operating at a low voltage.

FIG. 33 is a diagram of a specific example of a dynamic memory operating at a low voltage.

FIG. 34 is a diagram of a specific example of a dynamic memory operating at a low voltage.

FIG. 35 is a diagram of a specific example of a dynamic memory operating at a low voltage.

FIG. 36 is a diagram of a specific example of a dynamic memory operating at a low voltage.

FIG. 37 is a diagram of a specific example of various circuits that are operated at a voltage higher than the gate breakdown voltage of a fine element.

FIG. 38 is a diagram of a specific example of various circuits operated with a voltage higher than the gate breakdown voltage of a fine element.

FIG. 39 is a diagram of a specific example of various circuits operated with a voltage higher than the gate breakdown voltage of a fine element.

FIG. 40 is a diagram of a specific example of various circuits that are operated with a voltage higher than the gate breakdown voltage of a fine element.

FIG. 41 is a diagram of a specific example of various circuits operated with a voltage higher than the gate breakdown voltage of a fine element.

FIG. 42 is a diagram of a specific example of various circuits that are operated at a voltage higher than the gate breakdown voltage of a fine element.

FIG. 43 is a diagram of a specific example of various circuits operated with a voltage higher than the gate breakdown voltage of a fine element.

FIG. 44 is a diagram of a specific example of various circuits operated with a voltage equal to or higher than the gate breakdown voltage of a fine element.

FIG. 45 is a diagram of a specific example of various circuits operated with a voltage higher than the gate breakdown voltage of a fine element.

FIG. 46 is a diagram of a specific example of various circuits operated by a voltage higher than the gate breakdown voltage of a fine element.

FIG. 47 is a diagram of a specific example of various circuits operated with a voltage higher than the gate breakdown voltage of a fine element.

FIG. 48 is a diagram of a specific example of various circuits operated with a voltage higher than the gate breakdown voltage of a fine element.

FIG. 49 is a diagram of an embodiment showing the basic concept of the configuration of the input / output circuit.

FIG. 50 is a diagram of a specific example of an output circuit.

FIG. 51 is a diagram of a specific example of an output circuit.

FIG. 52 is a diagram of a specific example of an output circuit.

FIG. 53 is a diagram of a specific example of an output circuit.

FIG. 54 is a diagram of a specific example of an input circuit.

FIG. 55 is a diagram of a specific example of an input circuit.

FIG. 56 is a diagram of a specific example of an input circuit.

FIG. 57 is a diagram of a specific example of an input circuit.

FIG. 58 is a diagram of a specific example of an input circuit.

FIG. 59 is a diagram of a specific example of an input circuit.

FIG. 60 is a diagram of a specific example of an input circuit.

FIG. 61 is a diagram of a specific example of the input protection element.

FIG. 62 is a diagram of a specific example of the input protection element.

FIG. 63 is a diagram of a specific example of the input protection element.

[Explanation of symbols]

1 ... LSI chip, 5 ... Internal circuit part, 6 ... Voltage conversion circuit, 7 ... Input / output circuit, 8 ... Information holding state detection circuit, 9 ...
Reference voltage generation circuit, 10 ... Limiter enable signal generation circuit, 11 ... External input / output bus, 12 ... Internal input / output bus.

Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 27/092 G11C 11/34 354Z 27/10 461 (56) Reference JP-A-2-122726 (JP, A) JP-A-62-125713 (JP, A) JP 56-138335 (JP, A) JP 58-20034 (JP, A) JP 3-34722 (JP, A) JP 3-60218 (JP, A) Kai 61-24090 (JP, A) JP 60-167523 (JP, A) JP 60-48525 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03K 19 / 0948 G11C 11/407 G11C 11/412 G11C 11/417 H01L 21/8238 H01L 27/092 H01L 27/10 461

Claims (6)

(57) [Claims] 1. A first including a plurality of first complementary MOSFETs.
A semiconductor device having a circuit block and a second circuit block including a plurality of second complementary MOSFETs, wherein the plurality of first complementary MOSFs of the first circuit block are provided.
The threshold voltages of the P-channel MOSFET and the N-channel MOSFET included in ET are the P-channel M of the plurality of second complementary MOSFETs of the second circuit block.
Lower than the threshold voltage of the OSFET and the N-channel MOSFET, and the first complementary MOSFET is the first complementary MOS
Set the gate-source voltage of either the P-channel MOSFET or N-channel MOSFET included in the FET to 0
When V is set, MOSF flows through the source / drain path a current larger than the current that can be regarded as almost zero in circuit operation.
A semiconductor device formed by ET. 2. The second complementary MOS according to claim 1.
Set the gate-source voltage of either the P-channel MOSFET or N-channel MOSFET included in the FET to 0
When V is set, MOSF flows through the source / drain path a current smaller than the current that can be regarded as almost zero in circuit operation.
A semiconductor device formed by ET. 3. The current which can be regarded as substantially zero in the circuit operation according to claim 1 or 2,
For each of the T and N-channel MOSFETs, the gate width is converted to 1 nA per micron.
A semiconductor device, which is characterized by a degree. 4. The semiconductor device according to claim 1, wherein the operating voltage is a voltage of about 0.5 to 1V. 5. The semiconductor device according to claim 1, wherein the semiconductor device is a microprocessor LSI chip. 6. The semiconductor device according to claim 1, wherein the semiconductor device is an LSI chip including a dynamic memory.