JP2972384B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to an MO used for high-speed data output.
The present invention relates to a semiconductor memory device including an S dynamic memory cell.

[0002]

2. Description of the Related Art A conventional semiconductor memory device of this type includes:
With the advance of microfabrication technology, the degree of integration has been improved. In particular, in a dynamic memory device, the structure of the memory cell is simple, so that high integration is possible and there is an advantage of low cost. In addition, the speed of data output has been improved with higher integration. However, since the memory cells are of a dynamic type, it is necessary to refresh the memory cells even during standby, and there is a problem that external control becomes complicated. In order to solve this problem, a semiconductor memory device that incorporates an internal refresh circuit and automatically refreshes at standby time has been developed. A semiconductor memory device that can operate also has been developed.

FIG. 5 is a circuit diagram showing a typical memory cell section included in a conventional semiconductor memory device. As the configuration, a V _cc / 2 generating circuit 1 for applying a fixed potential level to one electrode of the dynamic type cell 11 is used.
2, the dynamic cell 11 and the other electrode of the dynamic cell 11 and the bit line 2015
And the NMOS transistor 10 whose gate is connected to the word line 202.

In FIG. 5, in a steady state operation state,
Since the breakdown voltage level between the electrodes of the dynamic cell 11 is low, a fixed voltage of V _cc / 2 is supplied to the dynamic cell 11 correspondingly. For this reason, in the steady operation state, a constant current is always supplied from the _Vcc / 2 generation circuit 12 to the dynamic cell 11.
Is flowing into

[0005]

In the above-mentioned conventional semiconductor memory device, a constant current is constantly supplied from the _Vcc / 2 generation circuit 12 at all times during normal operation, regardless of whether data is fetched or not. There is a disadvantage that the current consumption of the V _cc / 2 generation circuit 12 is stabilized due to the current flowing into the mold cell 11.

[0006]

According to the semiconductor memory device of the present invention, at least a memory cell section, a refresh timer, a timing generation circuit, and a _Vcc / 2 generation circuit (V
_CC is formed to include a power supply voltage), the data holding mode
The low-potential data holding mode and the normal data holding mode.
In the semiconductor memory device including a dynamic cell having a over de, one electrode, connected to the Dainamiggu type cell voltage level of the fixed than the predetermined node N ₁ is given, a drain to the other electrode of said dynamic cell And a first NMO having a source connected to a predetermined bit line and a gate connected to a predetermined word line.
And S transistors are drain respectively connected to the node N _1, together with the power supply voltage V _CC is supplied to the source, the data holding mode of the gates said low potential
In the first and second PMOS transistors and the third and fourth clock is input to the output is activated from the timing generation circuit and a drain connected to each of the nodes N _1, the source V V _CC / 2 output from the _CC / 2 generation circuit is supplied, and the first and second clocks activated and output from the timing generation circuit are output to the gates in the normal data holding mode. And a second and a third NMOS transistor to be inputted.

[0007]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a memory cell section included in the first embodiment of the present invention. As shown in FIG. 1, the memory cell unit according to the present embodiment includes a refresh timer 1 for outputting a clock 102, clocks 101 and
2 and 103, the clocks 104, 105, 1
06 and 107 in response to V _cc / 2 generating circuit 9 which generates and outputs timing generation circuit 2 and V _cc / 2 and outputs the activating give a voltage level of the fixed from the node N ₁ in one electrode And a NMOS transistor 7 having a drain connected to the other electrode of the dynamic cell 7, a source connected to the bit line 201, and a gate connected to the word line 202, and a drain connected to the node, respectively. is connected to N _1, its source is connected to the node N _2, and NMOS transistors 3 and 4, each clock 104 and 105 is input to the gate, drain respectively connected to the node N _1, the power supply voltage V to the source _cc is supplied,
PMOS transistors 5 and 6 whose gates receive clocks 106 and 107, respectively, are provided. Note that the NMOS transistors 3 and 4 and the PMO
The transistor size including the S transistors 5 and 6 is
The size of the NMOS transistor is set to be larger in the order of the NMOS transistor 4 and the NMOS transistor 3, and the size of the PMOS transistor is set to PM
The size is set to be larger in the order of the OS transistor 6 and the PMOS transistor 5.

FIG. 2 (a), (b),
(C), (d), (e), (f), (g), (h) and (i) are timing diagrams of each signal in the present embodiment.

Hereinafter, FIGS. 1 and 2 (a), 2 (b),
The operation of this embodiment will be described with reference to (c), (d), (e), (f), (g), (h), and (i).

Normal data holding mode (in FIG. 2,
In mode A), the clock 102 is activated in response to the refresh request,
4, 105, 106 and 107 are all the power supply voltage V
_cc level. The clock 103 is at the _Vcc level, and the normal data holding mode is selected.

In this state, PMOS transistors 5 and 6 are all inactive, and NMOS transistors 3 and 4 are in an activated state. The node N ₁ has a V _cc / 2 level.

In this normal data holding mode,
In response to the activation of the NMOS transistors 5 and 6,
In V _cc / 2 generating circuit 9, a current flows through the node N _2, is constantly the power is being consumed.

In FIG. 2, at time t ₁ ,
(2, wherein the mode B) data holding mode by the power supply voltage of the low potential when is selected, after the drop of _the power supply voltage V _cc at time t _2, the clock 103 the time t ₃ when selecting the mode of operation Activated in
Next, clocks 104 and 105 are deactivated.
Then, the clock 1 is in synchronization with the toggles of the clock 102 to a refresh request, at time t _4, respectively
06, also the clock 107 at time t ₅ are activated. In this case, the PMOS transistor 5
And 6, by activating the person successively smaller transistor sizes, the potential of the node N ₁ is set to V _cc level.

Clock 103 is deactivated at time t _{6. If} this operation mode is not selected, clocks 106 and 107 are all deactivated at time t ₆ , and PMOS transistors 5 and 6 are inactive. Be transformed into Thereafter, in synchronism with the toggle of the clock 102 that issues the refresh request, at time t ₇ and time t ₈ , the NMO of the small transistor size is
S transistors 3 and 4 are sequentially activated in this order.

In this manner, the level of the cell counter electrode is gradually changed to enhance the capability against voltage fluctuation, and V _cc / 2
By avoiding the use of the generation circuit 9 in the data holding mode with a low potential power supply voltage, the current consumption thereof is reduced.

That is, by applying the present invention, in the low-voltage data holding mode using the low-potential power supply voltage where the breakdown voltage of the dynamic cell does not matter, the level of the fixed potential level node N ₁ is set to V via _cc / 2 generating circuit 9 by setting the power supply voltage V _R of the low potential, it is possible to reduce the current consumption.

Next, a second embodiment of the present invention will be described. FIG. 3 is a circuit diagram showing this embodiment. As shown in FIG. 3, this embodiment has a dynamic cell 8 in which _one electrode is given a fixed voltage level from a node N1. And an NMOS transistor 7 having a drain connected to the other electrode of the dynamic type cell 7, a source connected to the bit line 201, and a gate connected to the word line 202, and a drain connected to the node N
₁ and the source is the node N _2, and the clocks 104 and 105 are input to the gate, respectively.
S-transistors 3 and 4, PMOS transistors 5 and 6 having drains at node N ₁ , power supply voltage V _ss supplied to the source, and clocks 106 and 107 input to the gate, and node N ₂
And V _cc / 2 generating circuit 9 connected to a refresh timer 1 to output the control clock 102, input the clock 101, 102 and 103, the clock 1
04, 105, 106, and 107. The size of the transistor including the NMOS transistors 3 and 4 and the PMOS transistors 5 and 6 is set larger in the order of the NMOS transistor 4 and the NMOS transistor 3 for the NMOS transistor.
Regarding the transistors, the PMOS transistors 6, P
The size is set larger in the order of the MOS transistors 5. 4 (a), (b), (c), (d),
(E), (f), (g), (h) and (i) are timing diagrams of each signal in the present embodiment. This embodiment is different from the first embodiment in that the power supply voltage supplied to the drains of the PMOS transistors 5 and 6 is V _ss at the ground level instead of V _cc .

In this embodiment, as in the case of the first embodiment, the effect of reducing current consumption can be obtained in the data holding mode using a low potential power supply voltage.

[0020]

As described above, according to the present invention, in the data holding mode using the low potential power supply voltage, _Vcc / 2
Since the use of the generation circuit is not required, the current consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a memory cell unit according to a first embodiment of the present invention.

FIG. 2 is a timing chart of each signal showing the operation of the memory cell unit of the first embodiment.

FIG. 3 is a circuit diagram showing a memory cell unit according to a second embodiment of the present invention.

FIG. 4 is a timing chart of each signal showing the operation of the memory cell unit of the second embodiment.

FIG. 5 is a circuit diagram showing a memory cell section of a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Refresh timer 2 Timing generation circuit 3, 4, 7, 10 NMOS transistor 5, 6 PMOS transistor 8, 11 Dynamic-type cell 9, 12, 1/2 _Vcc generation circuit

Claims (1)

(57) [Claims] 1. A least, the memory cell unit, a refresh timer, the timing generator and V _CC / 2 generating circuit (V _CC is the supply voltage) is formed to include a data holding
Modes include low-potential data retention mode and normal data
In semiconductor <br/> body memory device including a dynamic cell having a data holding mode, the one electrode, and Dainamiggu type cell voltage level of the fixed than the predetermined node N ₁ is given, the drain is the dynamic A first NMO connected to the other electrode of the cell, a source connected to a predetermined bit line, and a gate connected to a predetermined word line;
Each of the S transistors has a drain connected to the node N ₁ , a source supplied with a power supply voltage V _CC , and a gate connected to each of the S transistors.
In the low-potential data holding mode, first and second PMOS transistors to which third and fourth clocks activated and output from the timing generation circuit are input, and drains of which are connected to the node N ₁ , respectively. And the source is supplied with V _cc / 2 output from the V _cc / 2 generating circuit, and the gate is supplied with the normal data holding signal.
In the mode, the first and second clocks activated and output from the timing generation circuit are input.
And a third NMOS transistor.