JPH0235397B2 - - Google Patents

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to pseudo-static memory.

[Prior art]

The degree of integration of semiconductor memories has been improved along with advances in microfabrication technology. In particular, dynamic memory has the advantage of having a simple memory cell structure, allowing for high integration and low cost.
However, since the memory cells are dynamic circuits, the contents of the memory cells have to be refreshed even during standby, making the external control system complicated. In order to improve this drawback, pseudo-static memories have been developed that incorporate internal refresh circuits and automatically perform refresh during standby.

The internal refresh modes of the pseudo static memory include a pulse refresh mode in which refresh is performed automatically by applying a clock pulse, and a self-refresh mode in which refresh is performed automatically at a fixed period determined by a timer circuit by keeping the clock pulse low. There is a Tsushiyu mode. Although the timer cycle during self-refresh needs to be shorter than the refresh cycle of the memory cell, the refresh cycle is still long, so the current required for refresh is small. However, in pseudo-static memory with a built-in substrate voltage generation circuit,
Since the substrate voltage generation circuit needs to have the ability to absorb the substrate current generated during the minimum operating cycle, the current consumed by the substrate voltage generation circuit does not decrease in self-refresh mode, but instead accounts for a large proportion of the total current. There are drawbacks.

This drawback will be explained in more detail below using the drawings.

FIG. 1 is a circuit diagram of an example of a substrate voltage generating circuit used in an example of a conventional pseudo static memory. A three-stage inverter oscillation section consisting of transistors Q ₁ to Q ₆ , transistors Q ₇ and Q ₈ , and a capacitor C ₁
It consists of a charge pump section.
Transistors Q ₁ , Q ₃ , Q ₅ are P-channel MOS transistors, and transistors Q ₂ , Q ₄ , Q ₆ , Q ₇ , Q _{8 are} P-channel MOS transistors.
indicates an N-channel MOS transistor. The oscillation period of the substrate voltage generation circuit must be set short so that the pseudo static memory can absorb the substrate current generated during the minimum operation cycle.
As a result, during self-refreshing, even though the timer period becomes longer and the current required for refreshing decreases, the current consumed by the substrate voltage generation circuit does not decrease because its oscillation period remains short.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a pseudo static memory having a substrate voltage generation circuit which reduces current consumption during self-refresh by eliminating the above-mentioned drawbacks.

[Structure of the invention]

The pseudo-static memory of the present invention has a control circuit that controls the substrate voltage generation circuit to be driven by an internal clock during normal operation and by an external clock during refresh. It consists of

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a circuit diagram showing a substrate voltage generation circuit used in one embodiment of the present invention.

An oscillation section consisting of three stages of inverters consisting of transistors Q ₁ to _{Q 6} , a charge pump section consisting of transistors Q ₇ and Q ₈ and a capacitor C ₁ , and transistors Q ₉ and Q _10.
an input buffer section consisting of transistors Q ₁₁ ~
It consists of a switch section consisting of ₁₄ Q. Transistors Q ₁ , Q ₃ , Q ₅ , Q ₉ , Q ₁₁ , Q ₁₃ are P-channel MOS transistors, transistors Q ₂ ,
Q ₄ , Q ₆ , Q ₇ , Q ₈ , Q ₁₀ , Q ₁₂ , Q ₁₄ are N channels
Shows a MOS transistor.

That is, the substrate voltage generation circuit used in this embodiment includes a control circuit 1 consisting of an input buffer section and a switch section in addition to the conventional substrate voltage generation circuit shown in FIG.
1 is added to the input of the input buffer section, and the external clock signal _φ1 is also connected to the switching transistor.
The internal clock signal _φ2 or _φ2 is connected to the gates of _Q11 to _Q14 , respectively.

Next, its operation will be explained. During normal operation, the internal clock _φ2 is at a low level, switching transistors _Q11 and _Q12 are turned on, and the charge pump section is driven by the output of the oscillation section. During self-refresh, the internal clock _φ2 becomes high level, switching transistors _Q13 and _Q14 are turned on, and the external clock _φ1 drives the charge pump section. During self-refresh, the timer period becomes longer and the substrate current decreases, so the period of the external clock _φ1 can be lengthened, and the current consumed by the substrate voltage generation circuit can be reduced.

Note that although the above description has been made regarding the case of a CMOS circuit, it is also possible to configure the circuit using only N-channel transistors or P-channel transistors.

〔Effect of the invention〕

As described above in detail, the pseudo static memory of the present invention has a control circuit that controls the substrate voltage generation circuit to be driven by an internal clock during normal operation and by an external clock during refresh. This has the effect that the period of the external clock can be made longer in accordance with the timer period, thereby reducing the current consumption in the substrate voltage generating circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an example of a substrate voltage generation circuit used in an example of a conventional pseudo static memory.
FIG. 2 is a circuit diagram of a substrate voltage generation circuit used in one embodiment of the present invention. 11...Control circuit, Q ₁ , Q ₃ , Q ₅ , Q ₉ , Q ₁₁ ,
Q ₁₃ ... P channel MOS transistor, Q ₂ , Q ₄ ,
Q ₆ , Q ₇ , Q ₈ , Q ₁₀ , Q ₁₂ , Q ₁₄ ...N channel
MOS transistor, _C1 ...Capacitance, _φ1 ...External clock signal, _φ2 , ₂ ...Internal clock signal.

Claims (1)

[Claims] 1. A pseudo-static memory with a built-in substrate voltage generation circuit, characterized in that it has a control circuit that controls the substrate voltage generation circuit to be driven by an internal clock during normal operation and by an external clock during refresh. memory.