JP3358248B2 - Dynamic RAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory cell for recording data depending on whether or not electric charges are stored in a capacitor.
Semiconductor memory device provided with so-called dynamic memory cells, so-called dynamic RAM
(Dynamic Random Access Memory.
In particular, the present invention relates to a DRAM capable of performing an effective self-refresh operation when used when the battery is backed up.

[0002]

2. Description of the Related Art FIG. 19 shows a block diagram of a conventional DRAM.

In the figure, reference numeral 1 denotes a memory cell array section in which memory cells are arranged, 2 denotes one of the memory cells arranged in the memory cell array section 1, 3 denotes a capacitor for storing electric charges, and 4 denotes a capacitor. An enhancement type nMOS transistor forming a transfer gate, WL is a word line, and BL is a bit line.

An address buffer / predecoder unit 5 includes an address buffer for receiving an externally supplied address signal and a predecoder for predecoding a row address signal among the address signals received by the address buffer. .

A row decoder 6 decodes a predecode signal output from the predecoder of the address buffer / predecoder section 5 to select and drive a word line.

A column decoder 7 decodes a column address signal output from the address buffer of the address buffer / predecoder section 5 and outputs a column selection signal for selecting a column.

Reference numeral 8 denotes a sense amplifier circuit row for amplifying data read from the memory cell array unit 1, and 9 denotes an I / O gate for selecting a column based on a column selection signal output from a column decoder 7. is there.

Reference numeral 10 denotes output data DO1 to DO for latching data read from the memory cell array unit 1.
Reference numeral / OE denotes an output enable signal for controlling output supplied from the outside.

Reference numeral 11 denotes a data input buffer for receiving write data input from the outside, 12 a write clock generator for outputting a write clock signal for controlling the operation of the data input buffer 11, and / WE a supply from the outside. This is a write enable signal for controlling the writing to be performed.

Reference numeral 13 denotes a substrate bias generator for generating a substrate bias voltage;
This is a refresh address counter that outputs an address signal.

Reference numeral 15 denotes a self-refresh circuit required for performing self-refresh, 16 denotes an oscillator, 17 denotes a substrate bias generator, 18 denotes a timing circuit, 19 denotes a frequency dividing circuit, and 20 denotes an AND circuit. .

Also, / RAS is an externally supplied row address strobe signal, / CAS is an externally supplied column address strobe signal, 21 is a row decoder 6, a sense amplifier circuit row 8, and a substrate bias generator 13. It is a clock generator that outputs a clock signal necessary for such as.

Reference numeral 22 denotes a clock generator for outputting clock signals necessary for the address buffer of the address buffer / predecoder section 5, the column decoder 7, the write clock generator 12, and the like.

A mode controller 23 controls an operation mode.
Determines the CBR (CAS before RAS) refresh mode from the clock signal output from the clock generator 21 and the column address strobe signal / CAS, the CBR refresh mode signal φ
_{The CBR} is transmitted to the self refresh circuit 15.

VCC is an external power supply voltage supplied from the outside, for example, 3.3 [V], and VSS is a ground voltage supplied from the outside, 0 [V].

FIG. 20 is a waveform diagram showing a normal operation mode of the DRAM. After the row address strobe signal / RAS transitions from H level (high level) to L level (low level), the column When the address strobe signal / CAS transitions from the H level to the L level, a normal operation mode such as a read cycle is executed.

FIG. 21 is a diagram showing the self-operation of this DRAM.
FIG. 13 is a waveform diagram showing a refresh mode, in which a column address strobe signal / CA is changed before a row address strobe signal / RAS transitions from H level to L level.
When S transitions from the H level to the L level, the mode is the CBR refresh mode.

This state is, for example, 100 μm.
When maintained for a period of s, the mode shifts to a self-refresh mode, for example, a self-refresh operation is performed at intervals of 16 μs.

Note that φ _OSC is a signal output from the oscillator 16, and φ _SR is a signal output from the AND circuit 20 that regulates a self-refresh cycle.

In this DRAM, the external power supply voltage VCC supplied from the outside is supplied to the internal circuit not only in the normal operation mode but also in the self-refresh mode.

For this reason, the current consumption is increased, and when used in a portable device such as a laptop personal computer, there is a problem that the usable time of the backup battery is shortened. Was.

Therefore, conventionally, as shown in FIG. 22, a step-down circuit 25 is provided, and a self-refresh circuit 1 is provided.
Step-down voltage VI obtained by stepping down power supply voltage VCC with respect to
A method has been proposed for supplying I to reduce power consumption.

The level conversion circuit 26 provided in the self-refresh circuit 15 is provided with a self-refresh cycle signal φ _SR output from the AND circuit 20.
H level of VII level (step-down voltage level) to VCC
It is converted to the H level of the level (external power supply voltage level).

[0024]

The DR shown in FIG.
According to AM, it is possible to reduce the current consumption of the self-refresh circuit 15 to reduce the power consumption. However, such a reduction in the power consumption requires a laptop personal computer or the like. It is not sufficient for use in portable devices, and further reduction in power consumption is required.

In view of the above, the present invention aims to further reduce the power consumption and extend the usable time of the backup battery when used in a portable device such as a laptop personal computer. Can be
It is an object of the present invention to provide a DRAM capable of improving the convenience of such a portable device.

[0026]

SUMMARY OF THE INVENTION A DRAM according to the present invention
Include a plurality of dynamic memory cells, a data read / write circuit for reading / writing data, a self refresh circuit for self refreshing data held in the plurality of memory cells, and a data read / write circuit and a self refresh circuit. The present invention is to improve a dynamic RAM having a power supply voltage supply circuit for supplying a power supply voltage. -It is configured to supply the data to the refresh circuit.

[0027]

In the present invention, the power supply voltage supply circuit supplies a lower power supply voltage in the self refresh mode than in the normal operation mode to the data read / write circuit and the self-refresh circuit.
It is configured to supply to both circuit parts of the refresh circuit.

As a result, in the self refresh mode, only the self refresh circuit is supplied with a lower power supply voltage than in the normal operation mode.
Compared with the RAM, more current consumption can be reduced.

Therefore, according to the present invention, the power consumption can be further reduced, and when it is used in a portable device such as a laptop personal computer, the usable time of the backup battery is extended. be able to.

Further, according to the present invention, since the power consumption can be reduced more than in the conventional example, the operating environment such as noise in the chip can be improved more than the conventional example. In addition, the refresh cycle can be made longer than in the case of the conventional example, and from this point as well, the power consumption can be reduced.

In writing and reading, if a voltage higher than the power supply voltage supplied to the peripheral circuit is supplied to the selected word line, the data of "1" This configuration is preferable because sufficient writing or sufficient reading of data "1" can be performed.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment , a second embodiment, a first reference example, and a second reference example of the present invention will be described below with reference to FIGS. 1 and 13, parts corresponding to those in FIG. 19 are denoted by the same reference numerals, and redundant description is omitted.

First Embodiment FIGS. 1 to 5 FIG. 1 is a block diagram showing a main part of a first embodiment of the present invention. In the present embodiment, a power supply voltage supply circuit 28 is provided, and the rest is configured similarly to the conventional DRAM shown in FIG.

The power supply voltage supply circuit 28 supplies an external power supply voltage VCC externally supplied to an internal circuit in a normal operation mode, and a reduced voltage obtained by reducing the external power supply voltage VCC in a self refresh mode. VII
Is supplied to the internal circuit.

In the normal operation mode, however, a voltage higher than the external power supply voltage VCC is supplied to the selected word line via a booster circuit (not shown), and
Even in the refresh mode, a voltage higher than the step-down voltage VII is supplied to the selected word line via the booster circuit.

FIG. 2 is a circuit diagram showing a part of the memory cell array unit 1. In the figure, reference numeral 30 denotes a bit line precharge voltage generating circuit used in the normal operation mode, 31 denotes a VCC power supply line for supplying an external power supply voltage VCC, and 32 and 33 denote resistors having the same resistance value.

That is, the bit line precharge voltage generating circuit 30 sets the bit line precharge voltage VP1 to a node 34, which is a connection point between the resistors 32 and 33, as 1
/ 2 · VCC.

Reference numeral 35 denotes a switching element which is turned on (conducting) in the normal operation mode and turned off (non-conducting) in the self-refresh mode.

Reference numeral 36 denotes a bit line precharge voltage generation circuit used in the self-refresh mode. Reference numeral 37 denotes a VII power supply line for supplying a step-down voltage VII.
38 and 39 are resistors.

This bit line precharge voltage generating circuit 3
6 is a node 40 which is a connection point between the resistor 38 and the resistor 39.
To obtain the precharge voltage VP2,
The resistance ratio of the resistors 38 and 39 is determined such that VP2 = VII-1 / 2.VCC.

A switch element 41 is turned off in the normal operation mode and turned on in the self-refresh mode.

Reference numeral 42 denotes a bit line precharge circuit. Reference numerals 43, 44, and 45 denote enhancement type nMOS transistors whose on and off are controlled by a bit line precharge control signal PC. Is one sense amplifier.

When the bit line is precharged in the normal operation mode, the switch element 35 is turned on, the switch element 41 is turned off, and the bit line precharge control signal P
C = H level, nMOS transistors 43, 44, 45
= ON, and the bit lines BL and / BL are precharged to the bit line precharge voltage VP1 = １ ／ · VCC.

When the bit line is precharged in the self-refresh mode, the switching element 35
= Off, switch element 41 = on, bit line precharge control signal PC = H level, nMOS transistor 4
3, 44, 45 = ON and bit lines BL, / BL
Is the bit line precharge voltage VP2 = VII-1 / 2
-Precharged to VCC.

FIG. 3 shows the bit line precharge voltage VP1 = １ ／ · VCC in the normal operation mode and the bit line precharge voltage VP2 in the self refresh mode.
= VII-1 / 2.VCC.

As is apparent from FIG. 3, the voltage used as a reference for the logic judgment of the data read from the memory cell in sense amplifier 46, that is, the so-called logic judgment reference voltage is 1 / 2.VCC in the normal operation mode. In the self refresh mode, VII-1 / 2.
VCC.

Incidentally, when the resistors 38 and 39 of the bit line precharge voltage generating circuit 36 have the same resistance value, the bit line precharge voltage VP2 in the self refresh mode is 1/2 ・ VII.

FIG. 4 shows the bit line precharge voltage VP1 = 1 / 2.VCC in the normal operation mode when the resistors 38 and 39 have the same resistance value, and the bit in the self refresh mode. Line precharge voltage VP2
= 1/2 ・ VII.

As is apparent from FIG.
When 39 has the same resistance value, the logic judgment reference voltage in the normal operation mode is 1/2 · VCC, but the logic judgment reference voltage in the self refresh mode is 1/2 · VII.

In the first embodiment, the power supply voltage supply circuit 28 supplies the external power supply voltage VCC to the internal circuit in the normal operation mode, and supplies the reduced voltage VII to the internal circuit in the self-refresh mode. It is configured to supply to.

Therefore, according to the first embodiment, step-down voltage VII is supplied only to self-refresh circuit 15 in the self-refresh mode.
9, the power consumption can be reduced as compared with the conventional DRAM shown in FIG. 9, and when the first embodiment is used for a portable device such as a laptop personal computer,
The convenience of such a portable device can be improved.

Further, according to the first embodiment, since the power consumption can be reduced more than in the conventional example, the operating environment such as noise in the chip can be improved more than in the conventional example. Therefore, the refresh cycle can be made longer than in the conventional example, and from this point as well, the power consumption can be reduced.

In the first embodiment, the logic judgment reference voltage V in the self-refresh mode is set.
_{To set REFS} to VII-1 / 2 · VCC,
In the refresh mode, the voltages of the bit lines BL and / BL are precharged to VII-1 / 2.VCC.

As a result, when the H level (“1”) is written in the capacitor 3, the potential of the cell node 47 when the memory cell 2 is selected, the potentials of the bit lines BL and / BL, and the logic The relationship with the determination reference voltage is as shown in FIG. 5A. FIG. 5B shows the potential of the word line WL.

Therefore, for example, even if the potential of the cell node 47 becomes lower than VII due to radiation (α ray), the potential of the cell node 47 becomes VII-1.
If it is higher than / 2 · VCC, the data of the memory cell 2 can be logically determined by the sense amplifier 46.

As described above, according to the first embodiment, the logic error reference voltage in the self-refresh mode is set to VII-1 / 2.VCC, thereby improving the soft error withstand voltage. be able to.

[0057] (first reference example .. Figure 6-10) Figure 6 is a circuit diagram showing an essential part of the first embodiment of the present invention,
In the first reference example , the memory cell array unit 1 shown in FIG. 1 is configured as shown in FIG. 6 with a part thereof, and the other configuration is the same as that of the first embodiment shown in FIG.

In FIG. 6, reference numeral 49 denotes a bit line precharge voltage generating circuit. Reference numeral 50 denotes a VCC / VII power supply line for supplying an external power supply voltage VCC in a normal operation mode and supplying a reduced voltage VII in a self refresh mode. , 51 and 52 are resistors having the same resistance value.

That is, in the normal operation mode, the bit line precharge voltage generation circuit 49 obtains 1 / 2.VCC as a bit line precharge voltage at the node 53 which is a connection point between the resistors 51 and 52, and performs self refresh. In the mode, the bit line precharge voltage is 1 / 2V
II.

Also, 54 and 55 are bit lines BL and / BL
, A capacitor for setting the
_REFS is a logic judgment reference voltage setting signal for setting the bit lines BL and / BL to a logic judgment reference voltage.

FIG. 7 is a waveform diagram for explaining the operation in the self-refresh mode of the first reference example , and shows, for example, a case where memory cell 2 is selected. 7A is the potential of the cell node 47, the bit line B
7B shows the logic determination reference voltage setting signal φ _REFS , and FIG. 7C shows the potential of the word line WL.

That is, in the first reference example , the bit lines BL and / BL are set to 1 in the self refresh mode.
/ VII · VII, and then the logic determination reference voltage setting signal φ _REFS is changed from H level to L level.

As a result, the potentials of the bit lines BL and / BL are reduced to a voltage VD lower than the bit line precharge voltage of ・ · VII via the capacitors 54 and 55, and this voltage VD is This is used as a judgment reference voltage.

Thereafter, the word line WL = H level, nMO
The S transistor 4 is turned on, the data of the memory cell 2 is read, the potential of the bit line BL rises from the logic determination reference voltage VD, and the bit line / BL becomes the logic determination reference voltage V
D is maintained, and the potential difference between these bit lines BL and / BL is sensed by the sense amplifier 46.

Since the power supply voltage supply circuit 28 is provided also in the first reference example , the external power supply voltage V is set in the normal operation mode as in the first embodiment.
CC can be supplied to the internal circuit, and in the self refresh mode, the reduced voltage VII can be supplied to the internal circuit.

[0066] Thus, even with this first reference example,
Self-refresh mode, only the self-refresh circuit 15, can also reduce the power consumption than the conventional DRAM shown in FIG. 19 that supplies the step-down voltage VII, laptop the first reference example When used in portable devices such as portable personal computers, the convenience of such portable devices can be improved.

[0067] Also, by the first reference example, in this way, since it is possible to reduce the above conventional example of the power consumption, is possible to improve the operating environment such as noise in the chip over the prior art Thus, the refresh cycle can be made longer than in the conventional example, and from this point as well, the power consumption can be reduced.

In the first reference example , the logic determination reference voltage is 1 in the self refresh mode.
Since the voltage VD is lower than / 2 · VII, the soft error withstand voltage can be improved as in the case of the first embodiment.

It should be noted that VCC / VII power supply line 50 shown in FIG. 6 may be configured to supply only external power supply voltage VCC without providing power supply voltage supply circuit 28.

[0070] In this case, the logic determination reference voltage V _REFS1 in the normal operation mode, the relationship between the logical decision reference voltage V _REFS2 in the self-refresh mode, as shown in FIG.

That is, when the VCC / VII power supply line 50 shown in FIG. 6 is configured to supply only the external power supply voltage VCC without providing the power supply voltage supply circuit 28, the logic in the self-refresh mode is set. Since the judgment reference voltage V _REFS2 can be set to a voltage lower than ・ · VCC, it is not possible to reduce the power consumption. However, as in the first embodiment, the soft error withstand voltage is improved. You can do it.

FIG. 9 shows that the power supply line 50 shown in FIG.
FIG. 10 is a diagram showing a potential change of a cell node 47 when configured to supply only CC.

Here, since the logic judgment reference voltage V _REFS2 in the self refresh mode is set to a voltage lower than ・ · VCC, it is not necessary to perform the refresh at the time TA, but to perform the refresh at the time TA. It is enough to go with TB.

Therefore, in such a case, the self-refresh cycle can be set to, for example, 32 μs, which is twice the conventional case (16 μs), as shown in FIG.

[0075] (second reference example ... 11, 12) Figure 11 is a circuit diagram showing an essential portion of the second reference example of the present invention, the second reference example, the memory cell array portion shown in FIG. 1 1 is configured as shown in FIG. 11 and a portion is configured similarly to the first embodiment shown in FIG.

The second reference example is an improvement of the first reference example shown in FIG. 6. In the second reference example , the setting of the logic judgment reference voltage for the bit lines BL and / BL is performed. , Bit line BL is determined by a logic determination reference voltage setting signal φ _REFS2 via a capacitor 54, and bit line / BL is determined by a logic determination reference voltage setting signal φ _REFS1 via a capacitor 55. .

FIG. 12 is a waveform diagram for explaining the operation in the self-refresh mode of the second reference example , and shows, for example, a case where memory cell 2 is selected. 12A is a cell node 47 when the memory cell 2 stores the H level ("1").
, The potentials of the bit lines BL and / BL, and the logic determination reference voltage VD.

FIG. 12B is a logic judgment reference voltage setting signal φ _REFS1 , and FIG. 12C is a logic judgment reference voltage setting signal φ.
_REFS2 , FIG. 12D shows the potential of the word line WL, and FIG. 12E shows the potential of the cell node 47, the potential of the bit lines BL and / BL, and the logic determination reference voltage when the memory cell 2 stores the L level (“0”). VD is shown.

That is, in the second reference example , in the self-refresh mode, when the logic determination reference voltage setting signals φ _REFS1 and φ _REFS2 = “H”, the bit line B
L and / BL are precharged to 1 / 2.VII.

Thereafter, logic determination reference voltage setting signal φ
_REFS1 is changed from H level to L level, logic determination reference voltage setting signal φ _REFS2 maintains “H”, and bit line / BL
Is lowered to a voltage VD lower than ・ · VII via a capacitor 55, this voltage VD is used as a logic judgment reference voltage, and the potential of the bit line BL is reduced to １ ／.
-Maintained at VII.

Thereafter, the word line WL = H level, nMO
The S transistor 4 is turned on, the data of the memory cell 2 is read, and the potential of the bit line BL rises from １ ／ · VII which is the bit line precharge voltage, and the bit line /
BL maintains the logic determination reference voltage VD, and the potential difference between these bit lines BL and / BL is sensed by the sense amplifier 46.

When a memory cell connected to bit line / BL, for example, memory cell 2A is selected, logic determination reference voltage setting signal φ _REFS2 is changed from H level to L level, and logic determination reference The voltage setting signal φ _REFS1 maintains “H”, and the potential of the bit line BL is
To a voltage VD lower than 1 / 2.VII, this voltage VD is used as a logic judgment reference voltage, and the potential of the bit line / BL is maintained at 1 / 2.VII.

Since the power supply voltage supply circuit 28 is also provided in the second reference example , the external power supply voltage V is set in the normal operation mode as in the first embodiment.
CC can be supplied to the internal circuit, and in the self refresh mode, the reduced voltage VII can be supplied to the internal circuit.

[0084] Thus, even with this second reference example,
Self-refresh mode, only the self-refresh circuit 15, can also reduce the power consumption than the conventional DRAM shown in FIG. 19 that supplies the step-down voltage VII, laptop the second reference example When used in portable devices such as portable personal computers, the convenience of such portable devices can be improved.

[0085] Further, by the second reference example, in this way, since it is possible to reduce the above conventional example of the power consumption, is possible to improve the operating environment such as noise in the chip over the prior art Thus, the refresh cycle can be made longer than in the conventional example, and from this point as well, the power consumption can be reduced.

In the second reference example , the logic determination reference voltage is 1 in the self refresh mode.
Since the voltage VD is lower than / 2 · VII, the soft error withstand voltage can be improved as in the case of the first reference example .

Note that also in the second reference example , the first reference
As in the case of the conventional example, without providing the power supply voltage supply circuit 28, the power supply line 50 shown in FIG.
A configuration in which only C is supplied is also possible.

[0088] In this case, the self-refresh mode can not be reduced in power consumption, as in the first embodiment, it is possible to improve the soft error withstand voltage, self・ Refresh cycle
For example, as shown in FIG.
s), that is, 32 μs, which is twice as large as that of s).

[0089] (Second Embodiment ... view 13 to 18) FIG. 13 is a block diagram showing an important part of a second embodiment of the present invention, the second embodiment is provided with a power supply voltage supply circuit 57 The other configuration is the same as that of the conventional DRAM shown in FIG.

Power supply voltage supply circuit 57 supplies a reduced voltage VIIA obtained by stepping down external power supply voltage VCC to the internal circuit in the normal operation mode, and lowers external power supply voltage VCC in the self refresh mode. In this case, a reduced voltage VIIB lower than the reduced voltage VIIA is supplied to the internal circuit.

In the normal operation mode, a voltage higher than the step-down voltage VIIA is supplied to the selected word line via the booster circuit (not shown). A voltage higher than the step-down voltage VIIB is supplied to the selected word line via the booster circuit.

Here, the power supply voltage supply circuit 57
The block diagram is shown in FIG. In the figure,
58 generates a reference voltage V _REFA in the normal operation mode,
A reference voltage generation circuit that generates a reference voltage V _REFB lower than the reference voltage V _{REFA in the} self refresh mode.

.Phi.self is a self-refresh detection signal for controlling the reference voltage generating circuit 58, and is at the L level in the normal operation mode and at the H level during the self-refresh.

Reference numeral 59 denotes a step-down voltage VIIA obtained by stepping down the external power supply voltage VCC according to the reference voltage V _REFA output from the reference voltage generating circuit 58 in the normal operation mode.
(= V _REFA ) and the reference voltage V output from the reference voltage generating circuit 58 in the self refresh mode.
_This is a step-down circuit that generates a step-down voltage VIIB (= V _REFB ) obtained by stepping down the external power supply voltage VCC according to _REFB .

Here, the reference voltage generation circuit 58
It is configured as shown in FIG. In the figure, 61 to 64 are inverters, 65 is a NOR circuit, 66 is a long channel enhancement-type pMOS transistor, 67 to 6
9 is a normal channel enhancement type pMO
It is an S transistor.

Reference numerals 70 to 72 denote normal channel enhancement type nMOS transistors,
5 is a long channel enhancement type nMOS
Transistors, 76 to 78 are depletion type nM
OS transistor.

Here, the nMOS transistors 76 and 73
The nMOS transistor 76 is a driving transistor and n
A source follower circuit using the MOS transistor 73 as a load current source is configured.

The nMOS transistors 77 and 74
The nMOS transistor 77 is a driving transistor, and n
A source follower circuit using the MOS transistor 74 as a load current source is configured.

The nMOS transistors 78 and 75
The nMOS transistor 78 is a driving transistor and n
A source follower circuit using the MOS transistor 75 as a load current source is configured.

In reference voltage generating circuit 58, when self-refresh detection signal φself = L level,
As shown in FIG. 16, the output of the inverter 61 = H level, the output of the inverter 62 = L level,
Output = H level, output of NOR circuit 65 = L level,
The output of the inverter 64 becomes H level, and the pMOS transistors 67 to 69 are turned off.

Therefore, the enhancement type nMO
The threshold voltage of S transistors 70 to 72 is set to V
_THn , depletion type nMOS transistor 76
Assuming that a threshold voltage of ~ 78 is V _THd , in this case, V _REFA = 3V _THn +3 as the reference voltage V _REFA
| V _THd | can be obtained.

Further, self-refresh detection signal φse
In the case of lf = H level, as shown in FIG. 17, the output of the inverter 61 = L level, the output of the inverter 62 = H level, the output of the inverter 63 = L level, and the NOR circuit 65
= L level, and the output of the inverter 64 = H level.

Therefore, in this case, the pMOS transistor 67 is off, and the pMOS transistors 68 and 69
= ON, and V _REFB = 2V as the reference voltage V _REFB
THn + 2 | V _THd | can be obtained.

Note that self refresh detection signal φse
When lf changes from H level to L level, that is, when shifting from the normal operation mode to the self-refresh mode, the NOR circuit 65 generates a positive one-shot pulse.

As a result, negative one-
A shot pulse is output and the pMOS transistor 6
7 is temporarily turned on, the potential of the node 79 rapidly rises to 3V _THn , and the reference voltage is V _REFB = 2V _THn +2 |
It rapidly changes from V _THd | to V _REFA = 3V _THn +3 | V _THd |.

Therefore, when shifting from the self-refresh mode to the normal operation mode, the current required in the normal operation mode can be immediately supplied to the internal circuit, and as a result, a delay that hinders high speed operation is caused. Is prevented from occurring.

The voltage step-down circuit 59 is composed of a constant voltage circuit as shown in FIG. In the figure, reference numeral 81 denotes a differential amplifier circuit, and reference numeral 82 denotes an enhancement-type pMOS transistor forming a regulator.

In the normal operation mode, this step-down circuit 59 outputs as the step-down voltage VIIA _VREFA = _3VTHn + 3 | _VTHd |, which is the same voltage as the reference voltage _VREFA. As the voltage VIIB, V _REFB = 2 V, which is the same voltage as the reference voltage V _REFB
THn + 2 | V _THd | is output.

Here, according to the second embodiment , in the normal operation mode, external power supply voltage VC supplied from outside is used.
A step-down voltage VIIA obtained by stepping down C is supplied to the internal circuit. In the self refresh mode, a step-down voltage VIIB lower than the step-down voltage VIIA obtained by stepping down the external power supply voltage VCC is supplied to the internal circuit.

[0110] Thus, even with this second embodiment,
Self-refresh mode, only the self-refresh circuit 15, can also reduce the power consumption than the conventional DRAM shown in FIG. 19 that supplies the step-down voltage VII, laptop the second embodiment When used in portable devices such as portable personal computers, the convenience of such portable devices can be improved.

[0111] Also, with this second embodiment, like this, since it is possible to reduce the above conventional example of the power consumption, it is possible to improve the operating environment such as noise in the chip over the prior art Thus, the refresh cycle can be made longer than in the conventional example.

In the second embodiment , when the memory cell array unit 1 is configured as shown in FIG.
The logic judgment reference voltage in the self-refresh mode can be set to VIIB-1 / 2 · VIA,
In the configuration shown in FIG. 6 or FIG. 11, the logic judgment reference voltage in the self-refresh mode can be set to 1/2 ・ VII or less. The withstand voltage can be improved.

[0113]

According to the present invention, the power supply voltage supply circuit
In the self-refresh mode, the power supply voltage lower than that in the normal operation mode is supplied to both the information read / write circuit and the self-refresh circuit. As a result, when the present invention is used in a portable device such as a laptop personal computer, the usable time of a backup battery can be extended, and thus the portable device can be used. According to the present invention, since the power consumption can be reduced more than the conventional example, the operating environment such as the noise in the chip can be improved. Therefore, the refresh cycle can be made longer than in the conventional example. It is possible to achieve the reduction.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a part of a memory cell array provided in the first embodiment of the present invention.

FIG. 3 is a diagram showing a relationship between a bit line precharge voltage in a normal operation mode and a bit line precharge voltage in a self refresh mode according to the first embodiment of the present invention;

FIG. 4 is a diagram showing a bit line precharge voltage generation circuit used in a self refresh mode provided in the first embodiment of the present invention, in a normal operation mode when two resistors have the same resistance value; FIG. 4 is a diagram showing a relationship between a bit line precharge voltage and a bit line precharge voltage in a self refresh mode.

FIG. 5 is a diagram illustrating a self-refresh operation according to the first embodiment of the present invention;
FIG. 6 is a waveform chart for explaining an operation in a mode.

FIG. 6 is a circuit diagram showing a main part of a first reference example of the present invention.

FIG. 7 is a diagram illustrating a self-refresh operation according to a first embodiment of the present invention;
FIG. 6 is a waveform chart for explaining an operation in a mode.

FIG. 8 is a logic judgment criterion in a normal operation mode when the power supply line shown in FIG. 6 is configured to supply only the external power supply voltage without providing the power supply voltage supply circuit provided in the first reference example of the present invention; FIG. 5 is a diagram illustrating a relationship between a voltage and a logic determination reference voltage in a self refresh mode.

9 is a diagram showing a potential change of a cell node when the power supply line shown in FIG. 6 is configured to supply only the external power supply voltage without providing the power supply voltage supply circuit provided in the first reference example of the present invention; is there.

FIG. 10 is a waveform showing a self-refresh mode when the power supply line shown in FIG. 6 is configured to supply only an external power supply voltage without providing a power supply voltage supply circuit provided in the first reference example of the present invention; FIG.

FIG. 11 is a circuit diagram showing a main part of a second reference example of the present invention.

FIG. 12 is a waveform chart for explaining an operation in a self-refresh mode according to the second embodiment of the present invention;

FIG. 13 is a block diagram showing a main part of a second embodiment of the present invention.

FIG. 14 is a block diagram showing a power supply voltage supply circuit provided in a second embodiment of the present invention.

FIG. 15 is a circuit diagram showing a reference voltage generation circuit constituting a power supply voltage supply circuit provided in a second embodiment of the present invention.

FIG. 16 is a circuit diagram for explaining an operation of a reference voltage generation circuit constituting a power supply voltage supply circuit provided in a second embodiment of the present invention.

FIG. 17 is a circuit diagram for explaining an operation of a reference voltage generation circuit constituting a power supply voltage supply circuit provided in a second embodiment of the present invention.

FIG. 18 is a circuit diagram showing a step-down circuit constituting a power supply voltage supply circuit provided in a second embodiment of the present invention.

FIG. 19 is a block diagram showing a main part of an example of a conventional DRAM.

20 is a waveform chart showing a normal operation mode of the DRAM shown in FIG.

FIG. 21 is a waveform chart showing a self-refresh mode of the DRAM shown in FIG. 19;

FIG. 22 is a block diagram showing a main part of another example of a conventional DRAM.

[Explanation of symbols]

 15 Self-refresh circuit 28 Power supply voltage supply circuit

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Takaaki Koyama 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Prefecture Inside Fujitsu VSI Co., Ltd. (72) Mitsuhiro Nagao 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Fujitsu (72) Inventor Masahiro Niimi 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Prefecture Fujitsu VSI Inc. (56) References JP-A-1-159890 (JP, A) JP-A-3 -230389 (JP, A) JP-A-6-131876 (JP, A) JP-A-1-208793 (JP, A) JP-A-1-208794 (JP, A) (58) Fields investigated (Int. . ^7, DB name) G11C 11/40 - 11/4099

Claims (6)

(57) [Claims] A plurality of memory cells of a dynamic type; and a memory cell in a self-refresh mode .
A voltage lower than a half of a power supply voltage, which is a writing voltage, is supplied to a pair of first and second bit lines used for reading data from the memory cell, and the first and second bit lines are supplied. 2
A precharge voltage generating circuit for precharging the bit line of the dynamic RAM. 2. The dynamic RAM according to claim 1, further comprising an equalizing means for short-circuiting between said first and second bit lines in said precharge in said self refresh mode. 3. A data read / write circuit for reading / writing data from / to the plurality of memory cells; a self-refresh circuit for self-refreshing data held in the plurality of memory cells; a power supply line ; the data read / write circuit; A power supply voltage supply circuit that supplies the power supply voltage to the self-refresh circuit;
2. The dynamic RAM according to claim 1, wherein a power supply voltage lower than in a normal operation mode is supplied to the power supply line, the data read / write circuit, and the self refresh circuit in a mode. 4. An external power supply voltage is supplied to a power supply line in both the normal operation mode and the self refresh mode.
Dynamic RAM as described. 5. A plurality of dynamic memory cells, a data read / write circuit for reading / writing data from / to the plurality of memory cells, and a self-refresh circuit for self-refreshing data held in the plurality of memory cells. A dynamic RAM having a power supply voltage supply circuit for supplying a power supply voltage to the data read / write circuit and the self-refresh circuit, wherein the power supply voltage supply circuit has one end connected to a power supply line for supplying an external power supply voltage;
An element, a first switch element having one end connected to the power supply line, the other end of the resistance element, and the other end of the first switch element
And the ground, in turn, are connected in series in the forward direction.
1, second ... nth unidirectional element (however, n = 2 or more)
, One end of which is connected to one end of the first unidirectional element,
Is connected to a second switch connected to the other end of the first unidirectional element.
And a switch having an input terminal connected to one end of the first unidirectional element.
Depletion type n-channel insulated gate field effect transistor
First source hole using transistor as drive transistor
And the first source follower circuit is connected in cascade with the first stage as a first stage.
Depletion type n-channel insulated gate field effect
2nd to m-th transistors using transistors as driving transistors
A source follower circuit (where m is an integer of 2 or more), one end of which is connected to the other end of the first unidirectional element;
Is connected to an output terminal of the first source follower circuit.
3 and a self-refresh signal in the normal operation mode.
In response, the first, second, and third switch elements are turned off.
State in self-refresh mode.
The first switch element is turned off, and the second and third switches are turned off.
The switch element is turned on, and the self-refresh is performed.
・ When shifting from the mode to the normal operation mode,
Control for temporarily turning on the first switch element
And an output terminal of the m-th source follower circuit.
A reference voltage generating circuit adapted to obtain a reference voltage, and a constant voltage circuit, which steps down the external power supply voltage,
The same voltage as the reference voltage output from the reference voltage generation circuit
Provided a step-down circuit to output an internal supply voltage of pressure, the generating the internal power supply voltage based on a constant of the reference voltage independent of external power supply voltage, depending on the voltage value of the reference voltage to the self-refresh signal by switching the normal operation mode, it supplies a first internal power supply voltage lower than said external power supply voltage to the data write circuit and the self-refresh circuit, said self-refresh mode, the first A dynamic RAM configured to supply a second internal power supply voltage lower than one internal power supply voltage to the data read / write circuit and the self refresh circuit. 6. The resistance element has an gate having a grounded gate.
Hansment type first p-channel insulated gate field effect
And the first, second, and third switch elements are respectively
Enhancement-type second, third and fourth p-channel insulation
The first, second,..., M-th source follower circuits are configured by gate-type field-effect transistors.
Each is an enhancement type n-channel insulated gate type
The first, second,...
Claims characterized by being provided with a load current source
Item 6. The dynamic RAM according to Item 5 .