JPH1064259A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce time required for refreshing a memory cell while reducing current at the time of self refreshing. SOLUTION: A peripheral circuit part 2 is used to access the memory cell of a memory cell array 1. A self refresh control circuit 3 performs the burst refreshing of the memory cell of the memory cell array 1. A first substrate potential generation circuit 4 generates a potential to be supplied to the cell substrate of the memory cell. A substrate potential control circuit 6 generates a potential for reducing the difference between a substrate potential supplied to the cell substrate and a low-potential power supply by controlling the first substrate potential generation circuit 4 at the time of standby between the burst refreshes of the memory cell array 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a DRAM self-refresh.

In recent years, semiconductor memories have been required to have higher speed and lower current, and to have higher performance. In particular, in DRAMs, there is a strong demand for a reduction in self-refresh current. Therefore, it is necessary to reduce the self-refresh current of the DRAM.

[0003]

2. Description of the Related Art FIG. 7 shows an example of a conventional DRAM. The DRAM 100 includes a memory cell array 101 having a large number of memory cells, a row decoder 102, a sense amplifier 103, a column decoder 104, a self-refresh control circuit 105, a cell substrate potential generation circuit 106, and a peripheral substrate potential generation circuit 107. The row decoder 102, the sense amplifier 103, and the column decoder 104 constitute a peripheral circuit for accessing a memory cell of the memory cell array 101.

The DRAM 100 has a high power from a system power supply.
And low-potential power supply V_DD, V_SSIs supplied to the DRAM 10
0 is dual power supply V_DDAnd V_SSOperate based on Cell substrate
The potential generating circuit 106 has a high potential power supply V_DDAnd low-potential power supply V
_SSAs shown in FIG. 10, a constant value of the substrate potential
VC0 to generate the memory cell array 101
It is supplied to the cell substrate of the molycell. Peripheral substrate potential generation circuit
107 is a high potential power supply V _DDAnd low-potential power supply V_SSOn the basis of
As shown in FIG. 10, a constant value of substrate potential VP0 is generated.
And supplies it to the substrate of the transistor that constitutes the peripheral circuit section.
You.

FIG. 8 shows a cross-sectional structure of an nMOS transistor 115 forming a memory cell and an nMOS transistor 118 forming a peripheral circuit portion. p-type semiconductor substrate 1
10, an n-type separation layer 111 is formed.
1 has a p-type well 112 formed therein. The n-type source region 1 is provided at a predetermined interval in the p-type well 112.
13 and a drain region 114 are formed. An nMOS transistor 115 is formed by the p-type well 112, the n-type source region 113, and the drain region 114. The substrate potential VC0 output from the cell substrate potential generation circuit 106 is supplied to the p-type well 112.

Further, an n-type source region 116 and a drain region 1 are provided in a p-type semiconductor substrate 110 at predetermined intervals.
17 are formed. The p-type semiconductor substrate 110, the n-type source region 116 and the drain region 117
An OS transistor 118 is formed. The substrate potential VP0 output from the peripheral substrate potential generating circuit 107 is supplied to the p-type semiconductor substrate 110.

[0007] The row decoder 102 is a memory cell array 1
01, a plurality of word lines WL (WL0 to WLn)
It is connected to the. The row decoder 102 decodes the row address signal AR into a selection signal, and selects a predetermined word line from a plurality of word lines WL of the memory cell array 101 based on the selection signal.

The column decoder 104 is connected to a plurality of bit line pairs BL and BL bars extending from the memory cell array 101. Column decoder 104 decodes column address signal AC into a selection signal, and selects a predetermined bit line pair of memory cell array 101 by the selection signal. When a predetermined word line is selected by the row decoder 102 and a predetermined bit line pair is selected by the column decoder 104, a memory cell connected to the selected word line and bit pair is selected. Data is written to or read from a memory cell. The sense amplifier 103 amplifies data read from the selected memory cell.

When a predetermined time (100 μsec in this case) elapses after the externally input row address strobe signal RAS switches to the L level, the self-refresh control circuit 105, as shown in FIG. A self refresh entry signal SR is generated. After the self-refresh control circuit 105 switches the self-refresh entry signal SR to the L level, the self-refresh control circuit 105 self-refreshes the memory cells of the memory cell array 101 in the distributed mode based on the operation clock CLK.

In the distributed mode, a plurality of word lines WL (WL0 to WLn) of the memory cell array 101 in one predetermined refresh cycle Tc.
Are sequentially selected at equal time intervals Tc / n. The data of the plurality of memory cells connected to the selected word line is amplified by the sense amplifier 103 and written into the memory cells again, so that the memory cells are refreshed. Refresh of the memory cell connected to each word line is completed in a short time within a half cycle of the operation clock CLK.

[0011]

At the time of self-refresh, the memory cell array 101 is not accessed by the peripheral circuit portion. Therefore, refresh is required by reducing the leak current from the memory cell to the cell substrate. There is an advantage that the time can be reduced.

However, in the conventional DRAM 100, the self-refresh control circuit 105 is
01 is performed in the distributed mode, and the substrate potential VC0 of the memory cell at the time of self refresh is set to a value equal to the substrate potential of the memory cell at the time of normal operation. Therefore, the leak current from the memory cell to the cell substrate cannot be reduced, and the effectiveness of the self-refresh in a limited state cannot be utilized, so that the time required for the refresh cannot be reduced.

Further, at the time of self-refresh, the substrate voltage of the peripheral circuit is also equal to the substrate voltage at the time of normal operation, and the tailing current of the transistor constituting the peripheral circuit cannot be reduced at the time of self-refresh. The current consumption was increasing.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to reduce the time required for refreshing memory cells while reducing the current during self-refresh. Is to provide.

Another object of the present invention is to provide a semiconductor memory device capable of reducing a current in a peripheral circuit portion at the time of self refresh.

[0016]

FIG. 1 is a diagram illustrating the principle of the present invention. The peripheral circuit section 2 is for accessing a memory cell of the memory cell array 1. The self-refresh control circuit 3 is for performing a burst refresh of the memory cells of the memory cell array 1. The first substrate potential generation circuit 4 generates a potential to be supplied to a cell substrate of a memory cell. The substrate potential control circuit 6 includes the memory cell array 1
During standby during the burst refresh, the first substrate potential generation circuit 4 is controlled to generate a potential that reduces the difference between the substrate potential supplied to the cell substrate and the low potential power supply.

(Operation) Therefore, during standby during burst refresh of the memory cell array 1, the difference between the substrate voltage supplied to the cell substrate of the memory cell and the low-potential power supply is small. The current is reduced. Therefore, the refresh time can be lengthened, and the current consumption during the self-refresh period is reduced.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 2 shows a DRAM 10 of the present embodiment. The DRAM 10 includes a memory cell array 11 having a large number of memory cells, a row decoder 12,
Sense amplifier 13, column decoder 14, self-refresh control circuit 15, first substrate potential generation circuit 16, second substrate potential generation circuit 17, and substrate potential control circuit 20
It has. Row decoder 12, sense amplifier 13,
The column decoder 14 constitutes a peripheral circuit for accessing a memory cell of the memory cell array 11.

The DRAM 10 is supplied with high and low potential power supplies V _DD and V _SS from a system power supply, and the DRAM 10 operates based on both power supplies V _DD and V _SS . The first substrate potential generating circuit 16 is a circuit for generating a potential supplied to the cell substrate of the memory cell, generating a substrate potential VC1 shown in FIG. 6 based on the high potential power supply V _DD and the low-potential power supply V _SS Then, it is supplied to the cell substrate of the memory cells constituting the memory cell array 11. The second substrate potential generating circuit 17 is a circuit for generating a potential supplied to the substrate of the peripheral circuit portion, based on the high potential power supply V _DD and the low-potential power supply V _SS 6
And generates a substrate potential VP1 as shown in FIG.

FIG. 5 shows a cross-sectional structure of an nMOS transistor 85 forming a memory cell and an nMOS transistor 90 forming a peripheral circuit portion. An n-type separation layer 81 is formed in a p-type semiconductor substrate 80, and a p-type separation layer 81 is formed in the separation layer 81.
A mold well 82 is formed. In a p-type well 82, an n-type source region 83 and a drain region 84 are formed at predetermined intervals. An nMOS transistor 85 is formed by the p-type well 82, the n-type source region 83, and the drain region 84. Substrate potential V output from first substrate potential generation circuit 16 is applied to p-type well 82.
C1 is supplied, and a high potential power supply V _DD is supplied to the separation layer 81.

An n-type separation layer 86 is formed in the p-type semiconductor substrate 80, and a p-type well 87 is formed in the separation layer 86.
Are formed. In a p-type well 87, an n-type source region 88 and a drain region 89 are formed at predetermined intervals. p-type well 87, n-type source region 88
And nMOS transistor 9 by drain region 89
0 is formed. The substrate potential VP1 output from the second substrate potential generating circuit 17 is supplied to the p-type well 87, and the high potential power supply _VDD is supplied to the separation layer 86.
Here, a P substrate is given as an example, but a similar configuration is possible with an N substrate.

The row decoder 12 is a memory cell array 11
Connected to a plurality of word lines WL0 to WLn extending from the word lines WL0 to WLn. The row decoder 12 decodes the row address signal AR into a selection signal, and selects a predetermined word line from a plurality of word lines WL (WL0 to WLn) of the memory cell array 11 based on the selection signal.

The column decoder 14 is a memory cell array 1
The bit lines are connected to a plurality of bit line pairs BL and BL bars extending from one bit line. The column decoder 14 outputs a column address signal A
C is decoded into a selection signal, and a predetermined bit line pair of the memory cell array 11 is selected by the selection signal. When a predetermined word line is selected by the row decoder 12 and a predetermined bit line pair is selected by the column decoder 14, a memory cell connected to the selected word line and bit pair is selected. Data is written to or read from a memory cell.
The sense amplifier 13 amplifies data read from the selected memory cell.

The self-refresh control circuit 15 operates for a predetermined time (in this case, 10 seconds) after the externally input row address strobe signal RAS switches to the L level.
After 0 μsec), an L level self-refresh entry signal SR bar is generated as shown in FIG. After switching the self-refresh entry signal SR bar to the L level, the self-refresh control circuit 15 self-refreshes the memory cells of the memory cell array 11 in the burst mode based on the operation clock CLK.

The burst mode is a predetermined one refresh cycle Tc (64 msec in the present embodiment).
In c), a plurality of word lines WL (WL0 to WLn) of the memory cell array 11 are sequentially selected in synchronization with the operation clock CLK. The data of the plurality of memory cells connected to the selected word line is amplified by the sense amplifier 13 and written into the memory cells again, so that the memory cells are refreshed. Refresh of the memory cell connected to each word line is completed in a short time within a half cycle of the operation clock CLK.

In this embodiment, the word line WL is set to, for example, 40
In this example, the time required for refreshing the memory cells connected to one word line is set to, for example, 100 nsec.
Then, in one refresh cycle Tc, the time required for the actual refresh is 0.4 msec (= 100n)
sec × 4000) and the rest of the time is 63.6m
In a second (= 64 msec−0.4 msec), the standby state where no refresh is performed is set.

The substrate potential control circuit 20 in the standby between burst refresh of the memory cell array 11, the substrate potential VC1 and the low-potential power supply V _SS supplied to the cell substrate by controlling the first substrate potential generating circuit 16 A substrate potential VC1 having such a value as to reduce the difference is generated.
Further, the substrate potential control circuit 20 includes the memory cell array 11
In standby between burst refresh of generating the substrate potential VP1 values, such as the potential difference is large between the substrate potential VP1 of the peripheral circuit portion controls the second substrate potential generating circuit 17 and the low-potential power supply V _SS Things.

That is, the substrate potential control circuit 20 includes an oscillator 21, a burst counter 23, and a period counter 2.
4, control signal generation circuit 25, and first to fourth setting units 26
~ 29.

The oscillator 1 generates an operation clock CLK. When the memory cell array 11 starts refreshing in the burst mode, the burst counter 23 starts counting pulses of the operation clock CLK. The burst count 23 counts up when a pulse of the operation clock CLK is counted by the number of word lines of the memory cell array 11, and outputs a signal S1.

The period counter 24 has an operation clock CLK.
Is used to measure the refresh cycle Tc. When the memory cell array 11 starts to be refreshed in the burst mode, the cycle counter 24 starts counting pulses of the operation clock CLK. The cycle counter 24 outputs the signal S2 when it counts the pulses of the operation clock CLK until several hundred μsec before the end point of the refresh cycle Tc. When counting the pulses of the operation clock CLK for the refresh cycle Tc, the cycle counter 24 resets the counter 24 itself and the count value of the burst counter 23 based on the count-up signal.

The control signal generation circuit 25 includes a signal S1 output from the burst counter 23 and a period counter 2
The control signal S3 shown in FIG. 6 is output based on the signal S2 output from the control signal S4. That is, when the signal S1 is input after the completion of one burst refresh, the control signal S
3 becomes H level, and when the signal S2 is input several hundred μsec before the end point of the refresh cycle Tc,
The control signal S3 goes low.

The first setting portion 26 in a normal operating state except DRAM10 self refresh operation, a circuit for generating a low-potential power supply V _SS as the substrate potential VP1 of the peripheral circuit portion. The second setting unit 27 in the standby between DRAM10 the burst refresh is a circuit for generating a substrate potential VP1 values such as the potential difference between the substrate potential VP1 of the peripheral circuit portion and the low-potential power supply V _SS increases.

FIG. 3 shows a first setting section 26 and a second setting section 27.
The details are shown below. The first setting unit 26 includes an nMOS transistor 31 and an inverter 32. When the control signal S3 is at the L level in the normal operation state of the DRAM 10 and during the burst refresh, the output of the inverter 32 becomes H level.
Level, and the nMOS transistor 31 is turned on.
As a result, the low-potential power supply V _SS is output as the substrate potential VP1. When the control signal S3 is at the H level during standby during the burst refresh of the DRAM 10, the output of the inverter 32 goes to the L level, and the nMOS transistor 31 is turned off.

The second setting unit 27 is a pMOS transistor 3
5, nMOS transistors 36 to 39, 45, 46, N
AND circuit 41, inverters 42, 43, 48, 50,
It has a capacitor 44 and analog switches 47 and 49.

When the control signal S3 is at the L level during normal operation of the DRAM 10 and during burst refresh, the outputs of the inverters 48 and 49 are at the H level,
Switches 47 and 49 are turned off.

When the control signal S3 is at the H level during standby during the burst refresh of the DRAM 10, the outputs of the inverters 48 and 50 are at the L level, and the switches 47 and 49 are turned on. At this time, the gate of the pMOS transistor 35 is therefore connected to the low-potential power supply V _SS, pMOS transistor 35 outputs the turns H level signal. Therefore, the NAND circuit 41 operates as an inverter, and the NAND circuit 41 and the inverter 4
2, 43 operate as an oscillation circuit. The charging voltage of the capacitor 44 increases based on the output of the inverter 43, and the charging voltage becomes nM via the analog switches 47 and 49.
The signal is transmitted to the OS transistor 39. When the charging voltage of the capacitor 44 is lower than the low potential power supply V _SS by the threshold voltage of the four nMOS transistors 36 to 39, n
MOS transistors 36 to 39 are turned on. for that reason,
The output signal to the NAND circuit 41 becomes L level, the oscillation stops, and the charging of the capacitor 44 stops. At this time, the charging voltage VP12 of the capacitor 44 becomes equal to the substrate potential VP.
Output as 1.

The third setting section 28 is a circuit for generating the substrate potential VC1 of the cell substrate of the memory cell in a normal operation state except the self-refresh operation of the DRAM 10. The fourth setting unit 29 is a circuit in a standby between DRAM10 the burst refresh, generating a substrate potential VC1 values such as the potential difference between the substrate potential VC1 of the cell substrate and the low-potential power supply V _SS decreases.

FIG. 4 shows a third setting unit 28 and a fourth setting unit 29.
The details are shown below. The third setting unit 28 includes a pMOS transistor 61, nMOS transistors 59, 60, 62 to 64,
The circuit includes a NAND circuit 55, inverters 56, 57, 66, a capacitor 58, and an analog switch 65.

When the control signal S3 is at L level during normal operation of the DRAM 10 and during burst refresh, the output of the inverter 66 goes to H level and the switch 65 is turned on. At this time, the pMOS transistor 6
1 is connected to the low potential power supply V _SS ,
MOS transistor 61 is turned on and outputs an H level signal. NAND circuit 55 via analog switch 65
Is input to the NAND circuit 55.
Operates as an inverter, and the NAND circuit 55 and the inverters 56 and 57 operate as oscillation circuits. The charging voltage of capacitor 58 increases based on the output of inverter 57, and the charging voltage is transmitted to nMOS transistor 64. When the charging voltage of the capacitor 58 is lower than the low potential power supply V _SS by the threshold voltage of the three nMOS transistors 62, 63, 64, the nMOS transistor 6
2, 63 and 64 are turned on. Therefore, the NAND circuit 5
The output signal to the L level becomes L level, oscillation stops, and charging of the capacitor 58 stops. At this time, the capacitor 5
8 is output as the substrate potential VC1.

When the control signal S3 is at the H level during standby during the burst refresh of the DRAM 10, the output of the inverter 66 goes to the L level and the switch 65 is turned off.

The fourth setting unit 29 includes the pMOS transistor 6
7, nMOS transistors 68 and 69, an analog switch 70, the nMOS transistors 59 and 60, the NAND circuit 55, inverters 56, 57 and 66, and a capacitor 58.

When the control signal S3 is at the L level during normal operation of the DRAM 10 and during burst refresh, the output of the inverter 66 goes to the H level and the switch 70 is turned off.

When the control signal S3 is at the H level during standby during the burst refresh of the DRAM 10, the output of the inverter 66 is at the L level, and the switch 70 is turned on. At this time, the pMOS transistor 67
Is connected to the low potential power supply V _SS ,
The OS transistor 67 turns on and outputs an H-level signal. Since an H-level signal is input to the NAND circuit 55 via the analog switch 70, the NAND circuit 55 operates as an inverter, and the NAND circuit 55 and the inverters 56 and 57 operate as oscillation circuits. Inverter 5
7, the charging voltage of the capacitor 58 increases, and the charging voltage is transmitted to the nMOS transistor 69. When the charging voltage of the capacitor 58 is lower than the low potential power supply V _SS by the threshold voltage of the two nMOS transistors 68 and 69, the nMOS transistors 68 and 69
Turns on. Therefore, the output signal to the NAND circuit 55 becomes L level, the oscillation stops, and the charging of the capacitor 58 stops. At this time, the charging voltage V of the capacitor 58
C12 is output as substrate potential VC1.

In the standby state during the burst refresh of the memory cell array 11, the substrate potential V supplied to the cell substrate by controlling the first substrate potential generating circuit 16 is controlled.
C1 and the difference between the low-potential power supply V _SS generates the substrate potential VC1 of smaller becomes such a value. Further, the substrate potential control circuit 2
0, in the standby between burst refresh of the memory cell array 11, values such as the potential difference is large between the substrate potential VP1 of the peripheral circuit portion controls the second substrate potential generating circuit 17 and the low-potential power supply V _SS Substrate potential V
P1 is generated.

The present embodiment has the following effects. (1) In the DRAM 10 of the present embodiment, since the self-refresh control circuit 15 performs the self-refresh of the memory cell array 11 in the burst mode, a standby time can be generated between the self-refresh. At the time of this standby, the fourth setting unit 29 sets the cell substrate 82
A substrate potential VC1 generates a substrate voltage VC12 as the potential difference between the low-potential power supply V _SS decreases, the first substrate potential generating circuit 16 supplies the substrate potential VC12 to cell substrate 82 of the memory cell. Therefore, the leakage current from the memory cell to the cell substrate during standby is reduced. As a result, in the next refresh cycle Tc, the charge current to the memory cell can be reduced, the refresh can be performed in a short time, and the refresh characteristics can be improved.

[0046] (2) In the DRAM10 in this embodiment, in the standby between the self-refresh of the memory cell array 11, the second setting unit 27 increases the potential difference between the substrate potential VP1 substrate 87 of the peripheral circuit portion and the low-potential power supply V _SS A second substrate potential generation circuit 17 supplies the substrate voltage VP12 to the substrate 87 of the peripheral circuit section. As a result, the threshold voltage of the transistor 90 forming the peripheral circuit portion increases during standby during self-refresh, so that the tailing current of the transistor 90 can be reduced, and the current consumption can be reduced.

[0047]

As described in detail above, the inventions of claims 1 to 3 can shorten the time required for refreshing a memory cell while reducing the current during self refresh.

According to the second and third aspects of the present invention, it is possible to reduce the current in the peripheral circuit portion during self refresh.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram illustrating a DRAM according to an embodiment;

FIG. 3 is a circuit diagram showing details of first and second setting units;

FIG. 4 is a circuit diagram showing details of third and fourth setting units;

FIG. 5 is a cross-sectional view of a memory cell and a transistor in a peripheral circuit portion.

FIG. 6 is a waveform chart showing the operation of the DRAM of the embodiment.

FIG. 7 is a block diagram showing a conventional DRAM.

FIG. 8 is a cross-sectional view of a conventional memory cell and a transistor in a peripheral circuit portion.

FIG. 9 is a waveform chart showing the operation of a conventional DRAM.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory cell array 2 Peripheral circuit part 3 Self-refresh control circuit 4 First substrate potential generation circuit 5 Second substrate potential generation circuit 6 Substrate potential control circuit

Claims (3)

[Claims] A memory cell array having a plurality of memory cells; a peripheral circuit unit for accessing the memory cells of the memory cell array; a self-refresh control circuit for burst refreshing the memory cells of the memory cell array; A first substrate potential generation circuit for generating a substrate potential to be supplied to a cell substrate of the memory cell; and controlling the first substrate potential generation circuit during standby between burst refreshes of the memory cell array to control the cell potential. A semiconductor memory device comprising: a substrate potential control circuit that generates a potential that reduces a difference between a substrate potential supplied to a substrate and a low potential power supply. A second substrate potential generation circuit for generating a substrate potential to be supplied to a substrate of the peripheral circuit portion, wherein the substrate potential control circuit controls the second substrate potential generation circuit to generate a peripheral potential. 2. The semiconductor memory device according to claim 1, wherein a potential is generated such that a potential difference between a substrate potential supplied to a substrate of a circuit unit and the low-potential power supply increases. 3. The substrate potential control circuit includes: a first setting unit for setting a substrate voltage of a peripheral circuit unit during a normal operation; and a substrate voltage control circuit for setting a substrate voltage of the peripheral circuit unit during a standby period between burst refreshes. A third setting unit for setting the substrate voltage of the cell substrate of the memory cell during normal operation; and a third setting unit for setting the substrate voltage of the cell substrate of the memory cell during standby between burst refreshes. A fourth setting unit; a first counter for measuring the end of the burst refresh of the memory cell array; a second counter for measuring a standby state between burst refreshes of the memory cell array; Based on the measurement result of the counter and the measurement result of the second counter, during normal operation, And the substrate voltage of the third setting unit is output to the first substrate potential generation circuit, and the voltage of the second setting unit is output during standby during self-refresh. 3. The semiconductor memory device according to claim 2, further comprising: a control unit configured to output a substrate voltage to the second substrate potential generation circuit and to output a substrate voltage of the fourth setting unit to the second substrate potential generation circuit. 4. .