JPS63239670A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To surely detect a defect based on the destruction of storing capacitor by selectively connecting a plate potential supplying node of a memory cell to one power supply terminal of a circuit in accordance with the setting of a test mode. CONSTITUTION:The precharge levels of data lines DL, DL' connected to a dynamic memory cell MC and a plate potential supplied to a storing capacitor Cs are approximately set up to an intermediate level of a power supply voltage. In the semiconductor storage device, a plate potential supplying node Npl of a memory cell MC can be selectively connected to one power supply terminal of the circuit in accordance with the setting of the test mode. Since the plate potential Vpl and the precharge level are offset each other in the test mode, information read out from the memory cell MC is fixed in accordance with the plate potential Vpl if the storing capacitor Cs is weakly destructed. Conse quently, a defect based upon the destruction of the storing capacitor Cs can be surely detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device of a type in which stored information is stored in a storage capacity, and also to detection of destruction of the storage capacity therein.
For example, the present invention relates to a technique that is effective when applied to a DRAM (dynamic random access memory) composed of MOSFETs.

[Prior art]

Some DRAM memory cells are composed of one transistor, and as elements become finer due to higher integration, storage capacitance tends to become smaller in area.

In a one-transistor type memory cell, in order to increase the signal level for reading stored information, it is necessary to increase the storage capacitance or reduce the parasitic capacitance of the data line, but as the integration becomes higher, the data line becomes longer. In addition, in order to prevent refresh and soft error margins from decreasing, it is necessary to increase the storage capacity in a small area. In order to satisfy such requirements, for example, rLSI, published by Ohm Co., Ltd. on November 30, 1980,
As described in Handbook J P2S5 and P2S5, it is possible to thin the silicon oxide film for capacitance formation, use a high dielectric constant film such as silicon nitride film, and further improve the structure of a high-sea cell structure or trench-type capacitor cell. structure can be adopted. However, no matter which structure is adopted, the withstand voltage of the storage capacitance is inevitably lowered as miniaturization accompanies higher integration.

Therefore, as the withstand voltage of the storage capacitor decreases, a method has been adopted in the past to reduce the potential between the electrodes of the storage capacitor.1 For example, a plate potential approximately at an intermediate level of the power supply voltage is applied to the storage capacitor. . Thereby, the potential between the electrodes of the storage capacitor is reduced to half of the power supply voltage Vdd at the maximum.

[Problem that the invention seeks to solve]

By the way, when reading data from a dynamic memory cell, it is necessary to precharge the data line to which the memory cell is connected to a desired level. The intermediate level of the power supply voltage that can be obtained is often adopted as the precharge level.

The present inventors investigated the case where the plate potential and the precharge level are made approximately equal, and found that if the storage capacitor is destroyed weekly, the plate potential and the precharge level are made equal. , the read information can be either high level or low level depending on the leakage state. Therefore, the read information may match or mismatch with the normal stored information, making it impossible to confirm storage capacity destruction, which significantly reduces the reliability of defect detection. I found it.

An object of the present invention is to provide a semiconductor memory device that can reliably detect defects based on destruction of storage capacitors.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a semiconductor memory device in which the precharge level of a data line to which a dynamic memory cell is coupled and the plate potential supplied to a storage capacitor are approximately at an intermediate level of the power supply voltage, the plate potential supply node of the memory cell is set in test mode. The power supply terminal can be selectively coupled to one power supply terminal of the circuit in response to the setting of the power supply terminal.

[For production]

According to the above means, in the test mode, the plate potential and the precharge level are different, so if the storage capacitor is destroyed weekly, the information read from the memory cell is fixed in response to the plate potential. By doing so, reliability of failure detection based on destruction of storage capacitance can be achieved.

〔Example〕

FIG. 1 is a circuit diagram showing the main parts of a DRAM which is an embodiment of the present invention. The DRAM shown in the figure is formed on one semiconductor substrate by a known semiconductor integrated circuit manufacturing technique, although this is not particularly limited.

Although not particularly limited, the DRAM shown in FIG.
The memory cell array MCA includes a plurality of one-transistor type dynamic memory cells MC arranged in a matrix in which a channel type selection MO8FET QI and a storage capacitor Cs are connected in series.

Memory cells MC are typically arranged using complementary data lines DL, DL laid out using a folded data line method.
An equal number of data input/output terminals (M
The selection terminal (gate electrode of MO8FETQI) of each memory cell MC is connected to the word line Wm representatively shown in the corresponding column.

It is bonded to Wn. Although not shown, each complementary data line DL has a determination level (for example, approximately half the level of one power supply voltage Vdd) when reading data.
Dummy cells that give the following are connected one by one. Although not particularly limited, the dummy cell (not shown) has a storage capacity that is approximately half that of the memory cell MC, or the charging potential for the same storage capacity as the memory cell is approximately half of the power supply voltage Vdd, so that the above-mentioned determination level can be adjusted. be held in possession.

Addressing of memory cell MC involves driving one predetermined word line to a selected level based on the output of a column address decoder (not shown), and driving a pair of complementary data lines based on the output of a row address decoder (not shown). This is performed based on the operation of a switch circuit (not shown) that selectively connects to the complementary common data line that is not connected. When one word line is selected, the memory cell MC coupled to one of the complementary data lines DL, DL is selected; A dummy cell (not shown) coupled to the other one is also selected.

Each complementary data line DL, DL is coupled to an input/output terminal of a static sense amplifier SA, although this is not particularly limited. Although not particularly limited, this SEGIS amplifier SA includes a pair of complementary MMOS transistors in which a P-channel type MO5FET Q2 and an N-channel type MO5FET Q3 are connected in series.
O8 (hereinafter also simply referred to as CMO8) inverter circuit IV
N-channel power switch MO3FETQ4, which is configured by cross-coupling the input and output terminals of I and IV2, and receives sense amplifier operation signals with opposite phases to each other at its gate.
and a P-channel type power switch MO8FETQ8.

In FIG. 1, Q5 is an N-channel precharge MO3FET, which is turned on at a predetermined timing during the chip non-selection period to generate complementary data 1iDL,
The level of DL is balanced and precharged to the intermediate level Vdd'/2 of the basic power supply voltage Vdd. Note that when precharging the complementary data lines DL and DL, the power supply voltage Vd
It is also possible to use the output voltage of the voltage forming circuit VG that forms the voltage Vd d/2 which is half the level of d.

One electrode of the storage capacitor Cs in each of the memory cells MC (including one electrode of the storage capacitor in each dummy cell (not shown)) is connected to an N-channel control MO8FET.
Voltage forming circuit VG (7) output voltage V d via Q6
d/2 is supplied as a potential vpi of L/-1. This is in response to the need to increase the capacitance of the storage capacitor Cs in a small area as DRAMs become more highly integrated.
This is to cope with a decrease in the withstand voltage of the storage capacitor Cs by making the potential between the electrodes half of the power supply voltage Vdd as much as possible. Generally ■d
The plate potential Vpl corresponding to d/2 is the plate potential during normal operation of the DRAM.

Furthermore, the plate potential supply node NPI is coupled to the ground terminal Gnd, which is the other power supply terminal of the circuit, via an N-channel control MO5FET Q7. Above control MO5
The FETs Q6 and Q7 are complementary switch-controlled by the control signal φp1, and the storage capacitance Cs
The plate potential Vpl that can be supplied to the circuit can be selected to approximately Vdd/2 or the ground potential. The control signal φpi is set to a high level in the normal operation mode of the DRAM, and is set to a low level in response to setting the test mode to the DRAM. Therefore, the plate potential Vpl in the test mode is set to the ground level of the circuit. Note that the test mode in a DRAM is not particularly limited, but may be set when a voltage signal at a level higher than the power supply voltage Vdd is applied to a predetermined external terminal or dedicated pad, or may be set when a voltage signal at a level higher than the power supply voltage Vdd is applied to a predetermined external terminal or dedicated pad, Strobe) signal is set to high level,
CB that is set when the WE (write enable) signal is set to low level at a predetermined timing while the CAS (column address strobe) signal is set to low level.
It can be set in response to an operating mode such as R mode.

Next, the operation of the above embodiment will be explained.

In the normal operation of the DRAM, the control signal φp1 is set to a high level, so that MOSFETQ6 is turned on and MO5FETQ7 is turned off, and the memory cell array MCA has a plate potential Vpl approximately equivalent to Vdd/2. is supplied. On the other hand, D.R.A.
In the M chip non-selection state, precharge MO3
Complementary data lines DL and DL are half-precharged via FETQ5 to voltage Vdd/2, respectively.

When a memory read operation is instructed in this state and a predetermined memory cell is addressed, complementary data wADL
, DL, the charge in the storage capacitor Cs included in the addressed memory cell is redistributed between the parasitic capacitance of the data line, and in the other data line, the charge is redistributed in the dummy cell. Charges in the storage capacitor holding the level are redistributed between the undesired capacitance parasitic on the other data line. When such charge redistribution produces a minute level difference between the pair of complementary data lines DL, DL, it is detected and amplified by the sense amplifier SA. If the charge level of the storage capacitor to be stored is at a level corresponding to one power supply voltage Vdd, the data line on the memory cell side is set to a high level corresponding to one power supply voltage Vdd, and the data line on the dummy cell side is set to a high level corresponding to one power supply voltage Vdd. The voltage level is set to a low level corresponding to the ground level.

Conversely, if the charge level of the storage capacitor included in the addressed memory cell is a level corresponding to the ground level, the data line on the memory cell side is set to a low level corresponding to the ground level, and the data line on the dummy cell side is set to a low level corresponding to the ground level. The line is brought to a high level corresponding to one power supply voltage level Vdd.

By the way, if weekly leakage occurs in the storage capacitor, such a destroyed storage will occur because in the normal operation mode, the precharge level and plate potential are set to a level substantially equal to the voltage Vd d/2. Information read from a memory cell containing a capacitor can take either a high level or a low level depending on the degree of leakage, and may match or mismatch normal stored information.

In the DRAM of this embodiment, in order to reliably detect such a defective state at the test stage, the control signal φpt is set to a low level in response to the setting of the test mode, thereby turning off the 1M08FETQ6. With,
MO8FETQ7 is turned on, and the ground potential of the circuit is supplied to the memory cell array MCA as the plate potential VPI. In this state, if weekly leakage occurs in the storage capacitor Cs due to the difference between the plate potential Vpl (ground level) and the precharge level (Vdd/2), the destroyed memory cell The information to be read is always fixed at a low level corresponding to the plate potential.

According to the above embodiment, the following effects can be obtained.

(1) In test mode, if high level data is written in advance to the memory cell under test and then read out, the read data will always be set to low level for memory cells whose storage capacitance Cs is destroyed. As a result, it is possible to reliably detect defects based on the destruction of the storage capacitor, thereby improving the reliability of the defect detection test.

(2) By setting the plate potential to the ground level after DRAM assembly is completed, the potential between the electrodes of the storage capacitor can be raised higher than in the normal operation mode, which improves the efficiency of accelerated testing of the storage capacitor. Destruction of the storage capacity due to aging can also be easily detected, and the reliability of DRAM failure detection tests can be further improved.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited to the above-mentioned examples, and various changes can be made without departing from the gist thereof.

For example, in the above embodiment, the plate potential in the test mode is set to the circuit ground potential, but it may be set to the other power supply voltage level Vdd. Further, the plate potential and precharge level in the normal operation mode are not limited to the voltage Vd d/2 of the above embodiment. Furthermore, the memory cell
In the case of a DRAM, the memory cell is not limited to a one-transistor type, but may be a three-transistor type, a four-transistor type memory cell, or the like. Further, in the above embodiment, the precharge MOSFET Q5 is used to precharge the data line, but the precharge may be performed based on the output voltage of the voltage forming circuit VG without using such a MOSFET. The control M○5FETQ6 is not an essential switching element for controlling the plate potential.

In the above explanation, the invention made by the present inventor was mainly applied to DRAM, which is the field of application that formed the background of the invention, but the present invention is not limited thereto, and can also be applied to memories such as pseudo-static RAM. Can be applied.

The present invention can be applied to a device having at least a memory cell that stores storage information in a storage capacitor, and where the precharge level of the data line and the plate potential supplied to the storage capacitor are approximately equal.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, since the plate potential supply node of the memory cell can be selectively coupled to one power supply terminal of the circuit in accordance with the test mode setting, the plate potential and precharge level are different in the test mode. When the storage capacitor is destroyed on a weekly basis, the read information from the memory cell is fixed in response to the plate potential, thereby ensuring reliability of defect detection based on the destruction of the storage capacitor. Thereby, the reliability of failure tests can be significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the main parts of a DRAM which is an embodiment of the present invention. Q1-...Selection MO8FET, Cs-Storage capacity, MC
...Dynamic memory cell, MCA...Memory cell array, DL, DL...Complementary data line, SA...
Sense amplifier, Q5...precharge MO8FET,
VG...voltage forming circuit, Vpl...plate potential,
Q6 and Q7-... system @MO5FET, φp l -
Control signal agent Patent attorney Katsuma Ogawa 6ゝ, Figure 1

Claims (1)

[Claims] 1. A semiconductor having a memory cell that stores memory information in a storage capacitor, in which the precharge level of a data line to which the memory cell is coupled is approximately equal to the plate potential supplied to the storage capacitor. A semiconductor memory device in which a voltage at a level different from a precharge level can be selectively supplied to a plate potential supply node of a memory cell. 2. The plate potential is approximately at an intermediate level of the power supply voltage, and one power supply voltage of the circuit is supplied to the plate potential supply node via a switch element that is switch-controlled in accordance with the setting of the test mode. 2. A semiconductor memory device according to claim 1, characterized in that the semiconductor memory device is made of: