JP2000030438A - Synchronous type semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce current consumption in a clock buffer by operating a clock buffer with first drive power when a self refresh enable signal is inactivated, and a clock enable signal is activated and operating it with second drive power smaller than the first drive power when the clock enable signal is inactivated. SOLUTION: When the clock enable signal CKE is an L level, a synchronous DRAM becomes a power down mode. At this time, a signal /CKEP becomes an H level, and the self refresh enable signal SRE becomes the L level, and an inverter constituted of P, N channel MOS transistors LPT, LNT with large size and more power consumption are stopped, and the inverter constituted of the P, N channel MOS transistors SPT, SNT with small size and less power consumption is operated. Thus, the current consumption in the clock buffer CB is reduced by the current consumption much by the transistors SPT, SNT.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a synchronous semiconductor memory device, and more particularly, to a synchronous semiconductor memory device having a normal mode, a power down mode, and a self refresh mode.

[0002]

2. Description of the Related Art With the spread of portable information terminals such as portable telephones and mobile PCs, there is an increasing demand for lower power consumption of semiconductor memories. Above all, it is very important to reduce the power consumption of synchronous DRAMs (dynamic random access memories), which have been increasing in demand recently.

FIG. 7 is a block diagram showing a part of the configuration of a conventional synchronous DRAM. Referring to FIG. 7, this synchronous DRAM includes a self-refresh mode detection circuit 10, a CKEPC generation circuit 11, an address buffer 12, a clock buffer 100, an internal clock generation circuit 13, and an input / output receiving an external signal. Pin 14
And

[0004] Self-refresh mode detection circuit 10
Generates a self-refresh enable signal SRE in response to an external row address strobe signal / RAS, an external column address strobe signal / CAS, and a clock enable signal CKE. CKEPC generation circuit 11 generates signal / CKEPC in response to clock enable signal CKE. The address buffer 12 has a buffer AB0-
ABn. Buffers AB0-ABn are CKEPC
When output signal / CKEPC from generation circuit 11 is at L level, external address signals AD0-ADn are buffered and output as internal address signals IAD0-IADn, and output signal / CKEP from CKEPC generation circuit 11 is output.
It stops when C is at H level.

The clock buffer 100 includes a power supply node V
P-channel MOS transistors 101 and 102 connected in series between dd and output node OUT, N-channel MOS transistors 103 and 104 connected in parallel between output node OUT and ground node GND, and inverter 105 And The internal clock generation circuit 13
In response to clock buffer signal BUFCLK, internal clock signal int. CLK.

Next, the operation of the synchronous DRAM configured as described above will be described with reference to (a) the normal mode and (b)
The case of the power down mode and (c) the self refresh mode will be described.

(A) Normal mode When the clock enable signal CKE is at H (logic high) level, the synchronous DRAM enters the normal mode.

At this time, output signal / CKEPC from CKEPC generating circuit 11 and self-refresh enable signal SRE attain an L level. Thereby, buffers AB0-ABn in the address buffer are activated. Also, the P-channel MO in the clock buffer 100
The S transistor 101 is turned on, and the N-channel MOS
Transistor 104 turns off. Thereby, clock buffer 100 is activated, and P-channel MOS transistor 102 and N-channel MOS transistor 1
03 by the inverter constituted by the external clock signal Ext. CLK is inverted and output to output node OUT, and further inverted by inverter 105 and output as clock buffer signal BUFCLK. In response to this clock buffer signal BUFCLK, internal clock generation circuit 13 generates internal clock signal int. CLK.

(B) Power down mode Referring to FIG. 8, clock enable signal CKE is at L level.
At the (logic low) level, the synchronous DRAM enters the power down mode.

At this time, the output signal / CKEPC from the CLEPC generation circuit 11 goes high, and the buffers AB0-ABn in the address buffer 12 stop. As a result, current consumption by the address buffer is reduced.
On the other hand, self-refresh enable signal SRE attains an L level, and clock buffer 100 operates in the same manner as in the normal mode.

(C) Self-refresh mode Referring to FIG. 9, when clock enable signal CKE, row address strobe signal / RAS and column address strobe signal / CAS attain L level simultaneously, the synchronous DRAM enters a self-refresh mode. Become.

At this time, the output signal / CKEPC from the CKEPC generation circuit 11 goes high, and the buffers AB0-ABn in the address buffer 12 stop. Further, since self-refresh enable signal SRE attains an H level, P-channel MOS transistor 101 in clock buffer 100 is turned off, and N-channel M
The OS transistor 104 turns on. As a result, the clock buffer 100 stops. As a result, current consumption in the address buffer 12 and the clock buffer 100 is reduced.

As described above, the operation / stop of the clock buffer 100 is controlled by the self-refresh enable signal SRE.
Is controlled by

The reason is that when the operation / stop of the clock buffer is controlled by the clock enable signal CKE, the clock cannot be recovered in time when the clock enable signal CKE changes from the L level to the H level.

By the way, in the self-refresh mode, as shown in FIG. 9, since a command is input after a lapse of a predetermined time t from the end of the self-refresh mode, the operation / stop of the clock buffer 100 is enabled by the self-refresh enable. When the control is performed by the signal SRE, there is no problem as described above.

[0016]

SUMMARY OF THE INVENTION Clock buffer 10
0 operates / stops in response to the self-refresh enable signal SRE, and thus operates in the power-down mode in the same manner as in the normal mode. Therefore, it is not possible to reduce the current consumption of the clock buffer in the power down mode.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a synchronous semiconductor memory device capable of reducing current consumption in a clock buffer.

[0018]

A synchronous semiconductor memory device according to one aspect of the present invention includes a self-refresh mode detection circuit, an input buffer, and a clock buffer. The self-refresh mode detection circuit generates a self-refresh enable signal in response to an external signal. The input buffer operates to generate an internal signal in response to an external signal when the clock enable signal is active, and stops when the clock enable signal is inactive. The clock buffer generates an internal clock signal in response to the external clock signal. Further, the clock buffer operates with the first drive capability when the clock enable signal is active and the self-refresh enable signal is inactive, and the clock enable signal is inactive and the self-refresh enable signal is inactive. When the clock enable signal is inactive and the self-refresh enable signal is active, it operates with the second drive capability smaller than the first drive capability.

In the above-mentioned synchronous semiconductor memory device, when the clock enable signal is inactive and the self-refresh enable signal is inactive, the clock buffer operates at a second driving capability smaller than the first driving capability. Therefore, current consumption by the clock buffer is reduced.

[0020] Preferably, the clock buffer includes a first inverter and a second inverter. The first inverter operates when the clock enable signal is active and stops when the clock enable signal is inactive. The second inverter has a smaller driving capability than the first inverter, and is connected in parallel with the first inverter. Further, the second inverter operates when the self-refresh enable signal is inactive and stops when the self-refresh enable signal is active.

In the synchronous semiconductor memory device, when the clock enable signal is inactive and the self-refresh enable signal is inactive, the first inverter stops and the second inverter operates. Therefore, the current consumption of the clock buffer is reduced by the current consumption of the first inverter.

Preferably, the first inverter includes a first P-channel MOS transistor, a first switch transistor, a first N-channel MOS transistor, and a second switch transistor. The first P-channel MOS transistor is connected between a power supply node and an output node, and has a gate receiving an external clock signal. The first switch transistor is connected in series with the first P-channel MOS transistor between the power supply node and the output node, and is turned on when the clock enable signal is active, and is turned on when the clock enable signal is inactive. Turn off. The first N-channel MOS transistor is connected between an output node and a ground node, and has a gate receiving an external clock signal. The second switch transistor is connected in series with the first N-channel MOS transistor between the output node and the ground node, is turned on when the clock enable signal is active, and is turned on when the clock enable signal is inactive. Turn off. Further, the second inverter includes a second P-channel MOS transistor, a third switch transistor, and a second N-channel MOS transistor.
It includes a channel MOS transistor and a fourth switch transistor. The second P-channel MOS transistor has a smaller size than the first P-channel MOS transistor, is connected between a power supply node and an output node, and receives an external clock signal at a gate. A third switch transistor connected in series with the second P-channel MOS transistor between the power supply node and the output node;
It turns on when the self-refresh enable signal is inactive, and turns off when the self-refresh enable signal is active. The second N-channel MOS transistor has a smaller size than the first N-channel MOS transistor, is connected between an output node and a ground node, and has a gate receiving an external clock signal. The fourth switch transistor is connected in series with the second N-channel MOS transistor between the output node and the ground node, is turned on when the self-refresh enable signal is inactive, and is turned on when the self-refresh enable signal is active. Turns off once.

In the above synchronous semiconductor memory device, when the clock enable signal is inactive and the self refresh enable signal is inactive, the first and second switch transistors are turned off. Stops. Therefore, the current consumption of the clock buffer is reduced by the current consumption of the first inverter.

Preferably, the clock buffer includes a first P-channel MOS transistor, a first N-channel MOS transistor, a second P-channel MOS transistor, a first switch transistor, and a third N-channel MOS transistor.
It includes a channel MOS transistor and a second switch transistor. The first P-channel MOS transistor is connected between a power supply node and a ground node, and has a gate and a drain connected to each other. The first N-channel MOS transistor is connected between the drain of the first P-channel MOS transistor and a ground node, and receives a reference voltage at a gate. A second P-channel MOS transistor is connected between the power supply node and the output node;
The gate is connected to the gate of the first P-channel MOS transistor. The second N-channel MOS transistor is connected between an output node and a ground node, and has a gate receiving an external clock signal. The first switch transistor is connected in series with the second N-channel MOS transistor between the output node and the ground node, and is turned on when the clock enable signal is active, and is turned on when the clock enable signal is inactive. Turn off. Third N
The channel MOS transistor has a second N-channel MO
It has a smaller size than the S transistor, is connected in parallel with the second N-channel MOS transistor between the output node and the ground node, and receives an external clock signal at its gate. The second switch transistor is connected in series with the third N-channel MOS transistor between the output node and the ground node, is turned on when the self refresh enable signal is inactive, and is turned on when the self refresh enable signal is active. Turns off once.

In the above synchronous semiconductor memory device, when the clock enable signal is inactive and the self-refresh enable signal is inactive, the first switch transistor is turned off and the second switch transistor is turned on. Become. Therefore, the second N channel M
The current consumption by the clock buffer is reduced by the current consumption of the OS transistor.

[0026]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

[First Embodiment] FIG. 1 is a block diagram showing a part of a configuration of a synchronous DRAM according to a first embodiment of the present invention. Referring to FIG. 1, this synchronous DRAM includes a self-refresh mode detecting circuit 10.
, CKEPC generation circuit 11 and address buffer 12
, Clock buffer CB, and internal clock generation circuit 1
3 and an input / output pin 14 for receiving an external signal.

Self-refresh mode detection circuit 10
Generates a self-refresh enable signal SRE in response to an external row address strobe signal / RAS, an external column address strobe signal / CAS, and a clock enable signal CKE.

CKEPC generation circuit 11 generates signal / CKEPC in response to clock enable signal CKE.

The address buffer 12 includes a buffer AB0
-ABn. Buffers AB0-ABn are CKEP
When signal / CKEPC from C generating circuit 11 is at L level, external address signals AD0-ADn are buffered and output as internal address signals IAD0-IADn,
When the output signal / CKEPC from the CKEPC generation circuit 11 is at the H level, the operation is stopped. Note that internal address signals IAD0-IADn are applied to row address strobe signal / R
AS, and is supplied to a row decoder (not shown) or a column decoder (not shown) in response to a column address signal / CAS.

The clock buffer CB is a P-channel MO
S transistor SWP1, SWP2, LPT, SPT
And N channel MOS transistors SWN1 and SWN
2, LNT, SNT, and inverters 21-23. P-channel MOS transistor SWP1 is connected between power supply node Vdd and the source of P-channel MOS transistor LPT, and turns on / off in response to an output signal / CKEPC from CKEPC generation circuit 11. P-channel MOS transistor LPT is an N-channel MOS
It has a size larger than the transistor SPT, is connected between the drain of the P-channel MOS transistor SWP1 and the output node OUT, and has a gate connected to the external clock signal Ext. CLK. P-channel MOS transistor SWP2 is connected between power supply node Vdd and the source of P-channel MOS transistor SPT, and turns on / off in response to self-refresh enable signal SRE. P-channel MOS transistor SPT has a smaller size than P-channel MOS transistor LPT, is connected between the drain of P-channel MOS transistor SWP2 and output node OUT, and has its gate connected to external clock signal Ext. CLK. N channel MOS
Transistor SWN1 is connected between output node OUT and the drain of N-channel MOS transistor LNT, and turns on / off in response to an output signal from inverter 21. N-channel MOS transistor LNT has a larger size than N-channel MOS transistor SNT, is connected between the source of N-channel MOS transistor SWN1 and ground node GND, and has an external clock signal Ext. CLK. N channel MOS
Transistor SWN2 is connected between output node OUT and the drain of N-channel MOS transistor SNT, and turns on / off in response to an output signal from inverter 22. N-channel MOS transistor SNT has a smaller size than N-channel MOS transistor LNT, is connected between the source of N-channel MOS transistor SWN2 and ground node GND, and has an external clock signal Ext. CLK. Inverter 21
Is the output signal / CKEP from the CKEPC generation circuit 11.
Invert C. Inverter 22 inverts self-refresh enable signal SRE. The inverter 23
Invert the voltage of the output node OUT. The output from the inverter 23 becomes the clock buffer signal BUFCLK.

Internal clock generation circuit 13 responds to clock buffer signal BUFCLK to generate internal clock signal i.
nt. CLK.

Next, the operation of the synchronous DRAM configured as described above will be described with reference to (a) the normal mode and (b)
The case of the power down mode and (c) the self refresh mode will be described.

(A) Normal Mode Referring to FIG. 2, when clock enable signal CKE is at H level, the synchronous DRAM is in the normal mode.

At this time, the output signal / CKEPC from the CKEPC generation circuit 11 goes low. As a result, the buffers AB0-ABn in the address buffer 12
Is activated. P-channel MOS transistor SWP1 and N-channel MOS transistor SWN1
Turns on. Therefore, P-channel MOS transistor LPT and N-channel MOS transistor LNT
And an external clock signal E
xt. CLK is inverted and output to output node OUT.

The self refresh enable signal SRE goes to L level. Thereby, the P channel M
OS transistor SWP2 and N-channel MOS transistor SWN2 are turned on. Therefore, an external clock signal Ext. Is also provided by an inverter composed of P-channel MOS transistor SPT and N-channel MOS transistor SNT. CLK is inverted and output to output node OUT.

As described above, in the normal mode, the inverter composed of the P-channel MOS transistor LPT and the N-channel MOS transistor LNT and the P-channel MOS transistor
Transistor SPT, N-channel MOS transistor S
NT with the external clock signal Ext. CLK is inverted and output to output node OUT, which is inverted by inverter 23 and output as clock buffer signal BUFCLK. In response to clock buffer signal BUFCLK, internal clock signal int. CL
K is generated.

(B) Power Down Mode Referring to FIG. 3, when clock enable signal CKE is at L level, the synchronous DRAM enters a power down mode.

At this time, the output signal / CKEPC from the CKEPC generation circuit 11 goes high, and the buffers AB0-ABn in the address buffer 12 stop. Further, since the P-channel MOS transistor SWP1 and the N-channel MOS transistor SWN1 are turned off,
P channel MOS transistor LPT, N channel MO
The inverter constituted by the S transistor LNT stops.

On the other hand, since self-refresh enable signal SRE is at L level, P-channel MOS transistor SWP2 and N-channel MOS transistor
WN2 turns on. Therefore, P-channel MOS transistor SPT and N-channel MOS transistor SN
External clock signal E
xt. CLK is inverted and output to output node OUT, which is inverted by inverter 23 and output as clock buffer signal BUFCLK.

The internal clock generation circuit 13 outputs the signal / CK
While EPC is at the H level, internal clock signal int. CL
Stop generation of K.

When the clock enable signal CKE changes from the L level to the H level, the power down mode ends.
Accordingly, the signal / CKEPC changes from the H level to the L level, and the synchronous DRAM enters the normal mode.

As described above, in the power down mode, the P-channel MO having a large size, ie, a large current consumption, is used.
The inverter composed of the S transistor LPT and the N channel MOS transistor LNT stops, and the inverter composed of the P channel MOS transistor SPT and the N channel MOS transistor SNT having a small size, ie, consuming less current, operates. Therefore, the current consumption in clock buffer CB is reduced by the current consumption by P-channel MOS transistor LPT and N-channel MOS transistor LNT.

(C) Self-refresh mode Referring to FIG. 4, when clock enable signal CKE, row address strobe signal / RAS, and column address strobe signal / CAS attain L level simultaneously, the synchronous DRAM enters the self-refresh mode. Become.

At this time, the output signal / CKEPC from the CKEPC generation circuit 11 goes high, and the buffers AB0-ABn in the address buffer 12 stop. Further, since the P-channel MOS transistor SWP1 and the N-channel MOS transistor SWN1 are turned off,
P channel MOS transistor LPT, N channel MO
The inverter constituted by the S transistor LNT stops.

Further, since self-refresh enable signal SRE attains an H level, P-channel MOS transistor SWP2 and N-channel MOS transistor SWN2 are turned off. Thereby, the P-channel MOS
Transistor SPT, N-channel MOS transistor S
The inverter composed of NT also stops.

Therefore, clock buffer CB is completely stopped, and clock buffer signal BUFCLK is not output. The internal clock generation circuit 13 generates the internal clock signal int. Stop generation of CLK.

When the clock enable signal CKE changes from L level to H level, the self refresh mode ends. Accordingly, signal / CKEPC and self-refresh signal SRE change from the H level to the L level to enter the normal mode. However, in consideration of the case where the clock enable signal CKE becomes H level during the refresh,
After the predetermined time tSRC elapses after KE becomes H level, the next command cannot be input until the time tRC further elapses. Here, the time tRC is the minimum time required to refresh one row of the memory.

As described above, in the self refresh mode, the address buffer 12 and the clock buffer CB
Stops. Therefore, current consumption in the address buffer 12 and the clock buffer CB is reduced.

As described above, according to the first embodiment, the P-channel MOS transistor LPT and the N-channel MOS transistor LPT having a large size, ie, large current consumption, and a P-channel having a small size, ie, small current consumption, are employed. MOS transistor SPT and N-channel MOS transistor SNT are provided, and in power down mode, P-channel MOS transistor LP
The inverter constituted by the T and N channel MOS transistors LNT stops, and the inverter constituted by the P channel MOS transistor SPT and the N channel MOS transistor SNT operates. As a result, in power down mode, P-channel MOS transistor L
The current consumption in the clock buffer CB is reduced by the current consumption by the PT and N-channel MOS transistors LNT.

Note that address buffer 12 shown in the first embodiment is merely an example of an input buffer whose operation / stop is controlled by output signal / CKEPC from CKEPC generating circuit 11. Therefore, similarly to the address buffer 12, the operation / stop of the input buffer other than the clock buffer included in the synchronous DRAM is controlled by the output signal / CKEPC from the CKEPC generation circuit 11.

[Embodiment 2] Embodiment 2 of the present invention
Has a clock buffer shown in FIG. 5 instead of the clock buffer CB shown in FIG.

Referring to FIG. 5, this clock buffer includes P-channel MOS transistors 30, 31 and N-channel MOS transistors 32, SWN3, SWN4,
LNT1, SNT1 and inverters 33-35 are provided.

P channel MOS transistor 30 is connected between power supply node Vdd and the drain of N channel MOS transistor 32, and has a gate and a drain connected to each other. N channel MOS transistor 32
Is connected between the drain of P-channel MOS transistor 30 and ground node GND, and has a reference voltage V
Receive ref. P channel MOS transistor 31
Is connected between the power supply node Vdd and the output node OUT, and has a gate connected to the gate of the P-channel MOS transistor 30. Inverter 33 inverts output signal / CKEPC from CKEPC generating circuit 11 shown in FIG. The N-channel MOS transistor SWN3 is
Output node OUT and N-channel MOS transistor LN
It is connected between the drain of T1 and turned on / off in response to an output signal from the inverter 33. N-channel MO
S transistor LNT1 has a larger size than N channel MOS transistor SNT1, and
Source of OS transistor SWN3 and ground node GND
And an external clock signal Ext.
CLK. Inverter 34 inverts self-refresh enable signal SRE from self-refresh mode detection circuit 10 shown in FIG. N-channel MOS transistor SWN4 is connected between output node OUT and N
It is connected between the drain of the channel MOS transistor SNT1 and turned on / off in response to an output signal from the inverter 34. N-channel MOS transistor SNT
1 has a smaller size than the N-channel MOS transistor LNT, and
4 is connected between the source of the external clock signal Ext. CLK. Inverter 35 inverts the voltage of output node OUT and outputs the result as clock buffer signal BUFCLK.

Next, the operation of the clock buffer configured as described above will be described in the case of (a) the normal mode, (b) the power down mode, and (c) the self refresh mode.

(A) Normal mode As in the first embodiment, the clock enable signal CKE
Is at the H level, the synchronous DRAM enters the normal mode.

At this time, output signal / CKEPC from CKEPC generating circuit 11 and self-refresh enable signal SRE attain L level, and N-channel MOS transistors SWN3 and SWN4 are turned on.

As a result, P-channel MOS transistors 30 and 31, N-channel MOS transistors 32 and LN
A current mirror circuit is constituted by T1 and SNT1.
Therefore, the output node OUT is, as shown in FIG.
External clock signal Ext. When CLK is lower than reference voltage Vref, it is at H level, and when it is higher, it is at L level. The value of output node OUT is inverted by inverter 35 to become clock buffer signal BUFCLK. Further, similarly to the first embodiment, the clock buffer signal B
In response to UFCLK, internal clock signal int. CLK is generated.

As described above, in the normal mode, the external clock signal Ext. Is controlled by the current mirror circuit composed of the P-channel MOS transistors 30 and 31, the N-channel MOS transistors 32, LNT1 and SNT1. CL
Clock buffer signal BUFCLK is output in response to K.

(B) Power-down mode As in the first embodiment, the clock enable signal CKE
Is at the L level, the synchronous DRAM enters the power down mode.

At this time, the output signal / CKEPC from the CKEPC generation circuit 11 goes high, and the N-channel M
The OS transistor SWN3 is turned off.

On the other hand, since self-refresh enable signal SRE is at L level, N-channel MOS transistor SWN4 is turned on.

As a result, P-channel MOS transistors 30 and 31, N-channel MOS transistors 32 and SN
A current mirror circuit is configured by T1. Therefore, as in the normal mode, the output node OUT is connected to the external clock signal Ext. When CLK is lower than reference voltage Vref, it is at H level, and when it is higher, it is at L level. The value of output node OUT is inverted by inverter 35 to become clock buffer signal BUFCLK.

Similarly to the first embodiment, internal clock generating circuit 13 generates internal clock signal int.CLK while signal / CKEPC is at H level. Stop generation of CLK.

When the clock enable signal CKE changes from L level to H level, the power down mode ends.
Accordingly, the signal / CKEPC changes from the H level to the L level, and the synchronous DRAM enters the normal mode.

As described above, in the power down mode, P
Channel MOS transistors 30, 31, N-channel M
OS transistor 32, SNT1 and the external clock signal Ext. CLK
, Clock buffer signal BUFCLK is output. Therefore, the current consumption of the clock buffer is reduced by an amount corresponding to the current consumption by the large-sized, ie, large current consumption, N-channel MOS transistor LNT1.

(C) Self-refresh mode As in the first embodiment, the clock enable signal CK
When E, the row address strobe signal / RAS, and the column address strobe signal / CAS attain the L level simultaneously, the synchronous DRAM enters the self-refresh mode.

At this time, the output signal / CKEPC from CKEPC generation circuit 11 attains an H level, and N channel M
The OS transistor SWN3 is turned off.

Further, since self-refresh enable signal SRE attains an H level, N-channel MOS transistor SWN4 is turned off.

Therefore, the clock buffer is completely stopped, and no clock buffer signal BUFCLK is output. The internal clock generation circuit 13 generates the internal clock signal int. Stop generation of CLK.

As in the first embodiment, when the clock enable signal CKE changes from the L level to the H level, the self-refresh mode ends.

As described above, in the self-refresh mode, the clock buffer stops. Therefore, current consumption in the clock buffer is reduced.

As described above, according to the second embodiment, N-channel MOS transistor LNT1 having a large size, ie, consuming a large amount of current, and N-channel MOS transistor SNT1 having a small size, ie, consuming a small amount of current are provided. In the power down mode, N channel MOS transistor LNT1 stops. As a result,
In the power down mode, the current consumption in the clock buffer is reduced by the current consumption by N channel MOS transistor LNT1.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0075]

The synchronous semiconductor memory device according to one aspect of the present invention has a second drive capability smaller than the first drive capability when the clock enable signal is inactive and the self refresh enable signal is inactive. Since the clock buffer operating with the driving ability of the clock buffer is provided, the current consumption by the clock buffer is reduced.

The clock buffer has a first inverter that operates when the clock enable signal is active and stops when the clock enable signal is inactive, and a drive capability smaller than the first inverter. A second inverter that operates when the self-refresh enable signal is inactive and stops when the self-refresh enable signal is active, so that the clock enable signal is inactive and the self-refresh enable signal is inactive. At one time, the current consumption by the clock buffer is reduced by the current consumption of the first inverter.

The first inverter includes a first P-channel MOS transistor, a first N-channel MOS transistor, and first and second switch transistors, and the second inverter has a first P channel MO
A second P-channel MOS transistor having a size smaller than that of the S transistor, and a first N-channel MOS transistor
When the clock enable signal is inactive and the self-refresh enable signal is inactive, the second N-channel MOS transistor having a smaller size than the transistor and the third and fourth switch transistors are included. The current consumption by the clock buffer is reduced by the current consumption of the one P-channel MOS transistor and the first N-channel MOS transistor. The clock buffer includes first and second P-channel MOS transistors, first and second N-channel MOS transistors, and a third N-channel MOS transistor having a size smaller than that of the second N-channel MOS transistor. And the first and second switch transistors, so that when the clock enable signal is inactive and the self-refresh enable signal is inactive, the clock buffer corresponds to the current consumed by the second N-channel MOS transistor. Current consumption is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a part of a configuration of a synchronous DRAM according to a first embodiment of the present invention;

FIG. 2 is a timing chart for explaining an operation in a normal mode of the synchronous DRAM shown in FIG. 1;

FIG. 3 is a timing chart for explaining an operation in a power down mode of the synchronous DRAM shown in FIG. 1;

FIG. 4 is a timing chart for explaining an operation in a self-refresh mode of the synchronous DRAM shown in FIG. 1;

FIG. 5 is a block diagram showing a configuration of a clock buffer according to a second embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of the clock buffer shown in FIG. 5;

FIG. 7 is a block diagram showing a part of a configuration of a conventional synchronous DRAM.

8 is a timing chart for explaining an operation in a power down mode of the synchronous DRAM shown in FIG. 7;

9 is a timing chart for explaining an operation in a self-refresh mode of the synchronous DRAM shown in FIG. 7;

[Explanation of symbols]

10 self-refresh mode detection circuit, 12 address buffers, 30, 31, SWP1, SWP2, LP
T, SPT P-channel MOS transistor, 32, S
WN1-SWN4, LNT, SNT, LNT1, SNT
1 N-channel MOS transistor, CB clock buffer, Vdd power supply node, GND ground node, OU
T output node, Vref reference voltage, CKE clock enable signal, SRE self-refresh enable signal, Ext. CLK external clock signal, in
t. CLK Internal clock signal.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Tatsuya Fukuda 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term in Mitsubishi Electric Corporation (reference) 5B024 AA01 BA29 CA07 DA18

Claims (4)

[Claims] A self-refresh mode detection circuit for generating a self-refresh enable signal in response to an external signal; and operating to generate an internal signal in response to an external signal when a clock enable signal is active, An input buffer that stops when an enable signal is inactive; and a clock buffer that generates an internal clock signal in response to an external clock signal, wherein the clock buffer has the clock enable signal active and the self refresh When the enable signal is inactive, the first
And operates at a second driving ability smaller than the first driving ability when the clock enable signal is inactive and the self-refresh enable signal is inactive. A synchronous semiconductor memory device which is inactive and stops when said self-refresh enable signal is active. 2. The clock buffer operates when the clock enable signal is active,
A first inverter that stops when the clock enable signal is inactive; a first inverter that has a smaller driving capability than the first inverter; is connected in parallel with the first inverter; 2. The synchronous semiconductor memory device according to claim 1, further comprising: a second inverter that operates when active and stops when said self-refresh enable signal is active. A first P-channel MOS transistor connected between a power supply node and an output node, the gate of which receives the external clock signal at a gate; and a first inverter connected between the power supply node and the output node. Between the first P
A first switch transistor connected in series with the channel MOS transistor and turned on when the clock enable signal is active, and turned off when the clock enable signal is inactive; A first N-channel MO connected between the gates and receiving the external clock signal at its gate
S transistor; and the first N transistor between the output node and the ground node.
A second switch transistor connected in series with the channel MOS transistor and turned on when the clock enable signal is active, and turned off when the clock enable signal is inactive; A second P-channel MOS transistor having a size smaller than that of the first P-channel MOS transistor, connected between the power supply node and an output node, and receiving the external clock signal at a gate; Between the second node and the output node
A third switch transistor connected in series with a channel MOS transistor, which is turned on when the self-refresh enable signal is inactive and turned off when the self-refresh enable signal is active; A second N-channel MOS transistor having a smaller size than a MOS transistor, connected between the output node and the ground node, and receiving the external clock signal at a gate; The second N
A fourth switch transistor connected in series with the channel MOS transistor and turned on when the self-refresh enable signal is inactive and turned off when the self-refresh enable signal is active. 10. The synchronous semiconductor memory device according to claim 1. 4. A first P-channel MOS transistor, wherein the clock buffer is connected between a power supply node and a ground node, and has a gate and a drain connected to each other.
A transistor, a first N-channel MOS transistor connected between the drain of the first P-channel MOS transistor and the ground node and receiving a reference voltage at a gate, a connection between the power supply node and the output node A second P-channel MOS transistor having a gate connected to the gate of the first P-channel MOS transistor, a second P-channel MOS transistor connected between the output node and the ground node, and a gate receiving the external clock signal at a gate. 2 N channel MOS transistors, and the second N channel MOS transistor between the output node and the ground node.
A first switch transistor connected in series with a channel MOS transistor and turned on when the clock enable signal is active, and turned off when the clock enable signal is inactive; and a second N-channel MOS transistor A third N-channel MOS transistor having a smaller size, connected between the output node and the ground node in parallel with the second N-channel MOS transistor, and having a gate receiving the external clock signal; The third N between the output node and the ground node;
A second switch transistor connected in series with the channel MOS transistor and turned on when the self-refresh enable signal is inactive and turned off when the self-refresh enable signal is active. 10. The synchronous semiconductor memory device according to claim 1.