JPH11232870A - Semiconductor memory element having back gate voltage controlling delay circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory element whose dependence on power source voltage is lowered and which has a delay circuit for accessing data at high speed. SOLUTION: A semiconductor memory element is provided with an address buffer 200, a pre-decoder circuit 202, a memory circuit 204, a main amplifier 216, an address transition detection(ATD) pulse generating circuit 204 and a pulse delaying circuit 208. Moreover, the element includes a voltage generator generating back voltage. The back gate voltage is supplied to the address transition (ATD) pulse generating circuit 204 and the pulse delaying circuit 208 as a low voltage source VBB. Since delay control of the address transition detection(ATD) pulse generating circuit 204 and the pulse delaying circuit 208 is made by the back gate voltage VBB, the dependence of the memory element on high voltage VDD is lowered.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to semiconductor memory devices, and more particularly, to a back gate voltage (V _BB ) control delay circuit.
d delay circuit).

[0002]

BACKGROUND OF THE INVENTION It is becoming increasingly advantageous to reduce the supply voltage of semiconductor chips, especially memory devices, and to reduce power consumption. As a result, corresponding scaling methods have been developed to form integrated circuit devices in order to reduce supply voltage and power consumption. One of the problems with the scaling method is that the threshold voltage (V _TH ) of the transistor element is very low because the sub-threshold current of the transistor element is very constant.
Does not directly follow the scaling method, and the standby leakage current cannot be minimized. In this situation, in many devices, the dependence of the signal access time on the supply voltage becomes large, and the access time may be delayed.

[0003]

SUMMARY OF THE INVENTION The present invention discloses a semiconductor memory device having a back gate voltage (V _BB ) control delay circuit which seeks to have an advantage over prior art semiconductor memory device designs. It is.

[0004]

According to one aspect of the present invention, a semiconductor memory device has an address buffer. A pre-decoder circuit receives the output of the address buffer, and a memory array receives the output of the pre-decoder circuit. Meanwhile, the main amplifier receives the output of the memory array. Address transition detection (ATD: addres
s transition detector) The pulse generation circuit is also
The output of the buffer is received, and the pulse delay circuit receives the output of the address transition detection pulse generation circuit. The pulse delay circuit supplies the main amplified signal to the main amplifier. Further, the aforementioned memory device includes a voltage generator for generating a back gate voltage. The back gate voltage is supplied as a low voltage source (V _BB ) to an address transition detection (ATD) pulse generation circuit and a pulse delay circuit. The delay of the address transition detection (ATD) pulse generator and pulse delay circuit is controlled by the back gate voltage (V _BB ), reducing the dependence of the memory element on the high voltage source (V _DD ).

A technical advantage of the present invention is to provide a delay circuit which has low dependency on a power supply voltage and can realize a high data access time.

Further, the delay circuit is a voltage variable level converter.
(voltage swing level converter), and V _BB -V _DD
It is constituted by a voltage variable delay circuit. This delay circuit can use the same voltage source (V _BB ) as the back gate voltage of the memory array. Furthermore, the delay circuit
A separate V _BB generator with voltage level adjustment can be used and process parameter variations can be ignored.

[0007] Further technical advantages of the present invention will be apparent from the drawings, detailed description and claims.

[0008] The invention and its advantages may be better understood with reference to the following description taken in conjunction with the accompanying drawings. In the drawings, like reference numerals indicate like structures.

[0009]

FIG. 1 is a circuit diagram of a conventional address access (tAA) path for a dynamic random access memory (DRAM) device. As shown, an external address (Ax) is provided to the address buffer 10. Address buffer 10 is coupled to predecoder circuit 12 and address transition detection (ATD) circuit 14. The pre-decoder circuit 12 is coupled to a Y-decoder circuit 16, and the Y-decoder circuit 16
It is coupled to an array 18. The memory array 18
It provides an output to I / O switch 20, while I / O switch 20 provides a signal to main amplifier 22. The ATD circuit 14 also supplies a signal to the main amplifier 22. Main amplifier 22
Supplies the output to an output buffer 24, while the output amplifier 24 provides an external output (DQ).

FIG. 1 shows a typical address access (tAA) path for a DRAM. After the external address (Ax) is switched, the output signal of the address buffer 10 (AI) is supplied. The signal (AI) is connected to both the predecoder circuit 12 and the ATD circuit 14. Therefore, the access path is divided into two paths at this position. One path is for memory array 1
8 and the memory array 18 contains AY, YS, IO
Signals that reach the main amplifier 22, called MIO pairs, are used. The signal (AY) is an output signal of the pre-decoder circuit 12 and is supplied to the Y-decoder circuit 16. The Y-decoder circuit 16 sends the signal (YS) on the Y-select line into the memory array 18 and selects one of the sense amplifiers in the memory array 18. The selected sense amplifier feeds data to main amplifier 22 via I / O switch 20 on the IO pair and MIO pair lines. As can be understood from FIG. 1, the delay time of the memory array path is mainly composed of the RC delay of a long signal line.

The other signal path is an ATD path. A
The output signal (MA) of the TD circuit 14 is an enable signal for the main amplifier 22. The signal (MA) must wait for data from the memory array 18 and enable the main amplifier 22 when the MIO pair has developed a sufficient voltage difference. It should be understood that the delay of the ATD path is mainly composed of an inherent circuit delay. The access time for the memory element of FIG. 1 essentially corresponds to the signal (MA). The faster (MA), the faster the access time, but the MA must occur after the MIO data has been obtained and is therefore limited by the speed of the MIO. Thus, by minimizing the timing margin from MIO to MA, it is possible to design to achieve fast access times.

However, as a problem associated with the design for minimizing the timing margin, there is a dependency on the power supply voltage of the delay time when the above-mentioned circuit accesses the path. Since the memory array path includes an RC delay,
The dependence on the power supply voltage is relatively low. However,
Since the ATD path includes a circuit delay, the dependency on the power supply voltage is relatively large. As a result, even if the MIO and MA timings are designed such that the margin is minimized in the high voltage state, if the voltage dependence of the ATD path is large, the timing margin will be large in the low voltage state. Therefore, the present invention provides a delay circuit which has low dependency on a power supply voltage and which can realize a shortened access time.

FIGS. 2A and 2B are circuit diagrams of a delay circuit capable of realizing low dependency on a power supply voltage. As shown in FIG. 2A, inverters 30 and 32
Are coupled in series with the resistor 34. The input signal is N
The input signal is supplied to one input of an OR gate 36 and the input signal passes through a resistor 34. The output of NOR gate 36 is provided to inverter 38, which in turn provides this signal to resistor 40. Next, the input signal is
It is provided as an input to a gate 42. NOR gate 42
Also receives the voltage on the resistor 40. The circuit of FIG. 2A uses a resistive element (such as a diffused layer resistor) in the delay circuit. Normally, this circuit requires that the resistors 34 and 40 occupy a large surface area and sufficiently reduce the voltage dependence. As a result, this circuit realizes low dependency, but has a problem that the layout area becomes large. This layout area is two to three times larger than a transistor delay circuit that achieves low dependence on the supply voltage.

FIG. 2B shows another circuit. This circuit has an inverter 44, which is a P-channel transistor 4
6 and N-channel transistor 48. On the other hand, NOR gate 50 receives the input signal and the output of transistor pair 46,48. The output of NOR gate 50 is provided to another pair, P-channel transistor 52 and N-channel transistor 54, while these transistor pairs provide inputs to NOR gate 56. As shown, the other input of the NOR gate 56 is an input signal. This circuit also has problems. Typically, the circuit of FIG. 2B uses a low threshold voltage transistor for the delay element. The use of such a transistor has the same effect as following the scaling method. The result is a problem of large standby leakage currents and the need for additional process steps to increase the threshold voltage.

FIG. 3 is a block diagram of a delay circuit constructed according to the present invention. As shown, the delay circuit includes a voltage variable level converter 60, which receives an input signal (IN). The level converter 60 supplies the output signal (N1) to the delay circuit 62. On the other hand, the delay circuit 6
2 provides an output signal (OUT) as shown. Both the voltage variable level converter 60 and the delay circuit 62 receive the back gate voltage _VBB as a low power supply. During operation, the voltage variable level converter 60 changes the voltage variable range of the input signal (IN) to V _SS −V _{DD in the} intermediate signal (N1).
To change to the V _BB -V _DD from. Then, the delay circuit 62
It operates in the signal variable range of V _BB -V _DD .

FIG. 4 shows one embodiment of the delay circuit of FIG. 3 according to the present invention.
It is a circuit diagram of an embodiment. The circuit shown in FIG.
A circuit 14 can be formed. As shown in FIG.
Level shifter circuit 64 (similar to level converter 60 in FIG. 3)
Alike) is coupled to the delay circuit 66. level·
The shifter circuit 64 includes an inverter 68 and a P-channel transformer.
Transistor 70, N-channel transistor 72, N-ch
Channel transistor 74, P-channel transistor
76 and two N-channels connected as shown.
Including the channel transistors 78 and 80. These elements
Is a high voltage source V_DDAnd low voltage source V_BBTo
receive. The level shifter circuit 64 _SS-V_DDPossible
Receiving an input signal (IN) having a variable range;
And V_BB-V_DDInto a signal having a variable range of

The delay circuit 66 includes a P-channel transistor 82 and an N-channel transistor 84, which receive the output of the level shifter circuit 64. These transistors then feed two P-channel transistors 88,90 and N-channel transistors 86,92. The next stage includes a P-channel transistor 94 and an N-channel transistor 96. In addition, transistors 100 and 10
A similar structure is obtained by 2,104,106,108,110. Further, transistors 112, 114,
Similar structures are provided by 116, 118, 120, 122. Finally, transistors 124 and 12
6, 128 supply the inverter 130. Delay circuit 66
The internal elements are V _BB −V _DD of the output of the level shifter 64.
Operates to convert the variable range and delay its output.

FIG. 5 is a circuit diagram of one embodiment of a conventional delay circuit which can be compared with the delay circuit of FIG. The function of the circuit of FIG. 5 is as follows: level shifter circuit 140 and V _SS -V
It is the same as that of FIG. 4 except for the voltage variable level of _DD . As shown in FIG. 5, the level shifter circuit 140
It is connected to the delay circuit 142. The level shifter circuit 140 includes an inverter 144 and transistors 146, 148, 150, 15 interconnected as shown.
2,154,156. This stage includes a delay circuit 142
Is supplied. Delay circuit 142 includes P-channel transistors 158, 164, 166, 170, 176, 1
78,182,188,190 and N-channel transistors 160,162,168,172,174,
180, 184, 186, 192. These transistors are interconnected as shown, and inverter 194
Is supplied. Inverter 194 provides an output signal (OUT) of the circuit. As can be seen, the main differences between FIGS. 4 and 5 are the structure of the level shifter circuit 140,
And the source terminal of the N-channel transistor is V _BB
Rather than being connected to V _SS . Due to these differences, the circuit in FIG. 4 can operate with reduced dependency of the delay time on the power supply voltage.

FIG. 6 shows the circuit of FIGS. 4 and 5
6 is a graph of voltage versus time showing voltage dependence of delay time. As shown, the delay change when the power supply voltage level drops is smaller in the circuit of FIG. 4 than in the circuit of FIG. In this example, the transistor parameters are designed so that the same delay is obtained for both circuits, and V _DD is 3.
Equivalent to 7 volts. The broken line shows the characteristics of the conventional circuit of FIG. 5, and the solid line shows the circuit of FIG. As shown in FIG. 6, when the power supply voltage is reduced to make V _DD equal to 2.9 volts, a large difference in delay appears. The circuit of FIG.
The delay is shorter than that of the conventional circuit of FIG. This means that the circuit of FIG. 4 is less dependent on power supply voltage with respect to circuit delay. The graph of FIG. 6 is created for the case where the back gate voltage (V _BB ) is -1.0 volt. _Regardless of the variation of the back gate voltage (V _BB ), FIG.
Can affect the effective operation of the circuit
A recognized concern.

FIG. 7 shows the delay ratio of the circuit of FIG.
Gate voltage (V_BBShows one form of dependency
FIG. For a given back gate voltage (V_BBAbout)
And V _DDWas changed from 3.7 volts to 2.9 volts
The delay ratio in the case was determined. As shown in FIG.
V between_BBThe level dependency is V_BBIs less than -1 volt
Is negligible.

The driving current of the transistor can be expressed by the following equation.

(Equation 1) Here, V _GS is a delay circuit as shown in FIG. 5 (conventional circuit)
Equal to V _DD at Therefore, the ID change rate depends on the power supply voltage as shown below.

(Equation 2)

The following clear conditions are assumed in the simulation of the conventional delay circuit shown in FIG.

V _DD1 = 2.9 V, V _DD2 = 3.7 V, V _TH = 0.8 V (3)

(Equation 4)

The result is that the drive current of the transistor under the 2.9 volt condition is 52.4% of the drive current as compared with the 3.7 volt condition in the conventional delay circuit of FIG.
Means only to drive.

However, the same assumptions for the delay circuit of FIG. 4 are given below.

V _DD1 = 2.9 V− (V _BB ) = 2.9 V − (− 1 V) = 3.9 V V _DD2 = 3.7 V− (V _BB ) = 3.7 V − (− 1 V) = 4 0.7V (5) V _TH = 0.8V

(Equation 6)

As can be seen from these equations, the circuit of FIG. 4 with V _BB as the low supply voltage requires the transistor to operate at 63.2% drive current at 2.9 volts versus 3.7 volts. Drive.

This comparison means that the delay circuit of FIG.
Is slower than the circuit of FIG.
This means that the dependence of the delay time is low. As mentioned above
And V _BBLevels were assumed to be constant during this analysis.
And there is concern. However, V_BBIs the normal boot port
Generated by the_BBLevel is V_DDLes
Has a dependency on the bell. However, the pump
V_BBThe level dependency is V_DDLinearly proportional to the level
And this dependency is usually V_DDSmall against. Also, DR
AM uses a reference voltage regulator to_BBThe non
Always stable control, constant electric field of memory cell array
And high pause refresh characteristics (pause refresh
 characteristic). Therefore, V_BB
Has a significant effect on circuit performance, even if
Does not affect.

FIG. 8 is a block diagram of one embodiment of a memory device constructed according to the present invention. As shown, a common V _BB voltage is provided to the memory array, ATD pulse generator and MA pulse delay circuit. In the memory device of FIG. 8, an address buffer 200 receives an external address (Ax) and supplies a signal to a predecoder circuit 202 and an ATD pulse generator 204. back·
A gate voltage (V _BB ) generator 206 provides the V _BB voltage to the memory array 212 and the ATD pulse generator 204 and MA pulse delay circuit 208. Y-decoder 210 is coupled to memory array 212 and receives signals from predecoder 202. Memory array 21
2 provides a signal to the I / O switch 214 while the I / O switch 214
Switch 214 feeds the signal to main amplifier 216. Main amplifier 216 receives the signal from MA pulse delay circuit 208 and supplies the signal to output buffer 218. On the other hand, output buffer 218 provides an external output (DQ).

FIGS. 9A and 9B are circuit diagrams of a conventional embodiment of the ATD pulse generation circuit 204 of FIG. 8 and an embodiment according to the present invention. As shown in FIG. 9A, the conventional pulse generating circuit 220 includes a transistor connected as shown, V _ss acts as a low power supply voltage. As shown in FIG. 9B, the pulse generation circuit 222 includes transistors connected as shown, and V _BB acts as a low power supply voltage for the most part.

FIGS. 10A and 10B are circuit diagrams of a conventional embodiment of the MA pulse delay circuit 208 of FIG. 8 and an embodiment according to the present invention. The circuit 224 of FIG. 10A is a conventional circuit, and the circuit 226 of FIG. 10B is configured according to the present invention. As shown, the major difference between the two circuits is that the low voltage source of circuit 224 is V _SS , while that of circuit 226 is V _BB .

To illustrate the performance improvement provided by the present invention, an access speed simulation of address access (tAA) can be performed for the memory device of FIG. In this simulation, the ATD pulse generator 204 and MA pulse delay circuit 208
Each has been modified in accordance with the present invention as previously described in FIGS. 9A and 9B and FIGS. 10A and 10B. The parameters of the transistors are designed so that the same delay speed is obtained for both circuits under high access speed conditions. Under this condition, V _DD
Is equal to 3.7 volts, Ta is equal to 0 ° C., and there is a +3 sigma variation in transistor drive current.

FIG. 11 is a graph of voltage versus time showing the result of a simulation comparing delay times under high access speed conditions. The dashed line shows the conventional circuit of FIGS. 9A and 10A, and the solid line shows the circuit of FIGS. 9B and 10B according to the present invention. As can be seen in FIG. 11, both access speeds are essentially the same.

FIG. 12 is a voltage vs. time graph showing the result of a simulation comparing delay times under low access speed conditions. The dashed lines are shown in FIGS. 9A and 10A.
9B and FIG. 10B according to the present invention. Under low access speed conditions, V _DD
Is equal to 2.9 volts, Ta is equal to 90 ° C., and the transistor drive current has a -3 sigma variation. FIG.
As can be seen, for a tAA of about 25 nanoseconds, the access speed of the circuit according to the invention is about one time lower than the conventional circuit.
Nanosecond fast. The MA signal is MIO in FIG.
Note that the pair is activated when the difference is about 140 millivolts. This is typically the minimum timing margin that the MA signal should wait for. In FIG. 12, the circuit of the present invention activates the MA signal when the MIO pair has a 160 millivolt difference. Therefore, it still has a sufficient margin. However, the conventional circuit uses MI
Activate the MA signal when the O pair has a 180 millivolt difference. This is a much larger margin than necessary, and the access time is even slower.

FIG. 13 is a block diagram of another embodiment of the memory device constructed according to the present invention. As shown, the address buffer 230, the predecoder 23
2, ATD pulse generator 234, MA pulse delay circuit 2
40, memory array 244, Y-decoder 242, I
The / O switch 246, the main amplifier 248, and the output buffer 250 are connected to each other and operate in the same manner as the memory device of FIG. However, the difference is that the memory device of FIG. 13 includes two V _BB generators. First V _BB generator 236 is for ATD pulse generator 234 and MA pulse delay circuit 240, and second V _BB generator 238 is for memory array 244. V _BB generator 238 for memory array 244 can generate a stable constant voltage while V _BB for delay
_{The BB} generator 236 can include a voltage level adjustment circuit as shown. The voltage level adjusting circuit is, for example, a laser fused programmi.
ng). Thus, this circuit can be used to control the _VBB level and adjust the delay time (MA and MIO vs. timing margin) for process parameter variations after the wafer process is completed.

Although the present invention has been described in detail,
It will be understood that various changes, substitutions and alterations can be made to the present invention without departing from the spirit and scope defined in the claims.

With respect to the above description, the following items are further disclosed. (1) A semiconductor memory device, comprising an address buffer having an input and an output, a predecoder circuit coupled to receive the output of the address buffer, and coupled to receive an output of the predecoder circuit. A memory array, a main amplifier coupled to receive an output of the memory array, and an address memory.
An address transition detection (ATD) pulse generation circuit coupled to receive the output of the buffer; and a pulse delay circuit coupled to receive the output of the address transition detection pulse generation circuit. A pulse delay circuit coupled to provide a main amplified signal; and a voltage generator for generating a back gate voltage, the voltage generator providing the back gate voltage to cells in the memory array; Address transition detection (AT
D) a pulse generator and the voltage generator coupled to provide as a low voltage source of the pulse delay circuit, wherein the delay of the address transition detection (ATD) pulse generator and the pulse delay circuit comprises: Said back
A semiconductor memory device controlled by a gate voltage and having a low dependence on the high voltage source of the memory device. (2) The semiconductor memory device according to (1), wherein the pulse delay circuit sets the variable range of the input signal to
A voltage level variable range conversion circuit operable to convert to an intermediate signal having a variable range between a gate voltage and the high voltage source; and operable to receive the intermediate signal and provide a delayed output signal. And a delay circuit. (3) The semiconductor memory device according to (2), wherein the voltage level variable range conversion circuit is a level shifter circuit, and the delay circuit is an asymmetric delay circuit. (4) In the semiconductor memory device according to (1), the high voltage source is _VDD , and the back gate voltage is DR.
A semiconductor memory device that is _VBB in an AM device.

(5) A semiconductor device, an address buffer having an input and an output, a predecoder circuit coupled to receive the output of the address buffer, and an output of the predecoder circuit. A mains amplifier coupled to receive the output of the memory array; and an address transition detection (ATD) pulse generation circuit coupled to receive the output of the address buffer. A pulse delay circuit coupled to an output of the address transition detection pulse generation circuit, further comprising: a pulse delay circuit coupled to provide a main amplified signal to the main amplifier; and a first back gate. A first voltage coupled to generate a voltage and supply the first back gate voltage to cells in the memory array. A generator for generating a second back gate voltage and supplying the second back gate voltage to the address transition detection (ATD) pulse generation circuit and the pulse delay circuit as a low voltage source; And a second voltage generator, which detects the address transition (AT
D) A semiconductor memory device in which a delay of a pulse generator and the pulse delay circuit is controlled by the back gate voltage, and the memory device has low dependence on a high voltage source. (6) The semiconductor memory device according to (5), wherein the second voltage generator includes a voltage level adjusting circuit, and uses the voltage level adjusting circuit to adjust the second back gate voltage, thereby reducing the delay. A semiconductor memory element that can be adjusted. (7) The semiconductor memory device according to (5), wherein the pulse delay circuit changes a variable range of the input signal to an intermediate signal having a variable range between the second back gate voltage and the high voltage source. A semiconductor memory device comprising: a voltage level variable range conversion circuit operable to perform conversion; and a delay circuit operable to receive the intermediate signal and supply a delayed output signal. (8) The semiconductor memory device according to (7), wherein the voltage level variable range conversion circuit is a level shifter circuit, and the delay circuit is an asymmetric delay circuit. (9) In the semiconductor memory device according to (5), the high voltage source is _VDD , and the back gate voltage is DR.
A semiconductor memory device that is _VBB in an AM device.

(10) The semiconductor memory element has an address
It has buffers 200 and 230. Predecoder circuit 2
02, 232 receive the output of the address buffers 200, 230, and the memory array 212 receives the output of the predecoder circuit. On the other hand, main amplifiers 216 and 24
8 receives the output of the memory arrays 212,244.
Address transition detection (ATD) pulse generation circuit 204, 2
34 also receives the outputs of the address buffers 200 and 230, and the pulse delay circuits 208 and 240 receive the outputs of the address transition detection pulse generation circuits 204 and 234. In addition, the pulse delay circuits 208 and 240 supply the main amplified signals to the main amplifiers 216 and 248. The memory element further comprises a voltage generator 2 for generating a back gate voltage.
06,236. The back gate voltage is supplied to the address transition detection (ATD) pulse generation circuits 204 and 234 and the pulse delay circuits 208 and 240 by a low voltage source (V _BB ).
Supplied as Address transition detection (ATD) pulse generators 204 and 234 and pulse delay circuits 208 and 2
The delay that 40 has is controlled by the back gate voltage (V _BB ) and is less dependent on the high voltage source (V _DD ) of the memory device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a conventional address access path of a dynamic random access memory (DRAM) device.

FIG. 2 is a circuit diagram of a delay circuit capable of realizing low dependency on a power supply voltage.

FIG. 3 is a block diagram of a delay circuit configured according to the present invention.

FIG. 4 is a circuit diagram of one embodiment of the delay circuit of FIG. 3 according to the present invention.

FIG. 5 is a circuit diagram of one embodiment of a conventional delay circuit that can be compared with the delay circuit of FIG. 4;

FIG. 6 is a voltage vs. time graph showing the voltage dependence of the delay time for the circuits of FIGS. 4 and 5;

FIG. 7 is a diagram showing one form of dependence of the delay ratio of the circuit of FIG. 4 on the back gate voltage (V _BB ).

FIG. 8 is a block diagram of one embodiment of a memory device configured according to the present invention.

FIG. 9A is a circuit diagram of a conventional embodiment of the ATD pulse generation circuit of FIG. 8; 9B is a circuit diagram of an embodiment of the ATD pulse generation circuit of FIG. 8 according to the present invention.

FIG. 10A is a circuit diagram of a conventional embodiment of the MA pulse delay circuit of FIG. 8; FIG. 9B is a circuit diagram of an embodiment of the MA pulse delay circuit of FIG. 8 according to the present invention.

11 is a graph of voltage versus time showing the result of a simulation comparing the delay time in the high access speed state for the memory circuit of FIG. 8;

12 is a voltage vs. time graph showing the result of a simulation comparing the delay time in the low access speed state for the memory circuit of FIG. 8;

FIG. 13 is a block diagram of another embodiment of a memory device configured according to the present invention.

[Explanation of symbols]

10, 200, 230 address buffer, 12, 202, 232 pre-decoder circuit, 14, 204, 234 address transition detection (ATD) pulse generator, 16, 210, 242 Y-decoder circuit, 18, 212, 244 memory Array, 20,214,246 I / O switch, 22,216,248 main amplifier, 24,218,250 output buffer, 30,32,38,44,68,130,142,14
4,194 inverter, 34,40 resistor, 36,42,50,56 NOR gate, 46,52,70,76,82,88,90,94,1
58,164,166,170,176,178,18
2,188,190 P-channel transistors, 48,54,72,74,78,80,84,86,9
2,96,160,162,168,172,174,
180, 184, 186, 192 N-channel transistor, 60 voltage variable level converter, 62, 66, 142 delay circuit, 64, 140 level shifter circuit, 100, 102, 104, 106, 108, 110, 1
12, 114, 116, 118, 120, 122, 12
4,126,128,146,148,150,15
2,154,156 transistor, 204,234 ATD pulse generator, 206 back gate voltage (V _BB ) generator, 208,240 pulse delay circuit, 224,226 circuit, 236 first V _BB generator, 238 2 _VBB generator.

 ──────────────────────────────────────────────────続 き Continued on front page (72) Inventor Tadashi Tachibana 2350 Kihara, Miura-mura, Inashiki-gun, Ibaraki Pref.

Claims (1)

[Claims] 1. A semiconductor memory device, comprising: an address buffer having an input and an output; a predecoder circuit coupled to receive the output of the address buffer; and receiving an output of the predecoder circuit. A mains amplifier coupled to receive the output of the memory array; and an address transition detection (ATD) pulse generation circuit coupled to receive the output of the address buffer. A pulse delay circuit coupled to receive the output of the address transition detection pulse generation circuit, the pulse delay circuit further coupled to provide a main amplified signal to the main amplifier; and a back gate voltage. Wherein the back gate voltage is applied to cells in the memory array. And an address transition detection (ATD) pulse generator, the voltage generator coupled to supply as a low voltage source of the address transition detection (ATD) pulse generation circuit and the pulse delay circuit; A semiconductor memory device, wherein a delay of the pulse delay circuit is controlled by the back gate voltage, and the memory device has low dependence on a high voltage source.