JP2002184177A - Charge pump device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a charge pump device in which a pumping pulse having a stable frequency can be obtained. SOLUTION: In a charge pump device 6 having a charge pump circuit 5 generating boosting voltage supplied to a memory device 7, a pumping pulse based on a system clock is supplied to the charge pump circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a charge pump device for generating a boosted voltage to be supplied to a memory device.

[0002]

2. Description of the Related Art A conventional example of such a charge pump device will be described below with reference to FIG. This charge pump device CPD comprises an internal oscillator OSC and its internal oscillator OC.
It comprises a charge pump circuit CPC to which a pumping pulse from the SC is supplied. Then, the boosted voltage from the charge pump device CPD is transferred to the memory device {D-R
It is supplied to an AM (dynamic RAM) device #M.

[0003]

The frequency of the pulse generated from the internal oscillator OSC depends on its operating voltage, the size (current capability) of an inverter constituting the internal oscillator OSC, the number of stages of the inverter, and the like. The frequency of the pulse generated from the internal oscillator OSC greatly varies depending on the process of the inverter constituting the internal oscillator OSC, the ambient temperature, and the like.

The frequency of the internal oscillator OSC as a pumping pulse generating source is set to be an optimum frequency when the memory device to which the boosted voltage is supplied from the charge pump device CPD is in an operation state where the current load is the largest. Therefore, the current load on the memory device is reduced. For example, in a standby state, the pumping frequency is too high, and unnecessary peak noise is generated. Also, when the memory device is in a standby state, etc.
If the pumping frequency is too high, the voltage detector of the power supply in the memory device will not be able to follow the voltage change,
The voltage generated from the power supply becomes unstable.

In order to make the pumping frequency different depending on whether the memory device is in the operating state or the standby state, a plurality of internal oscillators having different frequencies are provided, and these internal oscillators are provided to the charge pump circuit CPC. It is conceivable to make a switching connection.

However, in this case, the configuration of the pumping pulse generation source becomes complicated, and it becomes difficult to set the frequency of each internal oscillator.

In view of the above, the present invention is to propose a charge pump device capable of obtaining a pump pulse having a stable frequency.

Further, the present invention proposes a charge pump device capable of obtaining a pumping pulse of a stable frequency and obtaining a pumping pulse of an optimum frequency according to the state of a memory device for supplying a boosted voltage. It is assumed that.

[0009]

According to a first aspect of the present invention, in a charge pump device having a charge pump circuit for generating a boosted voltage to be supplied to a memory device, a pump pulse based on a system clock is supplied to the charge pump circuit. FIG.

According to the first aspect, a pumping pulse based on a system clock is supplied to a charge pump circuit.

A second aspect of the present invention is the charge pump device according to the first aspect, further comprising a pumping pulse generating means for generating pumping pulses having different frequencies in accordance with the operation mode of the memory device.

A third aspect of the present invention is the charge pump device according to the second aspect, wherein the frequency of the pumping pulse is increased during the operation of the memory device and decreased during the standby time.

In the first, second, or third charge pump device, the memory device can be a D-RAM device.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an example of a charge pump device according to an embodiment of the present invention will be described in detail with reference to FIG. An example in which a system clock generation circuit is provided in an LSI (large-scale integrated circuit) on which a memory device (here, for example, a D-RAM device) is mounted is described. The system clock CLK (FIG. 4) from the system clock generation circuit 1 of the LSI is supplied to the charge pump device 6 as a pumping pulse.

In the charge pump device 6, the pumping pulse CLK from the system clock generating circuit 1
Is supplied to the double period generating circuit (frequency dividing circuit) 2 to generate a pumping pulse HC having a period twice as long as the pumping pulse CLK.
LK (FIG. 4) is obtained.

Generally speaking, the double period generation circuit 2 has N
A double cycle generation circuit (N = 2, 3, 4,...) Is possible, and the charge pump device 6 in FIG.

The pumping pulses CLK and HCLK are supplied to the selector 3, and a selection control signal, that is, an operation mode signal indicating an operation mode of the memory device (D-RAM device) 7, for example, a row address strobe signal RAS (bar ) (RASbar) (FIG. 4). In this case, when the memory device 7 is in the operating state, the pumping pulse CLK is selected, and when the memory device 7 is in the standby state, the pumping pulse HCLK is selected.

The pumping pulse PLS from the selector 3
(Pumping pulse CLK or HCLK) (FIG. 4)
It is supplied to a charge pump circuit (for example, composed of a CMOS-FET) 5. The boosted voltage from the charge pump circuit 5 is supplied to a memory device (D-RAM device) 7.

FIG. 5 shows a part of the circuit of the D-RAM device 7, wherein RDC is a row decoder, CDC is a column decoder, and CSL.
D is a column select line driver, BL is a bit line (actually plural lines are provided), WL is a word line (actually plural lines are provided), MC is an intersection of the bit line BL and the word line WL. Is shown.

The boosted voltage from the charge pump circuit 5 is applied to the MOS of the row decoder RDC of the D-RAM device 7.
-Applied to the drain of FET Q as a gate boost voltage.

The potential Vcc (V) of the N well and the potential V _B (V) of the P well of the memory cell of the D-RAM device 7 are generated based on the boosted voltage from the charge pump circuit 5.

Next, referring to FIG. 2, the selector 3 shown in FIG.
A specific circuit example will be described. The pumping pulse HCLK from the input terminal 11 is supplied to the NAND gate 14, and the pumping pulse CLK from the input terminal 12 is supplied to the NAND gate 16. The row address strobe signal RAS (bar) from the input terminal 13 is supplied to the NAND gate 14, and the row address strobe signal RAS is supplied.
(Bar) is supplied to the inverter 24 and the row address strobe signal RAS obtained is supplied to the NAND gate 16. The outputs of the NAND gates 14 and 16 are connected to N
An output terminal 18 for supplying a pumping pulse PLS to an AND gate 17
Is derived.

In the selector of FIG. 2, as shown in FIG. 4, a row address strobe signal RAS (bar)
When “1”, PLS = HCLK, and when “0”, PLS = CLK.

Next, referring to FIG. 3, the selector 3 shown in FIG.
Another specific circuit example will be described. The selector in FIG.
This is a case where a CMOS-FET analog switch is used. Reference numerals 25 and 26 are transmission gates composed of CMOS-FETs. The transmission gate connects the drain of the n-channel MOS-FET and the source of the p-channel MOS-FET to serve as an input terminal (or output terminal). Are connected to form an output terminal (or an input terminal) so that a control signal can be supplied to each gate of the n-channel and p-channel MOS-FETs.

Therefore, the pumping pulse HC from the input terminal 21 is applied to the input terminal of the transmission gate 25.
LK, and a pumping pulse CLK from an input terminal 23 to an input terminal of the transmission gate 26. The row address strobe signal RAS from the input terminal 22 is supplied to the gate of the n-channel MOS-FET of the transmission gate 25 and the gate of the p-channel MOS-FET of the transmission gate 26. A row address strobe signal RAS (bar) from the input terminal 22 is supplied to an inverter (CMOS
And a row address strobe signal RAS obtained by supplying the row address strobe signal RAS to the gate of the p-channel MOS-FET of the transmission gate 25 and the n-channel MOS-FE of the transmission gate 26.
Supply to T gate. The output terminals of the transmission gates 25 and 26 are connected to the pumping pulse PL.
Connect to output terminal 27 from which S is output.

In the selector of FIG. 3, as shown in FIG. 4, a row address strobe signal RAS (bar)
When “1”, the transmission gate 25
N, the transmission gate 26 is turned off,
PLS = HCLK, and when "0", the transmission gate 25 is turned off and the transmission gate 26 is turned on, so that PLS = CLK.

Returning to FIG. 1, the description will be continued. D-RAM
In the device 7, when it is in an operating state, a large amount of current is consumed for charging the word line, so that the charge pump device 6 requires a high current supply capability, and therefore, the frequency of the pumping pulse PLS is increased. There is a need to.
In the D-RAM device 7, when this is in the standby state,
Since the word line is in a quiescent state and consumes only a small off-leak current, the charge pump device 6 needs to have a low current supply capability, and therefore the frequency of the pumping pulse PLS is reduced.

The current supply capability of the charge pump circuit 5 is determined by the following equation: operating voltage × capacitance of pumping capacitor × pumping pulse frequency. Since the pumping pulse supplied to the charge pump circuit 5 uses the system clock from the system clock generating circuit 1, the frequency of the pumping pulse becomes stable, and based on this system clock, the period becomes the period of the system clock. 2, 3, 4,
‥‥‥‥ times the number of pumping pulses can be easily obtained.

When the operation frequency of the D-RAM device 7 is high, the frequency of charging the word line with the boosted voltage per unit time increases, but in that case, the frequency of the pumping pulse also increases, and The current supply capacity of the device 6 likewise increases. Conversely, when the operating frequency of the D-RAM device 7 is low, the frequency of charging the word line with the boosted voltage per unit time decreases, but in that case, the frequency of the pumping pulse also decreases, and The current supply capacity of the device 6 is likewise reduced.

In the above example, the D-RAM device 7
Although the case where the charge pump device 6 is provided, the above-described charge pump device 6 may be provided for an S (static) RAM device.

[0031]

According to the first invention, in a charge pump device having a charge pump circuit for generating a boosted voltage to be supplied to a memory device, a pumping pulse based on a system clock is supplied to the charge pump circuit. Therefore, it is possible to obtain a charge pump device that can obtain a stable frequency pumping pulse.

According to the second invention, the charge pump device of the first invention is provided with pumping pulse generation means for generating pumping pulses having different frequencies in accordance with the operation mode of the memory device, so that the charge pump device is stable. It is possible to obtain a charge pump device capable of obtaining a pumping pulse having an optimum frequency while obtaining a pumping pulse having a frequency and according to a state of a memory device supplying a boosted voltage.

According to the third invention, in the charge pump device according to the second invention, the frequency of the pumping pulse is
Because the memory device is set high during operation and low during standby, a stable frequency pumping pulse can be obtained, and a pumping pulse with an optimal frequency can be generated according to the state of the memory device that supplies the boosted voltage. When the current load of the memory device is high, the frequency of the pumping pulse increases to improve the current supply capability, and when the current load of the memory device is low, the frequency of the pumping pulse decreases. As a result, it is possible to obtain a charge pump device capable of avoiding generation of beak noise in the memory device due to the current supply capability being reduced and the frequency of the pumping pulse being too high.

In the first, second or third charge pump device, the memory device can be a D-RAM device.

[Brief description of the drawings]

FIG. 1 is a block diagram of an example of a charge pump device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of a selector of the charge pump device of FIG.

FIG. 3 is a circuit diagram showing another specific example of the selector of the charge pump device of FIG. 1;

FIG. 4 shows the charge pump device of FIG. 1 and FIGS. 2 and 3
6 is a timing chart of each signal in the selector of FIG.

FIG. 5 is a block diagram showing a part of the D-RAM device.

FIG. 6 is a block diagram showing a conventional charge pump device.

[Explanation of symbols]

1 system clock generation circuit, double cycle generation circuit,
3 selector, 4 row address strobe signal RAS
(Bar) input terminal, 5 charge pump circuit, 6 charge pump device, 7 memory device (D-RAM device).

Claims (6)

[Claims] 1. A charge pump device having a charge pump circuit for generating a boosted voltage to be supplied to a memory device, wherein a pump pulse based on a system clock is supplied to the charge pump circuit. apparatus. 2. The charge pump device according to claim 1, further comprising pumping pulse generating means for generating pumping pulses having different frequencies according to an operation mode of the memory device. 3. The charge pump device according to claim 2, wherein the frequency of the pumping pulse is increased during the operation of the memory device and reduced during the standby time. 4. The charge pump device according to claim 1, wherein said memory device is a D-RAM device. 5. The charge pump device according to claim 2, wherein the memory device is a D-RAM device. 6. The charge pump device according to claim 3, wherein the memory device is a D-RAM device.