JPH02350A - Semiconductor device - Google Patents

Abstract

PURPOSE:To form a semiconductor device with high stability and high reliability by controlling the operating voltage and the operating current of a circuit in the semiconductor device, according to the change of manufacturing condition and the use condition. CONSTITUTION:The title semiconductor device is provided with a controlling circuit 3 having a signal generating means or a controlled internal power supply voltage means. The former generates a signal changing in accordance with the change of the manufacturing condition and the use condition. The circuit 3 generates a controlling signal or a controlled internal voltage according to the change of the manufacturing condition or the use condition, and controls the operation of a circuit 2, via a control line 5. Thereby, characteristics of the circuit 2 are kept in a constant relation according to the manufacturing condition and the use condition, so that a semiconductor device with high stability and high reliability can be formed.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to improving the performance of a semiconductor device, and particularly to a semiconductor device suitable for achieving high stability and high reliability of a highly integrated semiconductor device. [Conventional technology] With the remarkable progress in high integration of semiconductor devices in recent years, MO
S dynamic type methe memory (abbreviated as D RAM)
For example, 1M bit is the mass production period. As 4M bits reach the completion stage of their prototypes, the focus of research is shifting to 16M bits. In order to realize such a highly integrated semiconductor device, it is necessary to make the dimensions of the elements, wiring, etc. that make up the device extremely fine, such as 0.5 μm to 1 μm. It is extremely difficult to process and manufacture such minute elements or wiring with high precision, resulting in the problem of large manufacturing variations. M.O.
Taking 3DRAM as an example, the gate length and threshold voltage that govern the characteristics of a MOS transistor vary greatly due to variations in processing dimensions, impurity diffusion concentration, etc., and variations in power supply voltage9 and ambient temperature under actual usage conditions also occur. Considering, DR
The variation range of the overall AM access time is two to three times greater, and this manufacturing variation also has a large impact on reliability. That is, the breakdown voltage of the element, which causes dielectric breakdown of the element and characteristic fatigue (due to pot carriers, etc.), decreases due to miniaturization, and furthermore, the characteristics are largely controlled by variations in processing dimensions. Traditionally, as a means of stabilizing characteristics and improving reliability,
Japanese Patent Application No. 56-57143, No. 56-168698, etc. use voltage converting means provided in a semiconductor device chip.
A technique has been disclosed for operating microscopic elements within a chip by lowering the external power supply voltage. [Problems to be Solved by the Invention] However, the above-mentioned conventional technology does not sufficiently consider the influence of changes in manufacturing conditions or usage conditions on electrical characteristics and reliability characteristics, and does not provide high stability and reliability. It was difficult to realize this semiconductor device. Furthermore, since no consideration is given to the effects of variations in manufacturing conditions, there is a problem in that during mass production, the yield of non-defective products that meet desired characteristics is low, resulting in increased costs. Therefore, one object of the present invention is to realize a stable and highly reliable semiconductor device whose electrical characteristics and reliability characteristics do not change even if the manufacturing conditions and usage conditions change.

[Means to solve problems]

The above object is achieved by controlling the operating voltage and operating current of a circuit within a semiconductor device in accordance with variations in manufacturing conditions and usage conditions. [Function] Operating voltage of elements or circuits in a semiconductor device. The operating current is controlled according to electrical characteristics and reliability characteristics. As a result, a highly stable and highly reliable semiconductor device can be realized. [Embodiment] FIG. 1 is an embodiment showing the basic concept of the present invention. In the figure, 1 is a semiconductor chip, 2 is an original internal circuit of the semiconductor device, and 3 is a control circuit of the present invention, which generates a control signal or a controlled internal voltage according to fluctuations in manufacturing conditions and usage conditions, The operation of the circuit 2 is controlled via a control line 5. Although 5 is shown as one signal, a plurality of signals may be prepared depending on the circuit of the circuit 2. According to this embodiment, the characteristics of the circuit 2 are maintained in a certain relationship depending on the manufacturing conditions and usage conditions, so that a highly stable and highly reliable semiconductor device can be realized. FIG. 2 shows another embodiment of the present invention, which differs in that the operating characteristics of the circuit 2, such as operating speed and operating current, are detected via a detection line 6 and a control signal is generated accordingly. According to this embodiment, since the operating characteristics in 2 are directly detected and a control signal is generated, more precise control is possible than in Fig. 1, and a more stable and reliable semiconductor device is realized. can. Of course, a plurality of detection lines 6 may be provided as necessary. FIG. 3 shows another embodiment of the present invention, which differs from the embodiment shown in FIG. 2 in that a detection circuit 4 having characteristics similar to those of 2 is provided in order to detect the operating characteristics of 2. According to this embodiment, even if there is no suitable circuit section in the circuit 2 to detect the operating characteristics, the characteristics of the circuit 2 can be detected indirectly through the circuit 4, and thereby the characteristics of the circuit 2 can be detected indirectly. It can be controlled to maintain a certain relationship. Note that 4 is also controlled by 5 here, but this is
This is to change the characteristics of 4 in the same way as 2, and it may be possible to operate it independently of 5 depending on the purpose. FIG. 4 shows an embodiment which is an application of the embodiment shown in FIG. It is suitable for cases where the device is composed of minute elements. In other words, by setting the potential of the 5th element to a value lower than the withstand voltage of the elements constituting the internal circuit 2, the control circuit 3 can operate a highly integrated semiconductor device made of minute elements with stability and high reliability. I can do it. Furthermore, according to this embodiment, there is no need to lower the external voltage, so there is no burden on the user.
56 bits, 1M bits. In order to increase the degree of integration to 4M bits, it is necessary to miniaturize the elements, but in this case, it is not desirable to lower the external voltage to deal with the drop in withstand voltage, so this is not recommended in this case. The example is valid. Although a plurality of control lines are shown in FIG. 4, in some cases, the characteristics of the internal circuit may be stabilized by controlling only the voltage of the internal circuit 2 by the control circuit. The internal voltage is determined by compensating for fluctuations in the internal voltage relative to the external power supply Vcc, and then determining the internal voltage based on external conditions such as temperature. It can also be changed to compensate for changes in internal circuit characteristics due to variations in manufacturing conditions. In the embodiment shown in FIG. 4, it goes without saying that the control circuit to which the external voltage Vcc is directly applied is constructed using elements having a withstand voltage equal to or higher than Vcc. However, in some cases, in order to improve the degree of integration or to match the characteristics of the control circuit and the internal circuit, it may be necessary to construct a part of the control circuit using micro elements with low breakdown voltage. In that case, as shown in FIG. 5, a voltage conversion circuit 3A is provided inside the control circuit 3, and a voltage lower than Vcc is supplied through the output line 5I of the voltage conversion circuit 3A, so that the withstand voltage in the internal circuit 2 and the control circuit 3 is increased. low part 3
In this way, according to the embodiment shown in FIG. 5, the control circuit can be constructed using miniaturized elements, so that the degree of integration can be further improved. Further, since the control circuit 3B and the internal circuit 2 can be constructed of elements having the same characteristics, there is an advantage that the characteristic fluctuations of the internal circuit 2 can be precisely controlled based on the characteristic fluctuations of the circuits in the control circuit 3B. In addition, the 4th. In the embodiment shown in FIG. 5, some of the elements with a high breakdown voltage in the internal circuit may be operated with the external voltage Vcc if necessary.By the way, in the case of using minute elements with a low breakdown voltage in FIGS. 2 and 3, Of course, the structure can also be constructed in the same manner as in FIGS. 4 and 5. Furthermore, in the embodiments shown in FIGS. 1 to 5, one control circuit is provided in each chip, but
If necessary, the internal circuit 2 may be divided into several parts and separate control circuits may be provided for each, and in that case, the configurations of FIGS. 1 to 5 may be combined as necessary. Of course. When the characteristics of the internal circuit 2 are controlled by dividing it into several parts as described above, it becomes possible to control the characteristics to the optimum characteristics depending on the function of each individual circuit. FIG. 6 shows the case where the operating speed of the circuit is controlled to different constant values. In FIG. 6, a broken line Ctt indicates the operating speed of a conventional circuit without a control circuit, and the operating speed varies greatly depending on changes in manufacturing conditions and usage conditions. On the other hand, if multiple control circuits are provided,
A circuit that requires high-speed operation can be kept constant at high speed like Blz, and a circuit that requires low-speed operation can be kept constant at low speed like Alt. For example, in an output circuit or the like, when the output is charged and discharged at high speed, noise is generated in the power supply, which adversely affects the operation of the internal circuit or semiconductor devices placed nearby. In such a case, by controlling only the output circuit to a low speed, the operating speed can be kept constant without reducing the overall speed. In addition, here the manufacturing conditions,
Although we have shown an example in which the circuit operation is controlled to be constant due to fluctuations in the usage conditions, it may be possible to make the circuit operation have a desired dependence on desired factors as necessary.For example, if the circuit operation is controlled as the temperature increases, Control that increases the operating speed is also possible. In that case, the speed of the semiconductor device or the entire system including it can be kept constant by controlling the delay in the resistance of the wiring within the semiconductor device or between the semiconductor devices to cancel out the increase in resistance due to temperature. can be kept. According to the embodiments shown in FIGS. 1 to 6, the characteristics of the circuit do not vary depending on the manufacturing conditions, so the yield of non-defective products in mass production is improved. Furthermore, since the characteristics do not vary depending on usage conditions, the reliability of a system such as a computer constructed using the semiconductor device of this embodiment is improved. Furthermore, in some cases, it may be necessary to synchronize the operations of two circuits in circuit 3, but in such cases, if this embodiment is used, the timing margin can be set to the minimum because there is no change in circuit characteristics. be able to. Therefore, there is an advantage that the speed of the semiconductor device can be increased accordingly.For example, in a DRAM, it is necessary to synchronize the operation of the memory cell array and the peripheral circuit, and the present invention can also be applied to such cases. As a result, the timing margin can be minimized, making it possible to increase the speed. This also applies when it is necessary to synchronize the operations of two or more semiconductor devices, and by using the semiconductor device to which the present invention is applied, systems such as computers made up of a plurality of semiconductor devices can be improved. Operation speed can also be increased. In addition, in FIGS. 4 and 5, the positive power supply is V
Although we assumed a so-called TTL interface with cc, the same applies to ECL. Although the following explanation will focus on the TTL interface, the present invention is not limited thereto and can also be applied to the ECL interface. Below, specific examples of circuits will be shown. First, a method for controlling the characteristics of a drive circuit, which is a basic circuit of an integrated circuit, will be described. FIG. 7 shows one specific embodiment for controlling the characteristics of the drive circuit in the circuit 2. In FIG. The figure shows an example in which characteristics are controlled by changing the power supply voltage of the circuit. Here, P channel M
A CMOS inverter consisting of an OS transistor Tpz and an N-channel MOS transistor TN1 is used, but this circuit can also be used with other logic circuits such as NAND and NOR circuits, or with a circuit composed of bipolar transistors or a combination of bipolar and MOS transistors. It may be a constructed circuit or a circuit formed by arbitrarily combining a plurality of these circuits. According to this embodiment, by changing the voltage V CONT of 5, the characteristics of 2', that is, the entirety of 2 can be controlled, and a highly stable and reliable semiconductor device can be realized. VCO
The value of NT is determined depending on the circuit type and purpose of the circuit 2' to be controlled.For example, it is shown in FIG. 7(A). CMOS
In order to stabilize the operating speed of the inverter and increase its reliability, it is necessary to adjust the V
CONT, that is, the delay time td of the CMOS inverter can be determined by the main fluctuation factors: gate length Lg of the MOS transistor, L/threshold voltage Vt, gate oxide film thickness tox, channel conductance β0. The relationship between temperature T (absolute temperature) and load capacity Ct is as follows (1). In actual circuits, there may be some deviation from this relational expression due to various circumstances, but the tendency shown in equation 1 (1) is almost maintained in all CMO8 circuits. Therefore, VCONT may be changed in accordance with this formula to keep td constant. In other words, as a qualitative trend, each variation factor (however, β
0 is its reciprocal) becomes larger or higher, V
By increasing the value of CONT, it is possible to keep td almost constant, thereby making it possible to keep the operating speed constant even if manufacturing conditions or usage conditions change. In addition, in this example, since it also responds to temperature changes,
Performance can be kept constant even with temperature fluctuations or ambient temperature fluctuations caused by differences in the amount of heat generated by the chip depending on the operating state of the semiconductor device itself, such as standby and normal operation. In addition, in equation (1), the MOS of both P and N channels is
Although Lg, vd, and toxtβ0 are commonly defined for transistors, in reality, they often have different values. However, in both channels, only the polarity of voltage and current differs, and the relationship in equation (1) holds true as is, so here, they will be treated without distinction unless it is particularly necessary. As mentioned above, in some cases, the speed of the circuit may not be constant, but may have a desired dependence on a desired parameter.For example, as mentioned above, the speed of the circuit may be changed as the temperature increases. If you want to speed up (1
) From the formula, instead of (V CONT -V T ) ccT-"', it is sufficient to set (V CONT-V d) a:T-" so that n > 1, 5. Next, regarding the element breakdown voltage, the dielectric breakdown voltage is Lg, t
As ox becomes smaller, it decreases, so similarly, V C
0NT can be controlled as shown in the same figure (B), and it has occurred near the drain of a MOS transistor, which has been attracting attention in recent years. High-energy carriers are injected into the gate oxide film, raising the threshold voltage and deteriorating characteristics such as decreasing channel conductance. Since Lg and tox are small and the temperature T is also low, VCONT can be controlled as shown in FIG. This allows even if
Even if the hot carrier breakdown voltage is lowered due to manufacturing variations, VCONT will also be lowered, so problems such as characteristic deterioration will not occur. Even if the threshold voltage increases or the channel conductance decreases due to hot carrier phenomenon or other factors due to long-term operation, VCONT will be
Since it is controlled as in B), the characteristics can be kept constant. As mentioned earlier, the embodiment of FIG.
Various circuits can be used in addition to the S inverter. For example, an iCMOS inverter as shown in Figure 8 may be used. In this case, the output can be driven by a bipolar transistor, so higher-speed operation can be achieved. . Further, in FIG. 8, the collector of the bipolar transistor QNIS is connected to the external power supply Vcc. As a result, most of the output current is supplied from the external power supply Vcc, so the control circuit 3
The driving capacity can be reduced, and the design becomes easier. Note that if the withstand voltage of the bipolar transistor is low, increase the drive capacity of the control circuit 3 and connect the collector of QN8 to VCON.
9 as 2' in FIG. 6. A circuit as shown in FIG. 10 can also be used. FIG. 9 shows the example of FIG. 7 with T ri s and T s
0 which is an additional output buffer circuit consisting of 4
The operating speed and output voltage of this example are as shown in Figure 7.
Although it is controlled by NT, since the drive current of the output load capacitor CL is supplied from Vcc, the drive capacity of the control circuit 3 can be reduced as in the embodiment of FIG. 8, and the design becomes easy. Figure 10 shows an example in which T'sa is replaced with a bipolar transistor QNa.e Because QN8 has a large driving capacity, it is possible to drive the load at higher speed, and at the same time, VCON
The driving capacity of T can be further reduced. In the embodiments shown in FIGS. 8 to 10 as well, the circuit characteristics can be controlled by VCONT as in FIG. 7. FIG. 11 shows another specific embodiment for controlling the characteristics of the dynamic circuit. The figure shows only the element circuit 2' in FIG. 7, and a P-channel MoS transistor Tpz and an N-channel MOS transistor TNz are inserted between the CMOS inverter of T P I T Nx and the external power supply voltage Vcc and ground. By controlling the gate voltage, the operating current of the inverter is controlled, and ultimately the operating speed is controlled. That is, increasing the current increases the speed, and decreasing the current decreases the speed. The delay time td has a tendency similar to that shown in equation (1) for each variation factor. Therefore, as shown in the same figure (B), L g e
As Vie t axe 1 /βO, T g Cta increases, each current increases. In other words, VCONT for gate control of P-channel MO5T controls the gate of N-channel MO8T from a high value to a low value. By changing VCONT' from a low value to a high value, it becomes possible to keep td almost constant. According to this embodiment, the operating current of one circuit is directly supplied from the power supply voltage, and Vcost and VCONT' need only drive the gates of the MOS transistors. The driving capacity of the control circuit 3 can be reduced, and the design becomes extremely easy. Note that in this embodiment, both P and N channels M
Although a method of controlling using an OS transistor has been adopted, it is also possible to provide only one of them as necessary. In the embodiment shown in FIG. 11, the gate widths of the MOS transistors Tpt and TNz are set to TP2. If the on-resistance of TPI and TNI is made larger than Tpte TNz by making it larger than T'N2, 'rpt,
The current flowing through TNI is 'rp. It is determined by the on-resistance of T'Nz, making it easier to control. Although FIG. 11 shows an example of an inverter, this embodiment is not limited to this, but can also be applied to various logic circuits such as a NAND circuit and a NOR circuit. That is, in FIG. 11, DRIV having the function of a drive circuit may be replaced with a logic circuit. Figures 12 (A) and (B) show that the control method in Figure 11 is 0MO.
This is an example in which the present invention is applied to a BiCMO3 drive circuit, which has a higher driving capability than the BiCMO3 drive circuit. BiCMO as it is well known
3, the base current of the bipolar transistor is controlled by the MOS transistor, and the current is increased by the bipolar transistor to drive the load capacitance. Therefore, the speed of the circuit can be controlled by controlling the base current as shown in (A). In FIG. 12(A), when the input IN becomes low level, p
M OS Tpze n M OS TN& is on,
nMO8T pi a , T N z , T N
l turns on. As a result, the bipolar transistor QN
8 is turned on and QN4 is turned off. At this time, the base current flowing through QNδ can be controlled by TP1, which is applied to the gate of VCONT. Therefore, the charging speed of the output can be controlled by VCONT. On the other hand, when the input IN becomes a high level, the bipolar transistor QNa is turned off, QN4 is turned off, and the output starts discharging. At this time, the base current of QN4 is the output OUT
Since this can be controlled by V(!ONT'), the discharge rate of the output can be controlled by VC!ONT'. In this way, in this embodiment, the operating speed of the BiCMO3 circuit can be controlled. In addition, to control the speed of the BiCMO3 circuit, the DRIV part in FIG. 11 may be simply replaced with a BiCMO8 circuit as shown in FIG. 12(B). In this case, the current is as shown in FIG. 11(A). Since it is determined by the MOS transistor Tpzv TNz, it is possible to control with higher precision than when only the base current is controlled as shown in FIG. 12 (A).Also, compared to the circuit shown in FIG. Since the MOS transistor in the DRIV can be made smaller according to the capacity, there is an advantage that the input capacitance seen from the input IN is small.In other words, the load on the front stage is light, so the speed can be increased.As shown in Figure 11, the power supply and drive circuit The method of controlling the current by inserting a MOS transistor between them can be applied to other methods. Figure 13 is an example of application to a level conversion circuit to obtain an output amplitude higher than the input amplitude. Figure 14. The circuit operation in Fig. 13 will be explained using
The potential of becomes the potential of V^-V T 11 n 0 Then, when E becomes a low potential, p M OS Tpa turns on and F
The potential of becomes VH. As a result, p M OST Tpz is turned off, n M OST N t is turned on, and the output OU
T becomes Ov. Note that when F rises to high potential Vn, A
, C is V^, and since TNIS is off, current does not flow from F to C and the potential of F does not drop. On the other hand, when IN becomes low potential while E is high potential, TNa
turns on, and F also becomes the same low potential as IN. This result Tp
z is on, T N 1 is off, and the output OUT is at high potential V
It is charged to H. Note that in this circuit, as shown by the dotted line in Figure 9, if the period tcE from when IN becomes a high potential V^ until when E becomes a low potential is long, the high potential of F will remain at V^-vT for a while. , TP! There may be a period in which a through current flows through , T s 1 and OUT remains at an insufficiently low potential. Therefore, it is desirable to shorten the tcE time. To do this, it is sufficient to switch E to a low potential at the same time that IN becomes a high potential, thereby solving the above problem. As described above, according to the embodiment shown in FIG. 13, the amplitude r9V^ of the input IN can be converted into a high amplitude Vo. At this time, since the current can be controlled by the MOS transistors TPz and IN2, it is possible to operate at a desired constant speed. The embodiment shown in FIG. 13 is effective as a circuit for obtaining an output voltage higher than an input voltage, such as a word driver for a dynamic memory. FIG. 15 is another embodiment for controlling the speed of the drive circuit. In this example,
This is an example in which a non-inverter is configured so as to directly obtain an output from the current control MOS transistor in FIG. In Figure 15, when the input voltage becomes high level, p
MOS Tpx, Tpa off, n M OST N
1, TNa turns on. As a result, pMO8T
The gate of pz becomes VCONT, and n M OS IN
The gate of 2 is Ov. This turns Tpz on.
tz is turned off, and a current controlled to a desired value by VCONT flows through the output to charge the load. Conversely, when the input IN becomes low level, TP2 is turned off, Tnx is turned on, a discharge operation starts, and OUT becomes Ov. At this time, the gate voltage of IN2 is VcoNt', so the discharge speed can also be controlled by vcoNT.
Since two MOS transistors are not connected in series, it is suitable for high-speed operation. Furthermore, control is easier than in the case of FIG. 11, in which the influence of characteristic fluctuations of two transistors connected in series must be taken into consideration. The method of controlling the operating speed of the drive circuit has been described above, but in the circuits shown in FIGS. 7 to 12 and 15,
External voltage Vca is applied to a part of it. Therefore, in some cases, problems such as difficulty in compensating for fluctuations in Vcc may occur. In that case, as shown in FIG.
A is provided and its output voltage V! By keeping Vcc constant, the internal circuit can operate stably against fluctuations in Vcc. In this case, if the internal voltage Vx is set low,
It is possible to stably operate a miniaturized element with a low withstand voltage. FIG. 16 shows an embodiment in which a voltage conversion circuit is provided within the chip as described above. In Figure 16, the 5th construction is
Voltage V! is sent from the voltage conversion circuit 3A to the circuit 3B in the control circuit and the internal circuit 2! This is the power line for supplying. Moreover, ICL is a MOS transistor T p z in FIG.
, T N 2, each circuit DRIV in the internal circuit
According to the zero-wire configuration, which is a current control circuit that controls the current of V!, the constant voltage V! does not depend on the external voltage Vcc. This allows the miniaturized elements to operate stably and at a desired speed depending on the function of each circuit. FIG. 17 is an embodiment showing another means for controlling the operating speed of a CMOS inverter. Here, by controlling the T P 1 and T N 1 (7) substrate 5BPI, 5BNI (7) voltages, T P 1. It controls the threshold voltage of T Nx and, as a result, the operating characteristics of the inverter. This embodiment is suitable for compensating for characteristic changes due to threshold voltage fluctuations. Although FIG. 17 shows a CMOS inverter,
It can also be applied to other circuits using MOS transistors such as B1CMOS inverters. Furthermore, it is of course possible to combine this method of controlling the substrate voltage with the other control methods described above. Figures 7 to 17 mainly show inverters. A method for controlling the characteristics of a drive circuit such as a non-inverter NAND circuit has been described, but in integrated circuits, differential amplifiers that output an output according to voltage differences are also frequently used in integrated circuits. An example of this differential amplifier will be shown below. FIG. 18 shows another embodiment of the present invention, in which the control method of FIG. 11 is applied to control the operating speed of a differential amplifier composed of MOS transistors. In the same figure, INI, I
N2 is a differential input, OUT 1. Even in the 0 circuit where 0UT2 is a differential output, the operating speed changes with the same tendency as shown in FIGS. 7 and 11 with respect to fluctuations in control conditions and usage conditions. Therefore, V C0NT
t V OON? By controlling ' in the same manner as in FIG. 11(B), the operating current changes, and as a result, the operating speed can be controlled in accordance with manufacturing conditions and usage conditions. The output voltage of this differential amplifier is the operating current and the load MO
It is determined by the product of on-resistances of S transistors TPL#TpL'. Therefore, determine the operating current and the on-resistance of TNC and T
If VOONT and VCONT' are controlled so that the on-resistance ratio of PI, TPL' is constant, the product of the operating current and the on-resistances of TPL and TPL', that is, the output voltage, can be kept constant and the operating speed can be increased. can be controlled. FIG. 19 shows an example in which TN^ and TPI^' in FIG. 18 are replaced with NPN bipolar transistors QN^+QN8, and the same effect as in FIG. 18 can be obtained, and at the same time,
It has features such as a large amplification factor. In FIG. 20, the current control transistor TNC in FIG. 19 is replaced with an NPN bipolar transistor QNC and a resistor Rc, and the operating speed can be controlled in the same way as in FIGS. 18 and 19. Additionally, since the operating current is made more constant, it also has the advantage of increasing the amplification factor. In addition, if applying Vcc in FIGS. 18-20 causes a problem in terms of withstand voltage or characteristic fluctuations due to fluctuations in Vcc, the voltage conversion circuit 3A provided inside the chip as shown in FIG. All you have to do is apply voltage. The preferred embodiments for controlling the characteristics of the various element circuits constituting the five circuits 2 have been described above. Next, a specific example of the control circuit 3 will be described. FIG. 21 shows an example thereof. In the figure, Tpn is a P-channel MOS transistor, and CC is a constant current source that flows a constant current i.According to this embodiment, the manufacturing conditions such as the gate length, threshold voltage, and gate oxide film thickness of the TPR, or the temperature Even if the usage conditions such as the above change, the gate voltage necessary to cause a constant current to flow through the TPR is always outputted to the output 5. Therefore, the V C! of FIGS. 11 to 13, FIG. 15, FIG. It is suitable as an ONT generation circuit. When applied to these circuits, TPR and Figs.
Tpz in FIGS. 3 and 15, or TPL, TPL,' in FIGS. 18 to 20 are well-known current mirror circuit connections. Therefore, by appropriately selecting the transistor dimensions of T p z or T PL , T PL ' relative to those of TPR, the operating current of each circuit can be controlled to any constant value. FIG. 22 shows an embodiment in which the structure shown in FIG. 21 is constructed using N-channel MOS transistors, and FIGS.
It is most suitable as the VcoNt' generating circuit shown in FIGS. 18-19, and the same effect as that shown in FIG. 21 can be obtained. FIG. 23 is an embodiment that combines FIGS. 21 and 22. According to this embodiment, FIGS. 11 to 13, FIG. 15,
VCONT for FIGS. 18-19. VC! ONT' can be generated simultaneously, and since these voltages are generated based on the same constant current source, extremely stable voltages with high mutual matching can be obtained. FIG. 24 shows a P-channel MOS transistor TPR and an N-channel MOS transistor TNR connected in series to
According to this embodiment, which is an embodiment in which CONT occurred,
The influence of variations in manufacturing conditions and usage conditions for both P and N channel MOS transistors is reflected in the value of VCONT. Therefore, it is suitable as the VCQNT generation circuit of FIGS. 7 to 10. FIG. 25 shows an embodiment in which an amplification stage consisting of an amplification Ja7 and a feedback circuit 8 with a feedback factor β is added to the output of FIG.
ONT is V. VcaNt=□, and by appropriately setting β, any value can be obtained. Therefore, in addition to reflecting the influence of fluctuations in manufacturing conditions and usage conditions in Vo, it is also possible to have β share some or all of the roles by making β dependent on manufacturing conditions and usage conditions. FIG. 26 shows one specific example of the constant current value CC. As shown in the figure, constant current source CC1 has resistors R1 to Ra, NPN
It is composed of bipolar transistor QN + QNz. In this example, the voltage of the base Bpiz of Q N 1 is
If the current amplification factor of the bipolar transistor is sufficiently large and the emitter-base forward voltage is Vo8, then V
BI! (R2+R8)/Ra (7) Constant voltage. therefore. A constant current flows through R8 and R4 m VBI! Since it is less susceptible to fluctuations in manufacturing conditions, it can output a stable current. In this embodiment, since i flows from the outside toward the ground, it is suitable as a constant current source for a circuit as shown in FIG. FIG. 27 shows an embodiment in which a constant current source is constructed using a PNP bipolar transistor. 1! Pressure. The only difference is the polarity of the current from that in FIG. 26, and the operation is exactly the same.In this embodiment, i flows out from the power supply voltage Vcc, so FIGS. 22 and 24. It is suitable as a constant current source for a circuit like the one shown in FIG. Figure 28 shows an example in which a constant current source in which current flows from the power supply voltage as shown in Figure 27 is realized using an NPN bipolar transistor.
Although there is a problem that the raw Qwz operating current is added to the constant current, this effect can be ignored by making the Qsz current amplification factor sufficiently large. According to this embodiment, a constant current source in which current flows from Vcc can be easily manufactured and realized using a high-performance NPN bipolar transistor. Note that this embodiment can be used either in which the current flows in or out. FIG. 29 shows that by taking advantage of this feature, the constant current source described above is applied to the circuit of FIG. 23.
C0NT and V C0NT' can be output simultaneously. FIG. 30 shows a configuration in which current flows from Vcc by a current source CC into which current flows toward ground, such as constant current source CC1 in FIG. 26, and a current mirror circuit consisting of P-channel MOS transistors TPM and TPM. This is an example of realizing a constant current source. By making the dimensions of T'pH and TPM' the same, the current flowing through both can be made equal, and the current that has the same value as the output current i of the CC can be applied to the power supply voltage V.
It can be output externally from cc. By inputting this to the N-channel MOS transistor TNR as shown in FIG. 22, VCONT' can be obtained. In this embodiment, by appropriately selecting the dimension ratio of Tp and TPM', The output current can be arbitrarily determined for the value. In FIG. 31, the voltage generated by TPM and CC in FIG. 30 is used as the voltage of VCONT. This embodiment has the advantage that VcoNtw and VCONT' can be generated simultaneously, and the characteristics of both can be controlled with good consistency as in FIG. 23. FIG. 32 shows an embodiment in which a highly stable constant current source is realized using MOS transistors. In the same figure, TNex to TNB8 are N-channel MOS transistors, TM01 has a negative threshold voltage and Tsex has a positive threshold voltage. The threshold voltage of arprBs can be either positive or negative, RBt = Ra s is a resistance, and 7 is a difference It is a dynamic amplifier. Here, the values of Rez, RBx, and TM01. T
If the dimensions of saz are set equal, TM0
1° It operates so that the currents flowing through TM01 are equal to each other. Therefore, the gate voltage Vxs of TNsz is
The voltage has a value equal to the difference between the threshold voltages of TN1ll and Tne2. The value of this difference in threshold voltage is kept approximately constant regardless of manufacturing conditions or usage conditions. In the above circuit, since the drain and source currents of TN8δ are equal, the output current i can be expressed as VII. Therefore, a current output having the same characteristics as Vre is obtained, and its value can be arbitrarily controlled by RSS. By using this example as a constant current source in each example, such as the current source CC in FIG. 31, highly stable characteristic control is possible. According to this embodiment, it is possible to configure a circuit without using Pipo transistors, so it is suitable for an integrated circuit configured with MOS transistors. Figure 33 shows Figures 21 to 25 and Figures 30 to 31.
This embodiment is an application of a well-known bandgap generator circuit as a constant current source, and is particularly suitable for changes in temperature, power supply voltage, etc. In contrast, a highly stable current can be obtained. In the figure, QISI~Qas are bipolar transistors, Rat-RI! A is a resistor that can create a constant current i with desired temperature characteristics. Note that isz is the resistance Rs
Current flowing through z, 1112 is bipolar transistor Q
The collector current of ISx, isa, is the collector current of bipolar transistor Q+sa. Below, before explaining the output current i, we will first explain the internal voltage VIA of this circuit.
The value of and temperature dependence will be explained. In the following, for simplicity, it is assumed that the base current can be ignored compared to the collector current of the bipolar transistor.
The description will be made assuming that the collector current and emitter current are approximately equal. The voltage V t 1 is expressed by the following equation. V! z=Vaa(Qax)+Isz・Rsz+Vt
sp(Q21z)-Vag(Qaa)
-(4) VBE (Q81), VaE (
Q+sz) and VaE(Qss) are the base-emitter forward voltages of the bipolar transistors Qsxe QaxtQI5s, respectively. In equation (I+), current IB2 is expressed by the following equation. Isz=(Vag(Qss) VaI!(Qsa)
)/RII+-(5) Here, if the current density of bipolar transistor QB8 is set to n times that of bipolar transistor Qaa by appropriately selecting the emitter areas of bipolar transistors Qas and QIs4, then 1 kT I sz = □ -Q n n
・= (6) R5 q holds true. In equation (6), k is Boltzmann's constant, T is absolute temperature, and q is electron charge. (Give) - (6) Formula % Formula (7) holds true. Therefore bipolar transistor Qaz
If the design is made so that the emitter current densities of and Qss are equal, the third and fourth terms on the right side of Equation 7 cancel out, so the temperature dependence of the electric Vwz is a VIz a Vat! (QISI) R
sz k= +□・-Qnn
...(9)aT aT Rsa
It becomes q. As is well known, the base-emitter voltage of a bipolar transistor has a negative temperature dependence, so from equation (9), the resistance Rsx. RII4 ratio or bipolar transistor Qas
Since the value of VII obtained when changing the ratio n of the emitter current density of It is called. In the above circuit, the collector current and emitter current of Qgs are almost equal, so the output current i is t x l=□...(
10) It can be expressed as Rsa. Therefore, V r 1
A current output with the same characteristics as Rfi is obtained, and its value is Rfi
It can be arbitrarily controlled by g. If this embodiment is used as a constant current source for each of the embodiments already described, extremely highly stable control becomes possible. In particular, regarding temperature, the temperature coefficient of the constant power source can be set to O1 or any positive or negative value depending on the purpose, thereby making it possible to arbitrarily control the operating characteristics of the circuit. Further, the internal voltage VIz of this embodiment can also be used as a highly stable constant voltage source. At this time, if the constant current output i is not required, the output terminal may be connected to Vcc. For example, V t t can be used as V(!ONT' in FIG. 20, and in that case, the temperature characteristics of the differential amplifier can be controlled. Some specific examples have been described so far. The method of controlling circuit characteristics according to the present invention has been described. Although these embodiments can be easily realized, when the elements are constructed with fine elements to increase the degree of integration, the withstand voltage of the elements becomes low. , it may be difficult to apply the external voltage Vcc directly to the element. Also, if the external voltage fluctuates, it may be difficult to obtain the desired characteristics. As in the embodiments shown in Figures 4, 5, and 16, a stable voltage V! can be created inside the chip and used instead of Vcc. Vcc may be applied to areas where the internal voltage V! In this example, the CMOS inverter shown in FIG. 11 is controlled by the circuit shown in FIG. 21 and shown in FIG. 22. However, the application is not limited to this and can be applied to the various embodiments described so far. In Fig. 34, pMO8Tpz and TPR. If the size of TPz is set appropriately, the drive circuit DRIV
The charging current can be set to any value. Further, by appropriately setting the size of TNz with respect to TNR, the discharge current can be set to an arbitrary value. Here, the source voltages of PMO8TPR and Tpx and the power supply voltage of current source CCz are V! By keeping the value lower than the element breakdown voltage, it is possible to use a fine element with a low element breakdown voltage. Furthermore, in this embodiment, the output amplitude is also V! As a result, the voltage input to the next stage can be stably controlled, and the operation of the next stage can also be kept stable. In addition, V
CONT. The VCONT' generation circuits 31 and 32 can be shared by a plurality of circuits, and even in that case, by setting the magnitudes of Tpz and TNz for each circuit, each circuit can be controlled at a desired speed. Next, an embodiment of a voltage conversion circuit suitable for generating a voltage lower than Vcc inside a chip as shown in FIGS. 4, 5, 34, etc. will be described. FIG. 35 shows an example of the configuration of the voltage conversion circuit. Here, A is a voltage conversion circuit, F is a constant voltage generation circuit, and G is an amplifier. Constant voltage generation circuit F generates constant voltage V11 from external power supply voltage Vcc. The amplifier G increases the voltage V t x to obtain the voltage value V! required for the internal circuit 2 or a part of the control circuit 3A. is output to the control line 5I. Here the voltage is V! can have various characteristics depending on the constant voltage circuit F and the amplifier G. For example, if temperature dependence and external power supply voltage dependence are compensated, the third
Since the output amplitude of the circuit shown in FIG. 4 can be kept constant regardless of Vcc and temperature, more stable operation can be realized. According to this embodiment, the output voltage V t t of the constant voltage circuit can be amplified to a desired voltage value by the amplifier G. Therefore. The value of the voltage Vl can be set without being limited to the value of the output voltage V t 1 of the constant voltage circuit. The embodiment shown in FIG. 36 is expanded in FIG. 35.

[1]
The circuit G is constructed by a differential amplifier GD and a feedback circuit H. Here, the feedback circuit H is designed so that a voltage equal to the constant voltage vrt is outputted to the output I2 when the voltage Vr takes a desired value. According to this embodiment, the output voltage V! Since the fluctuation of is fed back through the feedback circuit H, the value of the output voltage v can be kept constant with high accuracy even when the current supplied from the control wA5 changes rapidly with time. FIG. 37 shows a specific configuration example of the constant voltage generating circuit F in the embodiments shown in FIGS. 35 and 36. In the current source shown in FIG. 33, bipolar transistor Q3B
This is a circuit in which the collector of is connected to Vcc. In the circuit of FIG. 37, the output voltage V y 1 and its temperature dependence are (
8), given by equation (9). As already mentioned, temperature dependence can be set by changing the resistance ratio or the current density ratio of the bipolar transistor. When used in circuit F, the output voltage V! of switching circuit A is adjusted according to the temperature characteristics of amplifier G or differential amplifier GD, and feedback circuit H in the subsequent stage. The temperature dependence of can be set to zero or a desired value. In addition, the 37th
In the illustrated embodiment, the external voltage Vcc is approximately twice the base-emitter forward voltage of the bipolar transistor;
When the voltage exceeds about 1.8V, the voltage Vxz becomes almost constant regardless of Vcc. Therefore, if this embodiment is used in FIGS. 35 and 36, it is possible to easily obtain an output voltage Vl that is free from temperature dependence and external voltage dependence. By the way, when forming the constant voltage circuit F and other circuits simultaneously on the same semiconductor substrate as in the embodiments described so far, the transistors used for both are MOS transistors.
By unifying the transistors to one type of transistor or bipolar transistor, the process steps can be simplified and manufacturing costs may be reduced. Therefore, it may be desirable to use a MOS transistor as the constant voltage circuit F instead of using a bipolar transistor as in the embodiment shown in FIG. In that case, for example, in FIG. 32, the MOS transistor TNII11
You may use V I 8 of the circuit whose drain is set to VCC, or alternatively,
id-3tate C1rcuit. 5C-15, Jun, '80 or BLAUSHILD, Journal of 5oli
d-3tate C1rcuit. 5C-13, Dec. '78, etc. may be used. FIG. 38 shows a specific embodiment of the differential amplifier circuit GD in FIG. 36. In FIG. 38, the output voltage Vtt of the constant voltage circuit F is applied to the terminal 11, and the output voltage Vtz of the feedback circuit is applied to the terminal 12.
In this embodiment, the terminal 11.degree. 2 is the base electrode of the bipolar transistor, so the gain is high and fluctuations in the voltage Vl can be kept small. In addition,
The P-channel MOS transistor in FIG. 6 may be replaced with a resistor as shown in FIG. 7. Since this resistor can be formed in the base diffusion layer of the bipolar transistor, it can be formed in the impurity layer for the collector of the bipolar transistor. Therefore, the layout area of the circuit can be reduced. Note that various circuits can be considered as the current sources for the differential amplifiers in FIGS. 38 and 39, but
It is also possible to realize it with one MOS transistor as shown in FIG. Here is the MOS transistor T! ett
The gate of Tl7L was connected to E1. Since Vll has a constant value with respect to Vcc as described above, by doing this, the current of the amplifier can be kept constant with respect to Vca. Furthermore, if it is necessary to stably control the characteristics of the amplifier, various controls can be performed using circuits such as those shown in FIGS. 18 to 20. FIG. 42 shows a specific embodiment of the feedback circuit H in FIG. 36. In Fig. 42, for the voltage v■ of control line 5,
is outputted to the output terminal Iz and inputted to the differential amplifier shown in FIG. 36. Therefore, if the resistors R81 and 1ljst are designed so that the output voltage of the constant voltage circuit F is Vlt, and the desired voltage to be output to the control line 5 is Vwo, then Vw=V
I OteV t t = V r z, and the control line 5
The I(7) voltage is stabilized at the desired voltage Vwo. here,
If the output voltage Vll of the constant voltage circuit F is designed to have zero temperature dependence as described above, the temperature dependence of the voltage Vgo can also be made almost zero. In addition, if necessary, V! Of course, it is possible to give o a desired temperature dependence. FIG. 43 shows another embodiment of the feedback circuit H in FIG. 36. In the embodiment shown in FIG. 43, the control line 5I is not directly connected to the resistor, but is connected to the base electrode of the bipolar transistor Qllll. Therefore, since the current is amplified by the bipolar transistor Qez, even higher speed operation than that shown in FIG. 42 can be realized. Also GD
The load current can also be reduced. In Figure 43, (11)
Equation and Equation (12) are respectively Rox+R92 R91+ Rox, so the resistances R)l and Rs are adjusted to satisfy Equation (14).
All you have to do is decide the value of z. However, in this case, as is clear from equation (14), Rex+Rox, so the voltage V! due to the second term of equation (15). The temperature dependence of o does not match the temperature dependence of voltage V t t. In this case, from equation (15), it is of course possible to use the following formula. Now, when using the above circuit, the power supply voltage (Vcc)
Even if Vcc becomes excessive, the output voltage can be kept at a constant value lower than Vcc, which has the advantage of preventing minute elements from being destroyed. However, on the other hand, it may not necessarily be suitable for carrying out an effective kneeing test. In normal integrated circuits, after the final manufacturing process, a voltage higher than that used in normal operation is intentionally applied to each transistor in the circuit to identify transistors that are inherently prone to failure due to defects in the gate oxide film, etc. We carry out Nisinghist and guarantee reliability. In order to improve the rate of finding defects using this nagging test, it is necessary to apply a slightly lower voltage to each element than would destroy a normal element. However, in an integrated circuit chip configured to supply a constant power supply voltage via a voltage conversion circuit inside the chip as described above, there is a possibility that a sufficient aging voltage may not be applied to the internal circuit. In that case, the fourth
As shown in Figure 4. The voltage Vr generated in the voltage conversion circuit is converted to the external power supply voltage V
The external power supply voltage Vcc may be designed to rise when cc becomes excessively large.
to Vcg is the internally generated voltage V! is kept at a constant value Vro, and when Vcc rises to Vca, it increases as Vcc rises. In this way, Vc is higher than Vcg.
When c increases, Vx also increases, so if you increase it above Vaa & Vc+ at the time of a knee strike, the circuit inside the chip will be affected by V! A voltage higher than o can be applied. For this purpose, an effective kneeing chest can be performed. FIG. 45 shows a specific example for realizing the voltage characteristics shown in FIG. 44. The constant voltage circuit F in FIG. 45 is the same as the embodiment shown in FIG. 37 in which a resistor R111 is inserted between the collector and the terminal of the bipolar transistor of the output stage J, and a differential amplifier GD and a feedback circuit H. and were connected in the same manner as in Fig. 36. Further, the collector of the bipolar transistor Qllll is connected to the base of the bipolar transistor Qxtz, and the bipolar transistor Qll! The emitter of I was connected to control line 5, and the collector was connected to Vcc. In this circuit, the external power supply voltage Vcc is the output voltage V
! After reaching the stable point VIO, vI is constant and equal to Vto until bipolar transistor Q112 is turned on, and after bipolar transistor Qxtz is turned on, the output voltage increases along with Vcc. The point VCE at which bipolar transistor Qzzz turns on is given by the following equation. VcE=Vto+Vag(Qxxz)+Rtzx
・i 11-(17) Here, the current izx is the resistance R111
The current flowing through satisfies the following equation. 1nz=Vrt/Rzz2...(18) Therefore. aT aT aT aT (21) On the other hand, the temperature dependence of VB when Vcc>Vca is as follows. Here, the circuit shown in FIG. 42 is used as the feedback circuit H, and vcp
When Vcc rises above, VB rises according to the following equation. Vw = Vcc - Rtxtoi 11- Vaa (
Qnzz) aT aT V cC) V CE, aT As described above, according to this embodiment, the external voltage Vcc is vc
When the voltage exceeds E, the voltage Vt increases with Vcc, so that the kneeing chest can be effectively performed. By the way, when the temperature dependence of VBo is designed to be zero, the temperature dependence of VcE is aT from equation (19).
It becomes aT. Normal vcI! The temperature dependence of VcI! is about -2 mV/''C, so the temperature dependence of VcI!
The temperature dependence of VB is very small, and the feedback circuit H
At the 43rd δT, a T R91+ R112a T is obtained from equation (14), so (
21), From formula (22)... (23-A) V ca > V cp... (23-B). Here, from the formula (/?), -1,25
mV/''C and approximately +1.25 mV/'C, so even if the circuit shown in Figure 43 is used as the feedback circuit H, V
The temperature dependence of CH and the temperature dependence of VB when VCC>VCE are very small.Furthermore, when using the circuit shown in Fig. 43, by setting the value of VCH to approximately twice Vto, the temperature dependence of VCH The temperature dependence of VB when Vcc>vcE can be made almost zero at the same time. That is, if VBE(Qxlz)4Vag(Qet), then from (23-C), when η=1, aT = (1+ η)Vto+Vas(Qtxz)-11・v
BE(Qei) - (23-C) holds true. Therefore, for example, VcI! = 6V, VIO = 4v, Vaa (Qzzz) = Vai (Qex)a
6 As mentioned above, the feedback circuit H has the 42nd
Both when using the circuit shown in the figure and when using the circuit shown in Fig. 43, the voltage characteristics shown in Fig. 44 can be achieved with almost no temperature fluctuation, and Vcc<VcF! It is possible to generate a voltage vK with almost no temperature dependence both in the normal operating region at 100 Ω and in the aging test region at Vcc>Vcp, and the internal circuit group can be stably operated. As described above, it is of course possible to make VIO temperature dependent as necessary. Furthermore, when it is necessary to set the temperature dependence of the neeingst region independently of Vwo, connect the collector of Qllll to Vcc as shown in Fig. 37 and set the desired temperature dependence with R111 for the bias of K. A current source may be provided separately from F. In FIG. 45, when V cc > V CH, the voltage V! Bipolar transistor Qzt to increase
z was used. However, with nMOS transistor Q112
Replace the gate of the above nMOS transistor with terminal K.
Of course, it is also possible to connect the drain to Vcc and the source to E. At this time, the terminal has n
Since it is connected to the gate of the MOS transistor, there is no need to supply current, and therefore a constant voltage generation circuit can be easily designed. According to the embodiments described above, it is possible to supply from the control line 5I a stable voltage that has a desired temperature dependence and is independent of the external power supply voltage within a desired range. Therefore, circuits within the same chip can operate stably. However, in cases where the current supplied from the control line 5 is particularly large, a buffer circuit for current amplification is added to the voltage conversion circuit A to prevent voltage fluctuations, and the output 5I' of the buffer circuit is used as the control line. Just use it. FIG. 46 shows an embodiment of the buffer circuit, in which Cxxl and Cxxx are capacitors for reducing potential fluctuations of the terminal Nu and the control line 5I'. In FIG. 46, the voltage V I ' of 5I' is Vw
'=Vcc-VuE(Qzzt) CVcc<VI+
VueCQxx Engineering)...(24) Or VM=V! +VaE (Qzzz) Va11! (Qz
zx) (Vcc>Vx+Vag(Qzzz)...(
25) It is expressed as Therefore, in this embodiment, Vcc≧Vr+Vag(Qzzt) −
In the region (26), V t ' is V! is almost equal to V! The temperature dependence of V x ' can also be controlled by using the above-mentioned embodiment in the generation circuit of can be supplied. That is, even when the current supplied to the circuit is large, the voltage V I ' can be kept stable. Figure 47 shows the bipolar transistor in Figure 46 as a MOS.
This is an example of replacing it with a transistor. In this example, Vt
Vcc≧VI+VTH(Q182) − with o(Mzaz) as the threshold voltage of the MOS transistor
In the region (27), Vl' becomes approximately equal to Vt. Since the threshold voltage of the MOS transistor can be easily controlled, in this embodiment, Vt'
The output voltage Vt' can be stabilized by making it equal to vI. In the two embodiments described above, the voltage V! The range of external voltages in which the output voltage V■' of the buffer circuit is equal to is,
As expressed by equations (26) and (27), it is limited by the forward voltage between the base and emitter of the bipolar transistor or the threshold voltage of the MoS transistor, for example. Even if it is designed so that the output voltage VI of the voltage conversion circuit is constant at 4■ when the external voltage Vcc is 4V or more,
The output voltage V r ' of the buffer shown in FIG. 46 does not become constant at 4V unless Vcc becomes approximately 4.8V or higher, which may narrow the operating margin of the internal circuit with respect to the external voltage Vcc. In such a case, a buffer circuit as shown in FIG. 48 may be used. In FIG. 48, 5I' is replaced by a P-channel MOS transistor M
The source of the MoS transistor is connected to the external power supply Vcc, and the gate G141 is controlled by the output voltage of the differential amplifier 0. Here, at the input terminal of the differential amplifier. The output voltage v■ of voltage conversion circuit A and the output voltage V of one buffer circuit, respectively. ' was entered. Here, the capacitor C141 is for suppressing fluctuations in the output voltage Vt'. According to the zero-capacitor configuration, the output voltage V I ' by the differential amplifier is changed to the voltage V! is kept equal to . Therefore, unlike the embodiments shown in FIGS. 46 and 47, the output voltage V I ' can be made equal to the voltage vX regardless of the external voltage Vcc.
Stable voltage can be obtained over a wide range of. FIG. 49 shows an example of a specific circuit configuration of FIG. 48. In FIG. 49, terminal P. Signals with opposite phases are applied to P. Although the circuit operation will be described below when the signal P is at a high level and P is at a low level, the same applies even when the signal P is at a low level and P is at a high level. Also, regarding the explanation of this example,
The explanation will be made assuming that Vcc is 5V and Vt is 4V, but the same applies to other voltage relationships. Also, for simplicity, the base-emitter voltage of a bipolar transistor is O, SV
It will be explained as follows. When Vt is 4V, the base potential V B 16 a of the bipolar transistor Qz6a is 1.6V. At this time, the potential Vr' of the terminal 5I'
is 4V, and the base potential VB1154 of bipolar transistor Qzδ is 1.6V.
When VBI δ decreases, VBI δ also decreases, and the collector current of the bipolar transistor Q1!14 decreases. On the other hand, bipolar transistor Qll! Since the collector current of 1 m increases, the current flowing through the resistor R161 increases. As a result, MOS transistor M141 (71 gate VGMi
41 decreases. Therefore, MOS transistor M x a
1 drain current increases to v! ' rises to 4v
to recover. Conversely, when V r ' increases, VCI
M141 rises, MoS transistor M141 is turned off, and vsum' falls and recovers to 4■. Note that here, since the diodes D15δ to Dδ6 are connected in series between the collector of the bipolar transistor Q188 and Vcc, the collector potential never drops below 2.6V.
On the other hand, base potential VB1. ．． is 1.6V, so the base potential of bipolar transistor Q168 is always lower than the collector potential.
8 is never saturated, bipolar transistor Q1
The base potential of 84 is V! '-2.4V, the collector potential is Vcc-2.4V, and normally Vl is lower than Vac, so Ql! 14 is never saturated.By the way, when the circuit connected to the control line 5I' is in the timing state,
The current flowing from 5I' is small and almost constant in many cases. In this case, even if you reduce the current flowing to the amplifier,
V! can be kept constant, and by reducing the current, power consumption can be kept low. To do this, the resistance value of resistor R1112 should be made larger than R161, and the MoS
The gate widths of transistors Mxsap Mzea and M1118 are respectively Mzse* M1g? , Mt is set larger than 15g, and when there is a circuit connected to 5I', the potentials of terminals P and P are each set to a low level. Just switch to a higher level. Note that the output Vr or Vr' of the voltage generating circuit described in FIGS. 35 to 49 can also be used as the VCONT in FIGS. 7 to 10 in addition to the power supply in FIG. 34. As described above, according to the embodiments shown in FIGS. 35 to 49, fluctuations in Vx and Vt' due to external voltage Vcc and temperature can be controlled, so that the circuit characteristics shown in FIGS.
cc, temperature can be kept constant. Therefore, this method is particularly effective when Vcc or temperature fluctuations are more important than fluctuations in manufacturing conditions. So far, we have described specific methods for controlling circuit operations, but of these, we have mainly focused on methods for detecting voltage values as shown in Figure 48 as means for detecting and controlling the characteristics of internal circuits. Takita. However, depending on the case, it is also possible to use a method of detecting and controlling the phase difference of the signals as described below. FIG. 50 shows a specific example of the configuration shown in FIG. In this embodiment, two predetermined pulses φl in the circuit 2
, φ2 and detects the phase time difference Δt. This is an example in which the operation of No. 2 is controlled in response to this and the operation speed is kept constant. In the figure, F/F is a set/reset type flip-flop, which outputs a signal φ■ with a pulse width equal to the time difference Δt between φ1 and φ2 @SV/! e 5Wtt. SWs is a switch, C1 and CH are capacitors, and VREF is a reference voltage. Below, the operation of this circuit is shown in the same diagram (B).
This will be explained with reference to. First, when φwork is input, φ! is output. As a result, SWt turns on, and the capacitance Ct changes to a constant current i
The voltage at the Cr terminal 31 gradually increases. Δ
When φ2 is input after the elapse of time, φ■ becomes a low potential and SWx is turned off. Therefore, the voltage VH of 31
L becomes a voltage proportional to Δt. This voltage is taken into the capacitor CH when φS is input and SWs is turned on. Here, if CI>Cs, the voltage at 32 becomes approximately equal to VHL. On the other hand, since the SWR of CI is turned on by φR, it is discharged to Ov and prepares for the next operation. The VHL taken into the CH is converted into a reference voltage VRE! by the amplifier 7. It is compared with F and outputs a voltage corresponding to the difference to 5, thereby controlling the operating characteristics of 2. The circuit No. 2 is composed of circuits as shown in FIGS. 7 to 20,
Its operating characteristics are changed by the voltage 5, and it is controlled so that the values of vFI□EF and Vot are ultimately equal. As a result, the circuit characteristics of No. 2 are kept constant. In this embodiment, since the operating characteristic described in 2 is directly detected and controlled, it is possible to respond even if the characteristic changes due to fluctuation factors other than those considered in advance, and the characteristic can be controlled with extremely high accuracy. VREF of 0 examples that can be achieved
Since e i governs control accuracy, it needs to be highly stable, but the embodiments shown in FIGS. 32 and 37 can be used as VREF. For i, Figures 26 to 33
Each of the illustrated embodiments can be used. Here, the operating characteristics of the circuit 2 are detected by the time difference between φ and φ2, but it is also possible to control the characteristics by detecting the amount of operating current, for example. FIG. 51 shows an example in which the embodiment in FIG. 50 is applied to the embodiment in FIG. The operating characteristics are detected using the outputs .phi.1 and .phi.2' in the same manner as shown in FIG. 50, and the operating characteristics of 2 are controlled. 7th as 2'
A ring oscillator may be formed using an inverter as shown in the figure, and various other circuit formats may be selected depending on the purpose. In this embodiment as well, the same effect as in FIG. 50 can be obtained. Note that among the embodiments described so far, when the base and collector currents of the bipolar transistor are supplied from the same power source as shown in FIG. 12, the base potential is There may be a possibility that the collector potential temporarily decreases and the bipolar transistor becomes saturated. In this case, as shown in Fig. 52, it is sufficient to provide two collector terminals, use C1 as the collector electrode of the bipolar transistor, and connect the MOS transistor that supplies the base current to 02. In this way, the bipolar transistor Since the potential of the second collector electrode is lower than the potential of the original collector CO, the potential of the base connected to this through the MOS transistor will never become higher than the potential of the collector CO. Therefore, the saturation of the bipolar transistor is reduced. can be prevented. This embodiment can be used not only in FIG. 12. FIG. 53 shows a specific embodiment in which each of the embodiments described above is applied to a DRAM. In the figure, MA is a memory cell array, and memory cell MC
are arranged two-dimensionally. PC is a data line precharge circuit, and SA is a sense amplifier that amplifies the minute signal output from the memory cell to the data line, and is composed of both P and N channel MOS transistors. AB is an address buffer circuit that converts address input Ain into an internal signal, X-Dec & Drive, Y-Dec & D
riv are an X decoder driver and a Y decoder driver, respectively. DP is a data line precharge voltage generation circuit during memory operation standby, SAD is a sense amplifier SA drive circuit, and WC is a data input signal Di.
A write control circuit writes n into the memory cell according to the instruction of the write signal WE.The peripheral circuit is a circuit that generates pulse signals necessary for the operation of each circuit in response to the external input CE.MA amplifies the read signal on the I10 line. This is a main amplifier that performs the following operations, and the embodiment shown in FIG. 19 is applied here. 3 outputs a signal corresponding to fluctuations in manufacturing conditions, usage conditions, etc. to 5, thereby controlling the operation of each circuit and stabilizing the characteristics. Each circuit is constructed of circuits as shown in FIGS. 7 to 20 so that it can be controlled by the output 5 of 3. The operation of this circuit is that when GE is input, memory operation is started, Ain is amplified by AB,
Supply a signal to Y-Dec. X depending on that signal
- One word line W by D ec & D riv
When is selected, the information charge stored in C8 in the memory cell is output to the data line. As a result, a small signal appears on the data line and is amplified by SA* Y -Dec
The data line signal selected by &Drive is Il.
o, Ilo. This signal is amplified by the MA and output to the outside as Dout. In the write operation, a signal is written into the memory cell via the WC through a path opposite to the above. With the above configuration, control for various purposes is possible. First, there is a control method that maintains the operating speed or reliability characteristics of the entire circuit constant, but as already explained in some embodiments, the control circuit 3 is used to Then, a signal matching each circuit to be controlled may be outputted to 5 to control each circuit. Next, a method of controlling each individual circuit according to its purpose may be considered. In particular, in DRAM, a part of the memory cell array is constructed using the smallest elements, so the element withstand voltage is lower than other parts, which tends to cause problems with lower reliability. , and other circuits may be controlled with the aim of stabilizing the operating speed. The method for keeping the operating speed constant may be according to some of the embodiments already described. There are several possible ways to control part of the memory cell array. First, there is a method of keeping the electric field of the insulating film thickness of the CS in the memory cell constant. In order to increase the information charge Qs and operate stably, the larger the CS, the better.In order to achieve a large Cs with a smaller area, the thickness of the insulating film as the dielectric material, toxs, should be set to the highest value in the semiconductor chip. This is because C8 is generally made thinner and has the lowest dielectric strength voltage within the chip. In order to keep this electric field E oxs constant and compensate for reliability, the output voltages of SAD, DP, VC, etc. are controlled according to the variations in the insulating film, and C
What is necessary is to control the voltage v8 written to a. At this time, the information charge amount Qs is expressed as follows. QS=C8IlvS oxs = s oxs 'Aoxa 0 Eoxg where εO
XS is the dielectric constant, and AOXS is the area of C3. Therefore, if Eoxs is kept constant, Qs is also kept constant, which improves reliability and stabilizes operation. Furthermore, as the temperature rises, the leakage current of the diffusion layer in the MC increases, so it is necessary to increase the minimum amount of information charge required for stable operation. Therefore, there is also a control method that increases Qs, that is, E oxs, to further improve reliability as the temperature increases. In this case, since g- of the MOS transistor decreases as the temperature rises, the peak value of the data line charging/discharging current can be controlled without increasing so much. Next, there is a control method that focuses on MOS transistors of memory cells. This is because this MOS transistor is the smallest in the chip, and its dielectric breakdown voltage and hot carrier breakdown voltage are often lower than those of other transistors. The various breakdown voltages of MOS transistors are determined by the short gate length and the gate insulating film thickness.
It decreases as x becomes thinner. Therefore, Lt is short,
As Tox becomes thinner, it is preferable to reduce the voltage applied to the word line, data line, etc. The applied voltage can be controlled in the same manner as described above. Furthermore, as mentioned earlier, as the temperature decreases, the hot carrier breakdown voltage also decreases. Therefore, when the temperature drops, the word voltage, data line voltage, etc. may be lowered. Thereby, stable and highly reliable characteristics can be obtained. It is also possible to combine the control method described here with the control method focusing on Cs described above. According to the embodiments described above, the operation of the DRAM can be controlled according to various purposes. Note that, as mentioned above, in order to promote higher integration in DRAM, it is necessary to use minute elements. Currently, the power supply voltage V
Although 5V is used as cc, it is expected that it will be difficult to directly apply 5V to miniaturized elements due to the drop in withstand voltage of the elements as the integration increases to 4M and 16M bits in the future. . However, lowering Vcc below 5V is undesirable because it puts a burden on the user in terms of compatibility with conventional DRAMs. Various types of control can be performed after generating a low voltage and protecting microscopic elements. FIG. 54 shows an embodiment of a control circuit including the power supply circuit as described above. In FIG. 54, 511' is an address buffer decoder. A control line for supplying a voltage Vw' lower than Vcc to peripheral circuits such as a clock driver, 5I2 a control line for supplying a voltage VCH higher than Vs' to a word driver, and 5I3H and 5I3L a sense amplifier SA. This is a control line for controlling the drive circuits SAD and SAD. Although omitted here, it goes without saying that the control circuit 3 in FIG. 54 includes other necessary control circuits. FIG. 54 shows a constant voltage generation circuit F for generating a stable reference voltage suitable for the knee-singing test. Bipolar transistor Qxxxt comparator GD, feedback circuit H1, and reference voltage V! Based on VCC, address buffers, decoders, clock drivers, etc.
' Comparator O and MOS transistor M141. Furthermore, there is a high voltage generation circuit HOP for operation to supply a voltage Vcu higher than V r ' to the word driver, etc., a high voltage generation circuit for standby period, and a drive for controlling the data line voltage Vo and data line charging current. It consists of circuits DRV and DRV'. According to this configuration, V
r' is V! Equal to. Also, since vcH and Vo are also determined based on V I ',
All internal voltages in DRAM are set to V! It can be controlled by Therefore, according to the above-mentioned embodiment, both the memory cell array and the peripheral circuits are not subject to characteristic changes due to temperature and Vcc fluctuations, and the DRAM has very stable operation.
can be realized. In addition, needless to say, kneeing chest can be effectively performed. Incidentally, when the embodiments shown in FIGS. 37 and 45 are used in the constant voltage circuit F shown in FIG. 54, it is also possible to reduce the power consumption in the following manner. That is, in the constant voltage circuit F shown in FIGS. 37 and 45, the output voltage V! z is the resistance ratio "t" as shown in equation (15).
'It's decided. Further, the aging voltage characteristic is also determined by the resistance ratio as shown in equation (20). Therefore, the characteristics do not change depending on the absolute value of the resistance and are less affected by manufacturing variations. Therefore, by uniformly multiplying the absolute value of the resistance by seven times (2>0), only the current can be set to a desired value while the resistance ratio remains unchanged. In some cases, reducing the current value may make it more susceptible to the effects of noise from other circuits on the same semiconductor substrate, but in that case, the semiconductor device including this reference voltage generation circuit F may be in an operating state. At certain times, the current flowing through the reference voltage generation circuit F may be increased to prevent voltage fluctuations caused by noise, and when in a standby state, the current may be reduced to reduce power consumption. FIGS. 55 and 56 show specific examples for this purpose. In FIG. 55, a PMO is connected between the positive power supply terminal of the reference voltage generation circuit F and the external power supply Vcc.
An S transistor is provided. In addition, in FIG. 56, n is connected between the ground terminal of the reference voltage generation circuit F and the ground power supply.
A MOS transistor is provided. According to these embodiments, the current value of the reference voltage generation circuit F can be easily controlled by changing the gate voltage of the pMOS transistor TM200 or the nMOS transistor 10. For example, in the embodiment of FIG. When the potential of the gate terminal 200 is lowered, the resistance value of the pMOS transistor M2O0 is lowered, and the current flowing through the reference voltage generation circuit F is increased. Furthermore, when the potential of the gate terminal 200 is increased, the resistance value of the pMOS transistor M2O0 increases, and the current flowing through the reference voltage generation circuit F decreases. Therefore, according to the embodiment of FIG. 55, when the semiconductor device including the reference voltage generating circuit F is in an operating state, the potential of the terminal 200 is lowered. By raising the potential of the terminal 200 when in standby mode, it is possible to prevent the voltage value from fluctuating due to noise during operation, and to reduce power consumption by reducing current during standby mode. In the embodiment shown in FIG. 56, the same effect can be obtained by increasing the potential of the terminal 210 when the semiconductor device is in operation and lowering the potential of the terminal 210 during standby. Since the embodiment shown in FIG. 56 uses an nMOS transistor, it is possible to use a transistor with a gate +lJ smaller than that of the pMOS transistor in the embodiment shown in FIG. 55, and the area occupied by the circuit can be reduced. Note that when a MOS transistor is inserted between the power supply and the reference voltage generation circuit F as shown in FIGS. 55 and 56, the net voltage applied to the reference voltage generation circuit due to the resistance between the source and drain of the MOS transistor decreases. However, the output voltage V of the circuit shown in FIG. 37 or 45
Since r 1 does not depend on the power supply voltage and maintains a substantially constant value as shown in equation (15), the current can be controlled without changing the voltage characteristics. Drive circuits for address buffers, decoders, clock drivers, etc. that operate using the control line 5I' in FIG. 54 as a power source are those in which Vcc is set to Vt' in the embodiments shown in FIGS. You can use
Also, if necessary, change V C0NT in Figures 7 and 8 to V
Note that in Figures 7 to 17, logic circuits such as NAND circuits used in decoders are omitted, but for example, in Figure 11, the DRIV part may be
This can be easily realized by replacing it with D. by the way,
It is possible to increase the speed by using a BiCMO8 circuit where the load capacity is large, but in that case, if the withstand voltage of the bipolar transistor QN8 is sufficient as shown in Figures 8 and 12, the collector can be left at Vcc. You can also use it as At that time, since the collector current is supplied from Vcc, most of the charging current flows from Vcc and vI'
Only the base current needs to be supplied.If the collector potential is within the range where the bipolar transistor is not saturated, it will not affect the circuit characteristics much, so doing this will keep the circuit characteristics stable.■! '' supply current can be reduced. This makes it possible to keep V r ' even more stable. Furthermore, the first stage of the address buffer to which external input signals are directly applied can be has a large through current and if the power supply for this part is set to V I ', the current at V t ' will increase and it may be difficult to keep V r ' stable. In that case, only the first stage should be connected to Vcc. Next, an embodiment for controlling charging and discharging of data lines will be described in FIG.
pMO8 and nMO8, depending on the read information of
Charging and discharging is performed using a well-known sense amplifier formed of S. At this time, the amount of charge Qc stored in the capacitor of the memory cell is the product of the data line voltage VDL and the capacitance CS of the capacitor. In DRAM, it is desirable to keep the Qc stable from the viewpoint of reliability. Therefore, if data line voltage VDL can be made independent of external power supply voltage Vcc and temperature, stable and reliable operation can be ensured regardless of external conditions. At the same time, power consumption can be reduced by setting VDL to a value lower than Vcc within a range that does not adversely affect operation. Furthermore, in the latest megabit DRAM, for example, 1024 pairs of data lines must be simultaneously charged at high speed. Since the total capacitance of this data line reaches 500 to 1000 pF, transient current becomes a problem, so reducing the transient current is also desirable. It is desirable to do this symmetrically. In this embodiment, the data line voltage VCL is controlled by the voltage conversion circuit described above to be equal to V r ', eliminating the dependence of VDL on external power supply voltage and temperature, and at the same time
The present embodiment will be described below, which is intended to lower the transient current and noise by lowering the power consumption and controlling the speed of charging and discharging the data line. The charging of the data line is the common line am of the flip-flop which is a sense amplifier formed including pMO5.
This embodiment is characterized in that the drive circuit is composed of a current mirror circuit and a comparator. The current mirror circuit is controlled by a type of inverter consisting of transistors Qx and Qz.When eQz is on and Ql is off, Qs, a constant current source (i/n), and an output drive transistor Qo
A current mirror circuit is formed between Qz and Ql, and when Qz is off and Ql is on, Qo is off. The current inlet of the current source in the mirror circuit is i/n, and the gate width of MO8T is w.
/n, and if the gate width of Qo is W, then the on-current of Qn is a constant current i. Even if W or the gate length or the threshold voltage of the transistor changes due to variations in the manufacturing process, if i/n is kept constant, the driving constant current of Qo will be approximately constant. Here the constant current source is i/n. The reason for setting w/n is to reduce current consumption and occupy a small area, and the larger n is, the better. The comparator outputs the output voltage V! of the voltage conversion circuit. ’ (for example, 4
V) and the output voltage vO. When Vt'>Vo, the output of the comparator becomes a high voltage, and the effective V
When t'<Vo, the voltage is low. The operation will be explained based on the above preparation. In a normal DRAM, the data pair lines are set to approximately half the value of VDL during the precharge period, which is a so-called half precharge method. Precharge to. In this state, when a pulse is applied to the selected word line, a minute differential read signal appears on each data pair line. This situation is shown at Dot D in Figure 58.
o Symmetrically shown representatively. After that, nMO8T and p
The sense amplifier is formed of MO3T, and the low voltage side is Ov.
The high voltage side is charged to V r '. Discharge is performed by MOS transistor Tsz. Here, acQ, only charging of which will be described below, is driven by applying an input pulse φ. When the input pulse φ turns on (high voltage is input), the output voltage of the control circuit AND becomes a high voltage, and the gate voltage Vo of Qo becomes the output voltage Vs of the constant current source. The QD drives the load with a constant current i. As a result, the load voltage Vo increases from VI'/2 at a constant speed, but when it exceeds Vt', the comparator is activated and the control circuit AND
The output of becomes a low voltage, Ql is turned on, Qx is turned off, and Q
n is turned off and Vo is clamped to approximately Vr', thereby charging one data line of each data pair from Vw'/2 to approximately Vr'. Regarding discharge, when φ is applied, nMO3TMa and TN
Since z forms a current mirror, the speed can be controlled in the same way as charging. According to the embodiment described above, the data line voltage Vat is set to V
! 'The data line voltage VDL. It is possible to eliminate the dependence on the external power supply voltage Vcc within a desired range by making the temperature dependence of the voltage zero. Furthermore, since the data line can be charged with a substantially constant current, the data line can be charged at high speed without increasing transient current. Further, by keeping io constant, even if there are fluctuations in the power supply voltage or manufacturing variations, the influence thereof can be minimized. Furthermore, since the data line voltage can be kept low, power consumption is also reduced. Furthermore, since data line charging and discharging speeds can be made the same, noise can be reduced. Next, an embodiment of a word line drive circuit will be described. D
In a RAM, the word line voltage is approximately 2V higher than the data line voltage. For example, set the data line voltage to 4
v, the word line voltage needs to be approximately 6v,
For example, the circuit shown in FIG. 59 can be used as a circuit for driving the word line with Vn boosted to a value higher than Vcc, which requires means for boosting the voltage of the word line to a Vcc value of 5 V or higher. The VH generation circuit will be described later. First, the operation of the circuit shown in FIG. 59 will be explained using the voltage waveform diagram shown in FIG. 60. When C becomes a high potential while E is at a high potential, the potential of F becomes V^-V T t through nMOS11.
The potential of All becomes 0, and then when E becomes a low potential, 12
(pMO8) is turned on and the potential of F becomes Vu. Kono result 13 (pMO5) is off. 14 (nMOS) is on, bipolar transistor 15
is off, 16 (nMOS) is on, and the output W is Ov
become. Note that when F rises to the high potential VH, the potentials of A and C are V^, so 11 is off, so current does not flow from F to C and the potential of F does not drop.On the other hand, E
When C becomes a low potential while is at a high potential, 11 turns on and F
also has the same low potential as C. As a result, 13 turns on and 14
16 is turned off, the node G becomes Vo, and the output is rapidly charged to a high potential. The high potential of this output is V o −V
It is ag. In this circuit, as shown by the 60th wavy line, the period from when C becomes a high potential V^ until when E becomes a low potential is tcI! If is long, the high potential of F is V^-V t
Since it remains at 1111 for a while, a through current flows at 13° and 14, and there may be a period in which D remains at an insufficiently low potential. Therefore, it is desirable to shorten the tcE time. To do this, it is sufficient to switch E to a low potential at the same time that C becomes a high potential, thereby solving the above problem. According to this circuit, since a bipolar transistor is used for the output, the word line can be charged to V HV - V BH at high speed. In addition, in FIG. G may be directly output without using the bipolar transistor 15. At this time, the output voltage rises to VH, so it is only necessary to generate VH equal to the desired word voltage. Therefore, the design of the power supply G is easier than when using a bipolar type. Furthermore, since it is composed of MOS transistors, it has the advantage that the manufacturing process is simple. In addition, the fifth
Even in the circuit shown in FIG. 9, it is possible to control the operating speed by inserting a MOS transistor between the circuit and the power supply as shown in FIG. 13. FIG. 61 shows an embodiment of a circuit for obtaining a high voltage equal to or higher than Vcc based on voltage V r ', and FIG. 62 shows its operating waveform. The operation of the circuit shown in FIG. 61 will be explained below using FIG. 62. The circuit shown in FIG. 61 is a circuit that boosts the VCH terminal in synchronization with the RAS signal in a DRAM. When the RAS signal goes low and the DRAM enters the operating state, as shown in FIG. 23, φtps goes low, φZP8 goes high, and φIs and φ18^ go high. As a result, Gl, which has been precharged to the same potential as Vcc. G2. G3. Of G4 (7), G1 and G2 are boosted by MO8 capacitors MCzxx and MCxxx, and as a result, G1 is boosted through the MOS transistor Mztst Mzz^.
From G4. A current flows through G3, and G3. The potential of G4 increases. At this time, since G2 is boosted above Vcc, G3. The potential of G4 is MOS) - transistor Mzxe
The zeroth order φis and φ1s^, which can be boosted without being limited by the threshold voltage of tMzz^, fall to a low level, and φZS and φ8s transition to a high level. As a result, G1. G2 transitions to low level and G3. G4 is boosted. At this time, when φas becomes high level, the potential of G2 becomes Ov because the MOS transistor MxzB is turned on, and the MOS transistor Mxz^ is surely turned off. Therefore, the potential of 02 does not rise due to a timing shift of φ2s or a coupling nozzle, etc. Therefore, from 03, current flows through the MOS transistor M2zc and 5I2 is boosted. At this time, since 6 diodes are connected in series between the gate of MOS transistor G4 and 5', the potential of G4 is VCL+
Clamped at 6VBE. As a result, the voltage of VH increases the threshold voltage of the MOS transistor Mxx to vT2! c and shite vX'+6VB+! -V
1, e.g. V! clamped to txzc. ' 4v
, VBE 0, 8 V, VT22C 0.8 V
Then, it becomes 8■. Six diodes were used here, but by changing this number, V! ' Since VH can be prevented from exceeding a certain voltage, for example, if a word driver is connected to VH, the word line voltage can be controlled to a desired value. When becomes high level, φ2g and φ8s are returned to low level, φIPS is set to high level, and φ2PS is set to low level. As a result, MO8
The potential of G5 is boosted by capacitor MC22o, and pMO
MOS transistor M through S transistor Mzzt
The gate voltages of zzsv M2xs, Mzx7°Mxxm are boosted above Vcc, and Gl, G2°G3 . The potential of G4 becomes Vca and returns to the initial state. Note that here, the MOS transistor Mzzs is for protecting Mxz+ by preventing high voltage from being applied to the drain of M224. Note that when diodes are used in series, VBH has temperature dependence, so VH has temperature dependence. To solve this problem, the amplitude of φ18 to φ8s may be set to Vt' instead of Vcc, and the clamp circuit may be omitted. At this time, in order to set the voltage of 5I2 to the desired value, a circuit such as the one shown in Fig. 63 may be used. A voltage of est is output. Furthermore, VRI! F is V
z' may be used or a bipolar transistor Qts
VaI of st! A voltage having temperature dependence that cancels the temperature dependence of may be applied. As explained above, according to this embodiment, a voltage higher than Vcc can be obtained at 5I2. In this embodiment, current is supplied from VH to boost Vo during DRAM operation in synchronization with the RAS signal. Low power consumption operation is possible without consuming power by boosting the voltage when it is not necessary. However, depending on the usage conditions of the DRAM, the periodic state may continue for a long time, and the potential of VH may drop due to some kind of leakage. In that case, it is sufficient to separately provide a circuit to compensate for the leakage during the timing. For this purpose, in the embodiments shown in Figs. 61 to 63, the capacitance and transistor size are reduced to reduce the current drive capability. A separate device may be provided and operated independently of the RAS, or a circuit as shown in FIG. 64 may be used. Below, the 64th
The operation of the circuit shown in the figure will be explained using FIG. 65. When φ is set to a low level, the MOS transistors TMzto, TM
zat. Gztot Gzat, Vn by TMz4a
When the 0th order φθ precharged near ca is raised to a high level, the outputs of the inverter Iz+x and the inverter 242 become high and low levels, respectively. Therefore, Gzao is V
When the voltage is boosted to more than cc, current flows to Gzao, and the potential of at4° rises, and the zero-order φθ is set to a low level, the outputs of inverters Is4t and Izaz are each at a low level. The potential of Vn rises by periodically rising and falling φθ such that it becomes high level and Gzaz is further boosted, and a current flows to VH. As VCH rises, the diode QDzao=QDz+
G2ae* Vozae chisel position is also VaH- by s
6VBE(7) maintains the relationship and increases. When the threshold voltage of MOS transistor TMzae is -VTZ46, when VH becomes Vl' -VT248+ 6 Vaa or more, Vozae becomes Vl' Vt5e and TMZ
48 is off. The potential of D247 is set to O by the MOS transistor TM Hough.
It becomes v. As a result, the output θ5 of the NAND circuit NA240
The voltage is fixed at a high level and the boost operation is stopped. After that, the potential of Vo decreases due to the current IH flowing out from the control line 5I2, and V ■'V T248 + 6 V B!
When the voltage is below, Mz number 6 is turned on again and the VH boosting operation starts. As described above, according to this circuit, the potential of VH can be maintained at Vl' - Vtzae + 6 VBH, which is higher than Vcc, while Vx' is 4 V and Vtzae is 0.
5V, VBIl! If O, SV, Vu is 8.3
v. As described above, according to this embodiment, by combining the charge pump circuit and the level shift circuit described above, the output voltage VH can be maintained at a constant voltage higher than Vcc. Incidentally, it goes without saying that the number of diodes QD zao" QD zas for clamping may be increased or decreased depending on the case. Also, depending on the case, the current flowing through QDx6-QDwas from vcH If is too large, QDz
aa is a bipolar transistor, collector is Vcc
By connecting the base to the output of QD244, 1/h
The above current can be reduced to rp. The number of diodes may be determined so that the difference between the voltages V)I and vX' becomes a desired value.
6M0 where M can be replaced with other elements such as resistors
When using an S transistor, by making the gate length L5 larger than the gate width W, a high resistance value can be easily obtained with a relatively small occupied area. Furthermore, here, a pn junction diode is assumed as the diode. A pn junction diode can be easily realized, for example, by connecting the base and collector of a bipolar transistor. Therefore, it can be formed at the same time as a bipolar transistor, and the manufacturing process can be simplified. At this time,
If the resistor is also realized using the base layer of a bipolar transistor, the process can be further simplified. Since the forward voltage VBB of a pn junction diode is normally about 0.8V, in the embodiment shown in FIG. 1, the voltages Vo and v! The difference between Vo and Vr' can only be taken in units of 0.8V, but in some cases the difference between Vo and Vr' can be taken as 0.8V.
There may be cases where it is necessary to set the value to a value other than n times (n=1.2...). In that case, if a Schottky diode with a forward voltage VF of about 0.4V is used, Vn= VT' Vtzas+ i VF, and 0
．． The value of VH can be set in units of 4v. Also, the 67th
Of course, it is also possible to use an nM OS diode as shown in the figure; in this case, nM OS T
Assuming the threshold voltage of M^ to Vτ^, Vo= Vr'
-VT24B+ i VTMA, so VTMA
The potential difference can be made variable in units of . Note that it is also possible to create an arbitrary potential difference by using a circuit as shown in FIG. 4 instead of the diode. 4th [i! ! At 1, the potential difference between the terminals 3A and 3B can be expressed as follows. Therefore, the potential difference can be continuously changed by changing the ratio of R^ and RB. Although various other modifications are possible, the embodiment shown in FIG.
In this embodiment, the level shift circuit shown in FIG. 1 is constructed using only an OS, the clamp diode is
MOS diode and bipolar transistor 1
．． In this example, where the resistances R are replaced with nMOS Mlll and Msz, respectively, the relationship between Vo and Vl' is as follows, where the threshold voltage of THIII is V6O13 and the threshold voltage of the MOS diode is Vto, VH = Vt' - Vrzas+ VTM51+
n VTll, and the potential difference can be set using the threshold voltage vT111 as a unit. In this embodiment, n M
The current flowing through the OS diodes MD51 to MD5i is n MOS The bias current I flowing through OS Mas
Since it is composed of only N, there is no need to make the current supply capacity of 5I2 larger than necessary.Furthermore, in this embodiment, there is no need to use bipolar transistors, and since it is composed of only MOS transistors, it is possible to create an LSI composed of only MOS transistors. It is suitable for application to. MOS transistor M31. MIss gate voltage, gate length,
The gate width may be determined so that the currents IR and IN have desired values. For example, set the value of IR to 10 for IL.
If it is set to double, the fluctuation in the drain current of the MOS transistor Mat can be suppressed to about 10%, and VL can be kept almost constant. In the above embodiment, if the temperature characteristics of the clamp circuit are a problem, the temperature dependence of the clamp can be compensated for by making the source voltage of the MOS transistor TMzae have temperature dependence. The present invention is effective when applied not only to DRAM but also to SRAM as described above. FIG. 70 shows an example of an SRAM memory cell configured using an nMOS transistor and a resistor. For example, if a voltage VC70 is supplied from the voltage conversion circuit of the present invention, the temperature dependence of the memory cell characteristics and the dependence on the external power supply voltage. Since this technology eliminates the error, it is possible to achieve extremely stable memory operation, such as improved resistance to soft errors. At this time, since the current supplied from VC70, that is, the holding current of the memory cell, is a very small and almost constant DC current, it becomes easy to keep the voltage VC70 constant and accurate. Furthermore, if the voltages of the data 1iDL and DL, that is, the write voltage or the voltage of the word line W are stably controlled, reliability can be further improved. For this purpose, the above voltage V! obtained by the present invention! If the write voltage is determined based on , temperature dependence and external voltage dependence can be eliminated, and reliability can be further improved. Stable and highly reliable operation can be realized by controlling the drive circuit and differential amplifier used in the peripheral circuits of the SRAM in the manner described above. Furthermore, the present invention is applicable to logic LSIs other than memories. Further, in FIG. 53, the control circuit detects the characteristics of the peripheral circuit at 6, but this detection can be performed at various locations depending on the purpose. For example, the time from when a word line is applied to when a sense amplifier minute signal is amplified is detected, and based on the results, the SA drive voltage and drive current are changed to control the operating characteristics of a part of the array. There are also various methods of control. In addition, although the main components have been explained using MOS transistors and bipolar transistors as examples, other G
The principles of the present invention can be applied as is to devices constructed using compound semiconductor elements such as a and s. In addition, although we have mainly focused on the element constants of MOS transistors as factors for variation in characteristics, it goes without saying that variations in current amplification factor, cutoff frequency, forward voltage, etc. of bipolar transistors can also be dealt with in the same way. Furthermore, although each embodiment has been described with the main objective being to keep various characteristics constant, if the present invention is used, variations due to manufacturing conditions such as gate length and threshold voltage, power supply voltage,
If fluctuations in usage conditions such as speed increase the semiconductor device to a higher speed, it may be controlled to make the semiconductor device even faster, or vice versa. If the speed changes so that the speed changes, the speed can be controlled to be even slower. Note that although the embodiments described so far have been mainly described with respect to the TTL interface, it is of course applicable to other cases such as ECL as well. [Effects of the Invention] As described above, according to the present invention, a stable and highly reliable semiconductor device can be realized even if there are variations in manufacturing conditions, usage conditions, etc. At the same time, since a high yield of good products can be maintained during mass production, the semiconductor device can be manufactured at a lower cost than conventional semiconductor devices.

[Brief explanation of the drawing]

Figures 1 to 6 are diagrams showing embodiments illustrating the basic concept of the present invention, Figures 7 to 52 are diagrams depicting specific embodiments of the invention, Figures 53 to 69, and Figures 70. The figure shows the invention
FIG. 3 is a diagram showing an example applied to M and SRAM. 1... Chip, 2... Internal circuit, 3... Control circuit, 5... Control line. (7'-long) 4-X Upper eye outside S system cape beads 6 axillary field curtain (A) (snake) (cho-tota 5) L (width side 1) 1st release drawing (A) X /Roen 1st drawing Takuzu 2■ Fig. χ Fig. 3 Otsu zu Ame 37 Fig. 51-253 5 no IILI Sumire 4θ 4th fig. Transmission ＋＋＋−”￥】
Figure 51 Figure 58 ≠, 17 Figure 58 ≠, 17 Diagram HθP1 - Date of creation j - Ko jh Denman E Complete circuit diagram #Sheep NET % Diagram NET Sage? Field pressure 1 t'r ;', ,'') L-=-+++ -1---J]647 ko] ~L Uq 1 kite g Tamehan

Claims (1)

[Claims] 1. In a semiconductor device consisting of a plurality of internal circuits constituted by a plurality of semiconductor elements, the semiconductor device has a signal generating means or a controlled device that changes according to fluctuations in manufacturing conditions or usage conditions. 1. A semiconductor device comprising a control circuit having an internal power supply voltage means, the operation of at least a part of the semiconductor element or circuit being controlled by the signal or voltage. 2. The semiconductor device according to claim 1, wherein the control circuit includes means for detecting a change in characteristics of the internal circuit, and performs control according to the change in characteristics. Device. 3. The semiconductor device according to claim 1 above is characterized in that a monitor circuit exhibiting a change in characteristics similar to that of the internal circuit is provided, and the control is performed by detecting a change in the characteristics of the monitor circuit. semiconductor devices. 4. In the semiconductor device according to claim 2, the control circuit detects changes in the timing of a plurality of signals generated by the internal circuit, and performs control according to the changes in the timing. A semiconductor device characterized by: 5. In the semiconductor device according to claim 3, the control circuit detects a change in the timing of a plurality of signals generated by the monitor circuit, and controls the internal circuit according to the change in timing. A semiconductor device characterized by performing the following. 6. The semiconductor device according to claim 1, wherein the control circuit controls the operating speed of a drive circuit included in the internal circuit. 7. A semiconductor device according to claim 6, wherein the control is performed by a current mirror circuit. 8. In the semiconductor device according to claim 6, the control is performed by an MO
A semiconductor device characterized in that the semiconductor device operates by controlling the gate voltage of an S transistor. 9. The semiconductor device according to claim 1, wherein the control circuit controls a differential amplifier included in the internal circuit. 10. The semiconductor device according to claim 9, wherein the differential amplifier is controlled so that the product of load resistance and current, that is, the output amplitude, is always constant. 11. In a semiconductor device consisting of a plurality of internal circuits constituted by a plurality of semiconductor elements, the semiconductor device has a signal generation means or a controlled internal power supply voltage means that changes according to fluctuations in manufacturing conditions or usage conditions. In a semiconductor device comprising a control circuit, the operation of at least a part of the semiconductor element or circuit is controlled by the signal or voltage, at least a part of the power supply voltage is supplied inside the semiconductor device. A semiconductor device, wherein fluctuations due to power supply voltage and temperature are compensated by a voltage conversion circuit provided in the semiconductor device, and at least a part of the internal circuit operates using the output voltage of the voltage conversion circuit as a power source. 12. In the semiconductor device according to claim 11, the internal circuit includes a drive circuit, and the control controls the gate of a MOS transistor inserted between the power supply whose fluctuations are compensated for and the drive circuit. A semiconductor device characterized by being controlled. 13. A voltage conversion circuit comprising a reference voltage generation circuit and a voltage amplifier that amplifies the output voltage of the reference voltage generation circuit;
A semiconductor device comprising means for compensating for variations in the output voltage of the voltage conversion circuit due to temperature and external power supply voltage, and the output voltage is also used as the power supply voltage of at least some of the circuits. 14. In the semiconductor device according to claim 13, the output voltage of the voltage conversion circuit is constant regardless of fluctuations in the external power supply voltage as long as the external power supply voltage is within a desired range;
1. A semiconductor device comprising means for changing the external voltage when the external voltage exceeds a desired range. 15. The semiconductor device according to claim 13, wherein the voltage conversion circuit includes a bipolar transistor. 16. Includes a circuit group constituting a dynamic memory and a control circuit that generates a voltage that serves as a reference for the operation of the circuit group,
A semiconductor device comprising means for compensating for variations in the reference voltage due to temperature and variations due to external power supply voltage. 17. The semiconductor device according to claim 16, wherein the dynamic memory controls the storage voltage of a memory cell that stores information using the reference voltage. 18. A semiconductor device according to claim 13, which includes a circuit group constituting a static memory and a control circuit that generates a reference voltage for the operation of the circuit group, the temperature of the reference voltage being What is claimed is: 1. A semiconductor device comprising: means for compensating for fluctuations due to changes caused by external power supply voltage; 19. A semiconductor device according to claim 14, further comprising means for compensating for variations in the desired range due to temperature. 20, a semiconductor chip, provided on the semiconductor chip,
A power supply terminal that receives a power supply voltage from the outside, an internal circuit provided on the semiconductor chip, and a power supply terminal provided on the semiconductor chip that converts the external power supply voltage received from the power supply terminal and converts the external power supply voltage to the internal circuit. It has a power supply circuit that supplies power, and a control circuit that is provided on a semiconductor chip and controls the power supply circuit, and the control circuit has an external power supply voltage detection means and/or a temperature detection means, In response to a signal from the external power supply voltage detection means and/or the temperature detection means, the power supply voltage supplied to the internal circuit is changed to maintain a constant operating speed of the internal circuit. semiconductor devices.