KR100254004B1 - Semiconductor device comprising internal voltage generating circuit - Google Patents

Abstract

PURPOSE: A semiconductor device with an internal power supply is provided to improve stability and reliability by protecting the electrical characteristics notwithstanding deviation or variation in the condition of the fabrication process condition and the operating condition. CONSTITUTION: A semiconductor device includes a semiconductor chip(1), an internal circuit(2) inherent to a semiconductor device, and a control circuit(3) for generating control signals or controlling internal voltages. The control signal or internal voltage is utilized for controlling operation of the internal circuit(2) by way of a control bus or line(5). The characteristics of the internal circuit(2) are maintained in predetermined constant relationship in conformance with the fabrication process condition and the operating condition, whereby a semiconductor device enjoying high stability and improved reliability is realized.

Description

Semiconductor device with internal voltage generator circuit {SEMICONDUCTOR DEVICE COMPRISING INTERNAL VOLTAGE GENERATING CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an internal voltage generation circuit having an internal supply power source of low power consumption.

Conventionally, in a semiconductor device having an internal voltage generation circuit in which an external power supply voltage is input to generate an internal voltage, the differential amplification means in the internal voltage generation circuit always operates at a constant power consumption when comparing the internal voltage and the reference voltage.

In general, when an internal circuit of a semiconductor device responds to an input signal, an internal voltage fluctuates due to a load fluctuation (operation current fluctuation) of the internal circuit, so that an internal voltage is supplied to supply the internal voltage to the internal circuit. It is necessary to reduce the output impedance of the circuit. However, it has been clarified by the inventor that the output impedance of the internal voltage generating circuit supplying the internal voltage to the internal circuit may be increased in the non-operating state in which the internal circuit of the semiconductor device does not respond to the input signal.

In order to reduce the output impedance of the internal voltage generation circuit, the operating current of the differential amplification means in the internal voltage generation circuit may be increased. Increasing the operating current of the differential amplification means lowers the output impedance and reduces variations in the internal voltage irrespective of load variations (operating current variations) of the internal circuits.

On the other hand, in order to reduce the power consumption of the semiconductor device, it is necessary to reduce the power consumption of the internal voltage generation circuit in the non-operating state in which the internal circuit does not respond to the input signal. Therefore, when the internal circuit is in an inoperative state, the operating current of the differential amplifying means in the internal voltage generating circuit may be reduced.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having an internal voltage generating circuit which is stable and highly reliable even in the case of fluctuations in manufacturing conditions or usage conditions, and which can maintain high yield of good products during mass production.

1 to 6 is a view showing the basic concept of the present invention,

7 to 52 show specific embodiments of the present invention;

53 to 70 show an embodiment in which the present invention is applied to a DRAM and an SRAM.

Thus, the present invention will be described with reference to FIGS. 48 and 49, which are representative embodiments of the present invention. The reference voltage generation circuit for generating the reference voltage 5I, the internal voltage different from the external power supply voltage by receiving an external power supply voltage, A semiconductor device comprising an internal voltage generation circuit for generating 5I ') based on the reference voltage and an internal circuit supplied with the internal voltage, wherein the internal voltage generation circuit includes a first input terminal and a second input terminal. Differential amplification means (Q ₁₅₄ , Q ₁₅₃ , T _M151 , R ₁₅₁ , T _M154 and Q ₁₅₄ , Q ₁₅₃ , T _M152 , R ₁₅₂ , T _M157 ) for outputting a voltage according to the difference of the voltage input to each It has an internal voltage output means (T _M141 ) for receiving the output of the amplifying means and outputs the internal voltage, wherein the reference voltage is supplied to the first input terminal of the differential amplifier means, the second input terminal is the internal Voltage is fed back, Group differential amplifier means has a his operating current larger first mode (T _M151, T _M154 is turned on) and the second mode (the T _M152, T _M157 on) a small operating current than the first mode, the control The signal P is set to one of the first mode and the second mode.

In this way, when the output current of the internal voltage generation circuit is small, the current consumed by the differential amplification means is reduced, and the power consumption can be reduced by having two modes when the output current is large and small.

When the p-channel MOS transistor is used as the internal voltage output means and the internal voltage is output from the drain of the p-channel MOS transistor and fed back to the differential amplification means, the threshold voltage for the case of using the n-channel MOS transistor is used. The voltage drop can be prevented and the output impedance of the first output circuit made of the p-channel MOS transistor can be reduced.

In addition, as shown in FIG. 44, in order to output a voltage larger than the first voltage when the external power supply voltage is greater than or equal to the second voltage V _CE , as shown in FIG. When the second output circuit Q ₁₁₂ outputting the voltage according to the external power supply voltage when the voltage is higher than the predetermined voltage V _CE , the aging test can be executed simply by increasing the external power supply voltage. The aging test can be executed using only one external power supply terminal without providing the input terminal of the chip.

In the case where the internal circuit includes a memory cell composed of a transistor and a capacitor, the internal voltage is stabilized when the charge stored in the capacitor is multiplied by the capacitance of the capacitor and the internal voltage. The charges accumulated in the capacitor can be kept stable, thereby improving the reliability. When the voltage applied to the word line connected to the gate of the transistor is based on the internal voltage, the read and write of the memory cell can be performed stably and the reliability can be improved.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

1 is an embodiment showing the basic concept of the present invention. In the same drawing, reference numeral 1 denotes a semiconductor chip, reference numeral 2 denotes an original internal circuit of a semiconductor device, and reference numeral 3 denotes a control circuit of the present invention, and a control signal or a controlled internal voltage according to a change in manufacturing conditions or usage conditions. Is generated to control the operation of the circuit 2 via the control line 5.

Although the control line 5 is shown as one signal, several may be provided according to the circuit of the circuit 2. As shown in FIG.

According to the present embodiment, since the characteristics of the circuit 2 are maintained in a certain relation depending on the manufacturing conditions or usage conditions, it is possible to realize a highly stable and highly reliable semiconductor device.

2 is another embodiment of the present invention, in which the operating characteristics of the circuit 2, for example, operating speed, operating current, and the like are detected via the detection line 6, and control signals are generated accordingly.

According to this embodiment, since the operating signal of the circuit 2 is directly detected and a control signal is generated, more precise control is possible than in FIG. 1, and a highly reliable and highly reliable semiconductor device can be realized. Here, of course, the detection line 6 may provide several lines as needed.

3 is another embodiment of the present invention, in which a detection circuit 4 having similar characteristics to that of the circuit 2 is provided in order to detect operating characteristics of the circuit 2, which is different from the embodiment of FIG.

According to the present embodiment, even when there is no suitable circuit section for detecting operating characteristics in the circuit 2, the characteristics of the circuit 2 can be detected indirectly via the circuit 4, whereby the circuit 2 Can be controlled to maintain a certain relationship.

In addition, although the circuit 4 is also controlled by the signal 5 here, this is for changing the characteristic of the circuit 4 similarly to the circuit 2, and depending on the objective, it is also possible to operate independently of the signal 5, Is considered.

4 is an embodiment applying the embodiment of FIG.

In this embodiment, the control circuit 3 supplies the power supply voltage of the internal circuit 2 via the power supply line 5I. This embodiment is suitable for the case where the internal circuit 2 is composed of fine elements, for example. That is, when the potential of 5I is set to a value lower than the breakdown voltage of the elements constituting the internal circuit 2, the control circuit 3 makes the highly integrated semiconductor device made of the fine elements stable and high in reliability. Can be operated in a state.

In addition, according to the present embodiment, since the external voltage does not need to be lowered, there is no burden on the user. For example, in DRAM or the like, it is necessary to miniaturize the device because the integration density is increased to 256K bits, 1M bits, and 4M bits, but in this case, it is necessary to reduce the external voltage in response to a decrease in the breakdown voltage in terms of compatibility with conventional products. This embodiment is valid because it is not preferable. In addition, although several control lines are shown in FIG. 4, in some cases, the internal circuit characteristics may be stabilized by controlling only the voltage of the internal circuit 2 by the control circuit. The internal voltage may be changed to compensate for the fluctuation of the internal voltage with respect to the external power source Vcc, and then compensate for the characteristic change of the internal circuit due to the fluctuations in the external conditions such as temperature and manufacturing conditions. In addition, in the embodiment of Fig. 4, the control circuit to which the external voltage Vcc is directly applied is, of course, configured using an element having a breakdown voltage of Vcc or more. However, in some cases, in order to improve the degree of integration or to match the characteristics of the control circuit and the internal circuit, it may be necessary to configure a part of the control circuit as a micro element having a low breakdown voltage. In this case, as shown in FIG. 5, a voltage conversion circuit 3A is provided inside the control circuit 3 to supply a voltage lower than Vcc through the output line 5I, and the internal circuit 2 and the control. It is good to control the part 3B with low internal voltage in the circuit 3. As shown in FIG.

As described above, according to the embodiment of Fig. 5, since the control circuit can also be configured to be miniaturized, the degree of integration is further improved. In addition, since the control circuit 3B and the internal circuit 2 can be constituted by elements having the same characteristics, the characteristic variation of the internal circuit 2 can be precisely controlled in accordance with the characteristic variation of the circuit in the control circuit 3B. There is such an advantage. In addition, in the embodiment of Figs. 4 and 5, some of the elements with high internal voltage in the internal circuit may be operated at the external voltage Vcc as necessary. By the way, in the case of using the micro device having a low breakdown voltage in Figs. 2 and 3, of course, it can be configured similarly to Figs. In addition, in the embodiment of Figs. 1 to 5, an example in which control circuits are provided one by one in the chip has been described. However, if necessary, the internal circuits 2 may be divided into several to provide respective control circuits. In this case, it is a matter of course that each configuration of FIGS. 1 to 5 may be combined as necessary. As described above, when the internal circuit 2 is divided into several parts and its characteristics are controlled, This makes it possible to control the optimum characteristics.

6 illustrates a case where the operation speed of the circuit is controlled to another constant value. In Fig. 6, the dotted line C ₁₁ shows the operation speed of the conventional circuit without the control circuit, and the operation speed is greatly changed in accordance with the change in the manufacturing conditions and the use conditions. If On the other hand, provided with multiple control circuits, circuits which require high-speed operation is kept constant at a high speed, such as B _11, circuits that require a low-speed operation can be kept constant at a low speed, such as A ₁₁ Do. For example, in the output circuit or the like, when the output charging and discharging is performed at high speed, noise occurs in the power supply, which adversely affects the operation of the internal circuit or the semiconductor device disposed in the vicinity. In such a case, if only the output circuit is controlled at a low speed, the operation speed can be made constant without lowering the overall speed.

In addition, although the example of controlling so that a circuit operation | movement becomes constant by the fluctuation | variation of a manufacturing condition and a use condition was demonstrated here, you may have desired dependence on a desired factor as needed. For example, it is also possible to control the operation speed of the circuit to become high as the temperature rises. In this case, the speed of the semiconductor device or the entire system including the same can be kept constant by controlling to cancel the increase in the resistance of the wiring in the semiconductor device or the resistance of the wiring between the semiconductor devices.

According to the embodiment of FIGS. 1-6, since the characteristic of a circuit does not change with manufacture conditions, the yield of the goods at the time of mass production improves. In addition, since the characteristics do not vary depending on the use conditions, the reliability of a system such as a computer constructed using the semiconductor device of the present embodiment is also improved. In some cases, the two circuits in the circuit 3 may need to be synchronized with each other. However, in this case, the timing margin is minimized because the circuit characteristics do not change when the present embodiment is used. Can be set. Therefore, there is also an advantage that the speed of the semiconductor device can be increased by that amount. For example, in the DRAM, it is necessary to synchronize the operation of the memory cell array and the peripheral circuit, but even in such a case, the timing margin can be minimized by the application of the present invention, so that the speed can be increased. Similarly, even when the operation is to be synchronized between two or more semiconductor devices, the operation speed of a system such as a computer composed of several semiconductor devices can also be increased by using the semiconductor device to which the present invention is applied. have.

In addition, in FIG. 4 and FIG. 5, the so-called TTL interface which assumed the electrostatic source as Vcc was assumed, but also in ECL. Next, a description will be given mainly of the TTL interface, but the present invention is not limited to this, but can be applied to the ECL interface.

Next, an embodiment of a specific circuit will be described. First, a description will be given of a method for controlling the characteristics of a driving circuit which is a basic circuit of an integrated circuit.

7 is one of specific embodiments for controlling the characteristics of the driving circuit in the circuit 2. In the same drawing, an example of controlling characteristics by changing a power supply voltage of a circuit is described. Here, a CMOS inverter consisting of a p-channel MOS transistor T _P1 and an n-channel MOS transistor T _N1 is used as the element circuit 2 'constituting (2). However, this circuit includes other logic circuits such as NAND and NOR circuits, and more. Furthermore, the circuit which consists of a bipolar transistor, the circuit which consists of a combination of a bipolar, and a MOS transistor, and the circuit which arbitrarily combined each of these circuits may be sufficient.

According to the present embodiment, by changing the voltage V _CONT of the signal 5, the characteristics of the circuit 2 ', i.e., the entirety of the circuit 2 can be controlled, whereby a highly reliable and highly reliable semiconductor device can be realized. The value of V _CONT is determined according to the circuit type and purpose of the circuit 2 'to be controlled. For example, as shown in FIG. 7A. In order to increase the reliability by keeping the operation speed of the CMOS inverter constant, V _CONT may be changed as shown in FIG. 7B for various variation factors. That is, the delay time td of the CMOS inverter is determined by the gate length Lg, the threshold voltage V _T , the gate oxide thickness t _OX , the channel conductance β ₀ , the temperature T (absolute temperature), and the load capacity C _L of the MOS transistor, which are the main variables. about

Is in a relationship. In actual circuits, some of these circumstances may deviate somewhat from this relational expression, but the trend indicated by the equation (1) is almost maintained throughout the CMOS circuit. Therefore, V _CONT may be changed to keep td constant by this equation. That is, as a qualitative tendency, as shown in FIG. 7B, when each variation factor (where β ₀ is the inverse thereof) becomes large or high and the value of V _CONT is made high, td can be kept substantially constant. As a result, the operating speed can be kept constant even if the manufacturing conditions or the use conditions change. In addition, in the present embodiment, since the temperature response is also changed, the performance is kept constant against temperature fluctuations or ambient temperature fluctuations caused by the amount of heat generated by the chip depending on the operation state of the semiconductor device itself during standby and normal operation. There is a number.

In Equation 1, Lg, V _T , t _OX , and β ₀ are defined in common in the MOS transistors of both p / n channels, but in practice, they are often different values. However, in both channels, only the polarities of voltage and current are different, and the relationship of Equation 1 holds as it is.

In some cases, as described above, it is possible to have a desired dependency on a desired parameter without making the speed of the circuit constant. For example, if you want the circuit according to the speed of the temperature increase as described above at a high speed, the (V _CONT -V _T) without αT ^-1.5 in the formula _{1 (V CONT -V T) αT} -n It is good to set it as n> 1.5.

Next, in the breakdown voltage of the element, the breakdown breakdown voltage decreases when Lg and t _OX decrease, so that V _CONT may be controlled as in FIG. 7B. In addition, the upper limit of the operating voltage is specified due to a phenomenon in which high-energy carriers generated near the drain of the MOS transistor, which are recently attracting attention, are injected into the gate oxide film, thereby causing a decrease in characteristics such as a rise in threshold voltage and a decrease in channel conductance. Since the breakdown voltage (hereinafter referred to as the hot carrier breakdown voltage) also decreases as Lg and t _OX become smaller and the temperature T becomes lower, V _CONT may also be controlled as shown in FIG. 7B. As a result, even if the hot carrier internal pressure is lowered due to a manufacturing deviation, V _{CONT is} also lowered, so that there is no problem such as deterioration in characteristics. In addition, even if the threshold voltage increases or the channel conductance decreases due to a long period of operation other than the hot carrier phenomenon, V _CONT is controlled as shown in Fig. 7B, so that the characteristics can be kept constant.

As described above, the embodiment of FIG. 7 is a circuit 2 ', and various circuits can be used without being limited to the CMOS inverter. For example, a Bi-CMOS inverter as shown in FIG. 8 may be used. In this case, since the output can be driven by a bipolar transistor, higher speed operation can be realized. 8, the collector of the bipolar transistor Q _N3 was connected to the external power supply Vcc. As a result, most of the output current is supplied from the external power supply Vcc, so that the driving capability of the control circuit 3 can be reduced, thereby facilitating the design. When the withstand voltage of the bipolar transistor is low, the driving capability of the control circuit 3 may be increased to set the collector of Q _N3 as V _CONT . As the circuit 2 'of FIG. 6, a circuit as shown in FIGS. 9 and 10 may be used.

FIG. 9 adds an output buffer circuit consisting of T _N3 and T _N4 to the embodiment of FIG. 7. The operating speed and output voltage of this embodiment are controlled by V _CONT as in FIG. 7, but the driving current of the output load capacitance C _L is supplied from Vcc, so that the driving capability of the control circuit 3 is reduced as in the embodiment of FIG. 8. The design becomes easy.

10 shows an embodiment in which T _N3 is replaced with a bipolar transistor Q _N3 . Since the driving capacity of Q _N3 is large, the load can be driven at a higher speed and the driving capacity of V _CONT can be further reduced.

In the embodiments of FIGS. 8 to 10, the circuit characteristics can be controlled by V _CONT as in FIG. 7.

11 is another specific embodiment of controlling the characteristics of the driving circuit. Fig. 11 shows only a part of the element circuit 2 'in Fig. 7, p-channel MOS transistors T _P2 and n-channel MOS transistors T between the CMOS inverters of T _P1 and T _N1 and the external power supply voltage Vcc and ground. By inserting _N2 and controlling its gate voltage, the operating current of the inverter is controlled, and finally the operating speed is controlled. In other words, if the current is increased, the speed is faster, and if the current is smaller, the speed is slow. The delay time td has the same tendency as expressed by Equation 1 for each variation factor. Therefore, as shown in FIG. 11B, the current increases as Lg, V _T , t _OX , 1 / β ₀ , T, and C _L increase, that is, the gate control V _CONT of the p-channel MOS transistor is high. At low values, V _CONT ', which controls the gate of the n-channel MOS transistor, changes from a low value to a high value, making it possible to keep td almost constant.

According to the present embodiment, since the operating current of the circuit is directly supplied from the power supply voltage, and V _CONT and V _CONT ′ only need to drive the gate of the MOS transistor, the driving capability of the control circuit 3 can be reduced, and the design is very easy. Done.

In this embodiment, although the p and n bichannel MOS transistors are controlled in such a manner, only one of them may be provided as necessary. In addition, in the MOS transistor in the embodiment of Figure 11 T _P1, or the like to significantly than the gate width of the T _N1 to T _P2, T _N2 T _P1, largely to leave the on-resistance of the T _N1 than T _P2, T _N2 , The current flowing through T _P1 and T _N1 is determined by the on-resistance of T _P2 and T _N2 , making it easier to control.

Although an example of an inverter is shown in Fig. 11, the present embodiment is not limited to this and can be applied to various logic circuits such as a NAND circuit and a NOR circuit. That is, in Fig. 11, DRIV having a function of the driving circuit may be replaced with a logic circuit.

12A and 12B show an example in which the control method of FIG. 11 is applied to a driving circuit of Bi-CMOS having higher driving capability than that of CMOS. As is well known, in a Bi-CMOS circuit, a base current of a bipolar transistor is controlled by a MOS transistor, and the current is amplified in the bipolar transistor to drive a load capacity. Therefore, the speed of the circuit can be controlled by controlling the base current as shown in FIG. 12A. In FIG. 12A, when the input IN becomes low, pMOS T _P2 , nMOS T _N4 is turned on, and nMOS T _N3 , T _N2 , and T _N1 are turned on. As a result, the bipolar transistor Q _N3 is turned on and Q _N4 is turned off. At this time, the base current through Q _N3 can be controlled by T _P1 applied to the V _CONT to the gate. Therefore, the speed at the time of output charging can be controlled by V _CONT . On the other hand, when the input IN becomes high, the bipolar transistor Q _N3 is turned off and Q _N4 is turned off to start discharging the output. At this time, the base current of Q _N4 is supplied from the output OUT, but this can be controlled by V _CONT ', so that the discharge rate of the output can be controlled by V _CONT '. In this manner, in this embodiment, the operating speed of the Bi-CMOS circuit can be controlled.

In addition, in order to control the speed of the Bi-CMOS circuit, the portion of the DRIV in FIG. 11 may be simply replaced with the Bi-CMOS circuit as shown in FIG. 12B. In this case, since the current is determined by the MOS transistors T _P2 and T _N2 in FIG. 11A, the current can be controlled with higher precision than in the case where only the base current is controlled as in FIG. 12A. In addition, since the MOS transistor in DRIV can be made smaller by the driving capability of the bipolar transistor than in the circuit of Fig. 11, there is an advantage that the input capacitance seen at the input IN is small. That is, since the load of the front end is light, it can speed up.

As shown in FIG. 11, a method of controlling a current by inserting a MOS transistor between a power supply and a driving circuit can be applied to other applications. 13 is an example applied to a level converting circuit for obtaining an output amplitude higher than the input amplitude. The circuit operation of FIG. 13 will be described with reference to FIG. When E is state of the high potential and the input IN to the high potential V _A, the potential of F via the nMOS T _N3 is at a potential of V _A -V _T. Subsequently, when E becomes low, the pMOS T _P3 is turned on and the potential of F becomes V _H. As a result, the pMOS T _P1 is turned off, the nMOS T _N1 is turned on, and the output OUT becomes 0V. When F rises to the high potential V _H , the potentials of A and IN are V _A and T _N3 is off, so that a current flows from F to IN so that the potential of F does not drop. On the other hand, if E is at a high potential and IN is at a low potential, T _N3 is on and F is at the same low potential as IN. As a result, T _P1 is turned on and T _N1 is turned off to charge the output OUT to high potential V _H. In this circuit, as indicated by the dotted line in Fig. 14, when the period t _CE is long from IN to high potential V _A and then to E low potential, the high potential of F remains briefly at V _A -V _T. Therefore, there may be a period in which through current flows through T _P1 and T _{N1 so} that OUT stays at an insufficient low potential. Therefore, it is desirable to shorten the time of t _CE . For this, it is good to change E to low potential while IN becomes high potential. Thereby, the said problem can be solved.

As described above, according to the embodiment of FIG. 13, the amplitude V _A of the input IN can be converted into the high amplitude V _H. At this time, since the current can be controlled by the MOS transistors T _P2 and T _N2 , it is possible to operate at a desired constant speed. The embodiment of Fig. 13 is effective as a circuit for obtaining an output voltage higher than an input voltage, for example, a word driver of a dynamic memory.

15 is another embodiment for controlling the speed of the driving circuit. This embodiment is an example in which the inverter is configured to obtain an output directly from the MOS transistor for current control in FIG. In FIG. 15, when the input voltage becomes high, the pMOS T _P1 and T _P3 are turned off and the nMOS T _N1 and T _N3 are turned on. As a result, the gate of pMOS T _P2 becomes V _CONT , and the gate of nMOS T _N2 becomes 0V. As a result, T _P2 is turned on and T _N2 is turned off, and a current controlled to a desired value by V _CONT flows to the output to charge the load. When the input IN becomes low, on the contrary, T _P2 is turned off and T _N2 is turned on to start the discharge operation and OUT becomes 0V. At this time, since the gate voltage of T _N2 is V _CONT ′, the rate of discharge can also be controlled by V _CONT . In this embodiment, since two MOS transistors are not connected in series between the power supply and the output, they are suitable for high speed operation.

Further, control is easier than in the case of Fig. 11 in which the influence of the characteristic variation of two transistors connected in series is taken into consideration.

Although the method of controlling the operation speed of the driving circuit has been described above, the external voltage Vcc is applied to a part of the circuits of FIGS. 7 to 12 and 15. Therefore, in some cases, it is also considered that a problem occurs such that it becomes difficult to compensate for variations in Vcc. In this case, as shown in Fig. 5, by providing the voltage conversion circuit 3A in the control circuit 3 and keeping the output voltage V _I constant, the internal circuit can be operated stably against the variation of Vcc. There is a number. In this case, when the internal voltage V _I is set low, the micronized element with low breakdown voltage can be stably operated.

Fig. 16 shows one embodiment in which a voltage conversion circuit is provided in a chip as described above. In Fig. 16, reference numeral 5I denotes a power supply line for supplying the voltage V _I from the voltage conversion circuit 3A to the circuit 3B and the internal circuit 2 in the control circuit. The ICL is a current control circuit that controls the current of each circuit DRIV in the internal circuit, such as the MOS transistors T _P2 and T _N2 in FIG. 11. With this arrangement, it is possible to stabilize the device miniaturized by the constant voltage V _I does not depend on the external voltage Vcc operation, also possible to operate at the desired speed according to the respective function circuits.

17 is an embodiment showing another means for controlling the operation speed of the CMOS inverter. Here, to control the threshold voltage of T _P1, T _N1 by controlling the voltage of the substrate SBP1, SBN1 of T _P1 and T _N1, and controls the operating characteristics of the inverter as a result. This embodiment is suitable for compensating for the characteristic change caused by the variation of the threshold voltage.

Although a CMOS inverter is shown in Fig. 17, it can be applied to other circuits using MOS transistors such as Bi-CMOS inverters. It is of course possible to combine the method of controlling the substrate voltage in this manner with the other control methods described so far. 7 to 17 mainly describe a method of controlling characteristics of a drive circuit such as an inverter, a non-inverter, and a NAND circuit, but in the integrated circuit, a differential amplifier that generates an output according to a voltage difference is also widely used. Next, an embodiment of this differential amplifier is described.

FIG. 18 shows another embodiment of the present invention in which the control method of FIG. 11 is applied to the operation speed control of a differential amplifier composed of a MOS transistor. In Fig. 18, IN1 and IN2 are differential inputs, and OUT1 and OUT2 are differential outputs. Also in this circuit, the operating speed changes with the same tendency as in FIGS. 7 and 11 with respect to variations in manufacturing conditions and usage conditions. Accordingly, by controlling V _CONT and V _CONT ′ as in FIG. 11B, the operating current changes, and as a result, the operating speed can be controlled in accordance with manufacturing conditions or usage conditions. The output voltage of this differential amplifier is determined by the product of the operating current and the on-resistance of the load MOS transistors T _PL , T _PL '. Therefore, if V _CONT and V _CONT ′ are controlled so that the ratio of the ON resistance of T _NC to determine the operating current and the ON resistance of T _PL , T _PL 'is constant, the on-resistance of the operating current and T _PL , T _PL ' The product, i.e., the output voltage, remains constant and the speed of operation can be controlled.

FIG. 19 is an embodiment in which T _NA and T _NA 'of FIG. 18 are replaced with NPN bipolar transistors Q _NA and Q _NA ', and the same effects as those of FIG. Has

FIG. 20 is a diagram in which the current control transistor T _NC of FIG. 19 is replaced with an NPN bipolar transistor Q _NC and a resistor Rc. Similar to FIGS. 18 and 19, the operation speed can be controlled. In addition, since the operating current becomes more constant, the amplification factor can be increased. 18 to 20, when applying Vcc becomes a problem in terms of characteristic variation due to breakdown voltage or Vcc variation, a desired voltage is set by the voltage conversion circuit 3A provided inside the chip as shown in FIG. It is good to apply.

As mentioned above, although the Example suitable for controlling the characteristic of the various element circuits which comprise the circuit 2 was described, the specific Example of the control circuit 3 is described next.

21 shows that one embodiment. In Fig. 21, T _PR is a p-channel MOS transistor, and CC is a constant current source through which constant current i flows. According to this embodiment, even if the manufacturing conditions such as the gate length of T _PR , the threshold voltage, the gate oxide film thickness, or the use conditions such as the temperature vary, the output 5 always outputs the gate voltage necessary for flowing a constant current through the T _PR . do. Therefore, it is suitable as the V _CONT generating circuit of FIGS. 11 to 13, 15, 18 to 20 and the like. When applied to these circuits, T _PR and T _{P2 in} Figs. 11 to 13 and 15 or T _PL and T _PL 'in Figs. 18 to 20 become well-known connection of current mirror circuits. Therefore, by appropriately selecting the transistor dimensions of T _P2 , T _PL , and T _PL ′ for that of T _PR , the operating current of each circuit can be controlled to any fixed value.

Fig. 22 is an embodiment in which Fig. 21 is composed of an n-channel MOS transistor, which is most suitable as the generation circuit of V _CONT ′ in Figs. 11 to 13, 15, 18, and 19, and the same effects as those in Fig. 21 can be obtained. .

FIG. 23 shows an embodiment in combination with FIGS. 21 and 22.

According to the present embodiment, V _CONT and V _CONT ′ for FIGS. 11 to 13, 15, 18, and 19 can be generated simultaneously, and these voltages are generated based on the same constant current source, so that mutual compatibility is achieved. This high very stable voltage can be obtained.

24 illustrates an embodiment in which V _CONT is generated by connecting a p-channel MOS transistor T _PR and an n-channel MOS transistor T _NR in series. According to the present embodiment, the influence of variations in the manufacturing conditions and usage conditions of the p and n bichannel MOS transistors is reflected in the value of V _CONT . Therefore, it is suitable as the V _CONT generating circuit of Figs.

FIG. 25 shows an embodiment in which an amplifier stage comprising an amplifier 7 and a feedback circuit 8 of feedback rate β is added to the output of FIG. In this embodiment, if the amplification factor is selected very large, the output V _CONT

By setting β appropriately, any value can be obtained. Therefore, in addition to reflecting the influence of variation in manufacturing conditions and usage conditions by V ₀ , the role of all or part of β can be shared by giving β dependence on manufacturing conditions and usage conditions.

Fig. 26 shows one specific embodiment of the constant current source CC. FIG constant current source CC1 as 26 is composed of resistors R ₁ ~R _4, and an NPN bipolar transistor Q _N1, Q _N2. In the present embodiment, the voltage of the base B _N1 of Q _N1 is sufficiently large that the current amplification factor of the bipolar transistor is high, and the constant voltage of V _BE (R ₂ + R ₃ ) / R ₃ is set when the forward voltage between emitter-base is V _BE . It becomes a voltage.

therefore,

Constant current flows. Since V _BE is almost unaffected by variations in manufacturing conditions, stable current can be output.

In this embodiment, since i flows in from the outside toward ground, it is suitable as a constant current source of the circuit as shown in FIG.

27 shows an embodiment in which a constant current source is configured using a PNP bipolar transistor. The polarities of the voltages and currents are different from those of Fig. 26, and the operations are completely the same. In this embodiment, since i flows out from the power supply voltage Vcc, it is suitable as a constant current source of the circuits shown in Figs.

FIG. 28 illustrates an embodiment in which a constant current source having a current flowing out from a power supply voltage is realized as an NPN bipolar transistor as shown in FIG. 27. In this embodiment, there is a problem in that the operating currents of R ₁ , R ₂ , R ₃ , and Q _N2 are added to the constant current, but the influence can be ignored by sufficiently increasing the current amplification factor of Q _N1 .

According to this embodiment, it is easy to make a constant current source of a type in which current flows out of Vcc, and can be realized by using a high-performance NPN bipolar transistor. In addition, the present embodiment can be used as any type in which current flows in and out.

Fig. 29 applies this constant current source to the circuit of Fig. 23 utilizing this feature. According to the present embodiment, V _CONT and V _CONT ′ can be output at the same time.

30 is a constant current of a type in which a current flows out of Vcc by a current mirror circuit including a current source CC into which the current flows toward the ground and a p-channel MOS transistor T _PM , T _PM ', for example, the constant current source CC1 of FIG. 26. The embodiment which realized the circle.

By making the dimensions of T _PM and T _PM 'the same, the current flowing in both can be made the same, and a current having the same value as the output current i of CC can be output from the power supply voltage Vcc to the outside. V _CONT 'can be obtained by inputting this to the n-channel MOS transistor T _NR similarly to FIG. In this embodiment, the output current can be arbitrarily determined with respect to the current value of CC by appropriately selecting the ratio of the dimensions of T _PM and T _PM '.

FIG. 31 shares the voltage generated by T _PM and CC in FIG. 30 as the voltage of V _CONT . According to the present embodiment, V _CONT and V _CONT ′ can be generated at the same time, and the characteristics of both can be controlled consistently as in FIG. 23.

Fig. 32 shows an embodiment in which a constant current source of high stability is realized by using a MOS transistor.

In Fig. 32, T _N61 to T _N63 are n-channel MOS transistors, T _N61 is negative, and T _N62 has a positive threshold voltage. The threshold voltage of T _N63 may be either government. R ₆₁ to R ₆₃ are resistors, and (7) are differential amplifiers.

Here, R _61, leaving the dimension of the value of R ₆₂ and T _N61, T _N62 same set, respectively, and operates the current flowing through the T _N61, T _N62 so as to be equal to each other. Thus, the gate voltage V T of _{I6 N62} is at a voltage equal to the difference between the threshold voltage of T and T _{N61 N62.} The value of the difference of the threshold voltages is maintained almost constant regardless of the manufacturing conditions or usage conditions.

In the above circuit, the drain and source currents of T _N63 are the same, so the output current i is

It can be expressed as Therefore, a current output having the same characteristics as V _I6 can be obtained, and the value thereof can be arbitrarily controlled by R ₆₃ .

This embodiment can be used as the constant current source of each embodiment, for example, for the current source CC of FIG.

According to this embodiment, the circuit can be configured without using a bipolar transistor, and therefore, it is suitable for an integrated circuit composed of MOS transistors.

FIG. 33 shows an embodiment more suitable as the constant current of FIGS. 21-25, 30, 31, and the like. In this embodiment, a well-known bandgap generating circuit is applied as a constant current source, and a high-definition current can be obtained, particularly with respect to variations in temperature, power supply voltage, and the like.

In FIG. 33, Q ₅₁ to Q ₅₆ are bipolar transistors, and R ₅₁ to R ₅₅ are resistors, and a constant current i having desired temperature characteristics can be formed. I ₅₁ is a current flowing through the resistor R ₅₁ , i ₅₂ is a collector current of the bipolar transistor Q ₅₂ , and i ₅₃ is a collector current of the bipolar transistor Q ₅₃ . Before describing the output current i, the value of the internal voltage V _I1 and the temperature dependence of the present circuit will be described. In the following description, for simplicity, the base current is negligible compared to the collector current of the bipolar transistor, and the collector current and the emitter current are almost the same. The voltage V _I1 is represented by the following equation.

Here, V _BE (Q ₅₁ ), V _BE (Q ₅₂ ), and V _BE (Q ₅₆ ) are forward voltages between base-emitters of the bipolar transistors Q ₅₁ , Q ₅₂ , and Q ₅₆ , respectively. In Formula 4, the current I ₅₂ is represented by the following formula.

Here, a bipolar transistor Q ₅₅ and the emitter of the emitter ₅₄ by Q to suitably select the area, setting the current density of the bipolar transistor Q ₅₅ n times of the bipolar transistor Q _54,

This holds true. In Equation 6, k is Boltzmann's integer, T is the absolute temperature, and q is the charge of the electron. By equations 4 to 6

This holds true. Therefore, if the emitter current densities of the bipolar transistors Q52 and Q56 are designed to be the same, the right and right sides 3 and 4 of Equation 7 are deleted.

This holds true, and the temperature dependence of electricity V _I1

It becomes As is well known, the base-emitter voltage of a bipolar transistor has a negative temperature dependency. Therefore, by changing the ratio of the resistors R ₅₂ and R ₅₄ or the ratio n of the emitter current densities of the bipolar transistors Q ₅₅ and Q ₅₄ in equation 9,

Can be set arbitrarily.

Since the value of _VI1 obtained when this temperature coefficient is 0 becomes a value around 1.2V, which is almost equal to the bandgap voltage of the silicon semiconductor, it is generally called a bandgap generating circuit.

In the above circuit, since the collector current and emitter current of Q ₅₆ are almost the same, the output current i is

It can be expressed as Therefore, a current output having the same characteristics as V _I1 is obtained, and the value thereof can be arbitrarily controlled by R ₅₅ .

When the present embodiment is used as the constant current source of each of the embodiments described above, highly reliable control is possible. In particular, regarding the temperature, the temperature coefficient of the electrostatic source can be set to 0, or positive or negative, depending on the purpose, whereby the operating characteristics of the circuit can be arbitrarily controlled.

The internal voltage V _I1 of the present embodiment can also be used as a constant voltage source of high stability. At this time, when the constant current output i is unnecessary, the output terminal may be connected to Vcc.

For example, V _I1 may be used as V _CONT ′ in FIG. 20, and in this case, temperature characteristics of the differential amplifier can be controlled.

Some specific examples have been described so far and the control method of the circuit characteristics according to the present invention has been described. Although these embodiments can be easily realized, in the case of using a fine element for increasing the degree of integration, the breakdown voltage of the element may be low, and it may be difficult to directly request the external voltage Vcc directly to the element. In addition, when the external voltage fluctuates, it may be difficult to obtain desired characteristics. In such a case, as in the embodiments of Figs. 4, 5 and 16, a stable voltage V _I may be formed inside the chip and used instead of Vcc. At this time, Vcc may be applied in some cases, and in the case where there is no problem, Vcc may be applied. By doing so, the burden on the voltage source generating the voltage V _I is reduced, and thus V _I can be maintained more stably.

FIG. 34 shows an embodiment for controlling the operation speed to a desired value when the internal voltage V _I is used. Although the case where the CMOS inverter shown in FIG. 11 is controlled by the circuit of FIG. 21, FIG. 22 is demonstrated as an example, it is not limited to this, It can apply to the various Example described so far. In FIG. 34, pMOS T _P2 and T _PR and nMOS T _N2 and T _NR form a current mirror. Therefore, similarly to the above embodiment, if the size of T _P2 for T _PR is appropriately set, the charging current of the driving circuit DRIV can be set to an arbitrary value. In addition, if properly set the size of the T _N2 for T _NR, it may set the discharge current to an arbitrary value. Here, if the source voltage of the pMOS T _PR and T _P2 and the power supply voltage V _I of the current source CC2 are kept lower than the device breakdown voltage, a microelement having a low device breakdown voltage can be used. In addition, in the present embodiment, the output amplitude is also V _I , so that the voltage input to the next stage can be controlled stably, and the operation of the next stage can also be stably maintained. In addition, the V _CONT and V _CONT 'generation circuits 31 and 32 can be shared by multiple circuits. Even in this case, if the sizes of T _P2 and T _N2 are set for each circuit, each circuit is controlled at a desired speed. can do.

Next, an embodiment of a voltage conversion circuit suitable for generating a voltage lower than Vcc in the chip as shown in Figs. 4, 5, 34, etc. will be described.

35 shows one embodiment of the configuration of the voltage conversion circuit. Where A is a voltage conversion circuit, F is a constant voltage generating circuit, and G is an amplifier. The constant voltage generating circuit F generates the constant voltage V _I1 at the external power supply voltage Vcc. The amplifier G amplifies the voltage V _I1 and outputs the voltage value V _I required for the internal circuit 2 or part 3A of the control circuit to the control line 5I. Here, the voltage V _I can have various characteristics by the constant voltage circuit F and the amplifier G. For example, by compensating for the temperature dependence and the external power supply voltage dependency, the output amplitude of the circuit as shown in FIG. 34 can be made constant without depending on Vcc and temperature, so that a highly stable operation can be realized. According to this embodiment, the output voltage V _I1 of the constant voltage circuit can be amplified to a desired voltage value by the amplifier G. Therefore, the value of the voltage V _I can be set without being limited to the value of the output voltage V _I1 of the constant voltage circuit.

In the embodiment shown in FIG. 36, the amplifier G is constituted by the differential amplifier GD and the feedback circuit H in FIG. Here, the feedback circuit H is designed such that the same voltage as the constant voltage V _I1 is output to the output I ₂ when the voltage V _I takes a desired value. According to this embodiment, since the fluctuation of the output voltage V _I is fed back through the feedback circuit H, even if the current supplied from the control line 5I changes at high speed with time, the value of the output voltage V _I can be precisely adjusted. You can keep it constant.

FIG. 37 shows a specific configuration example of the constant voltage generating circuit F in the embodiment of FIGS. 35 and 36, which is a circuit in which the collector of the bipolar transistor Q ₅₆ is connected to Vcc in the current source shown in FIG. In the circuit of Fig. 37, the output voltage V _I1 and its temperature dependence are given by equations (8) and (9). As described above, the temperature dependency can be set by changing the ratio of the resistance or the ratio of the current density of the bipolar transistor.

In the case where the present embodiment is used as the constant voltage generating circuit F of the embodiment shown in Figs. 35 and 36, the temperature of the amplifier G, the differential amplifier GD, and the feedback circuit H of the rear stage is adjusted. The temperature dependence of the output voltage V _I of the voltage conversion circuit A can be set to 0 or a desired value by designing the value of.

The configuration shown in FIG. 37 is generally referred to as a bandgap reference circuit, and is described by "ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS" (PAUL R. GRAY, ROBERT G. MEYER, JOHN WILEY AND SONS, Inc., 1977). It is almost the same as providing the output terminal J at the output of the Widlar band-gap reference described in Fig. 4, 30a of pp. 259.

In addition, in the embodiment of Fig. 37, when the external voltage Vcc is almost twice the base-emitter forward voltage of the bipolar transistor and exceeds about 1.8V, the voltage V _I1 becomes almost constant without depending on Vcc. Therefore, if the present embodiment is used in Figs. 35 and 36, the output voltage V _I without temperature dependency and external voltage dependency can be easily obtained.

By the way, when the constant voltage circuit F and the other circuits are simultaneously formed in the same semiconductor substrate as described in the above-described embodiment, it is possible to simplify the process process by unifying transistors used in both of them as MOS transistors or bipolar transistors. In some cases, the manufacturing cost can be reduced. Therefore, as a constant voltage circuit F, it is preferable to use a MOS transistor instead of using a bipolar transistor as in the embodiment of FIG. In that case, for example, in Fig. 32, V _I6 of a circuit in which the drain of the MOS transistor T _N63 is set to Vcc may be used, or OGUEY, Journal of Solid-State Circuit, SC-15, Jun. '80 or BLAUSCHILD, Journal of Solid-State Circuit, SC-13, Dec. The constant voltage generation circuit described in '78 may be used.

FIG. 38 shows a specific embodiment of the differential amplifier circuit GD in FIG.

In Figure 38, the output voltage V _I1 of the constant-voltage circuit to the terminal I F _1, is applied to the output voltage V _I2 of the feedback circuit to the terminal I _2. In this embodiment, the terminals I ₁ and I ₂ are the base electrodes of the bipolar transistor, so that the gain is high and the variation in the voltage V _I can be suppressed to be small. In addition, the p-channel MOS transistor in FIG. 38 can be substituted with a resistor as shown in FIG. Since this resistor can be comprised by the base diffusion layer of a bipolar transistor, it can be formed in the impurity layer for the collector of a bipolar transistor. Therefore, the layout area of the circuit can be reduced.

Although various circuits can be considered as the current source of the differential amplifiers of FIGS. 38 and 39, it is also possible to realize one MOS transistor as shown in FIGS. 40 and 41. Here, the gates of the MOS transistors T _I61 and T _I71 were connected to I ₁ . Since V _I1 becomes a constant value for Vcc as described above, the current of the amplifier can be kept constant with respect to Vcc. When it is necessary to stably control the characteristics of the amplifier, various controls can also be executed using a circuit as shown in Figs.

FIG. 42 shows a specific embodiment of the feedback circuit H in FIG.

In Fig. 42, the output terminal I ₂ is connected to the voltage V _I of the control line 5I.

Are output, and is input to the differential amplifier in FIG. 36, according to the desired voltage to output the output voltage of the constant voltage circuit F to V _I1, control line (5I) as a V _IO

When the resistors R ₈₁ and R ₈₂ are designed to satisfy V _i = V _IO and V _I1 = V _I2 , the voltage on the control line 5I is stable at the desired voltage V _IO . If the output voltage V _I1 of the constant voltage circuit F is designed such that the temperature dependency is zero as described above, the temperature dependency of the voltage V _IO can be made almost zero.

In addition, it is, of course, possible to give V _IO the desired temperature dependence as needed.

FIG. 43 shows another embodiment of the feedback circuit H in FIG. In the embodiment of Figure 43 without connecting the control line (5I) in direct resistance it was connected to the base electrode of the bipolar transistor Q _91. Therefore, since the current is amplified by the bipolar transistor Q ₉₁ , a higher speed operation can be realized than in FIG. 42. In addition, the load current of the differential amplifier GD can be reduced. In FIG. 43, Formula 11 and Formula 12 are respectively

Therefore, the values of the resistors R ₉₁ and R ₉₂ may be determined so as to satisfy the expression (14). In this case, however, as shown in Equation 14,

Therefore, the temperature dependence of the voltage V _IO does not coincide with the temperature dependence of the voltage V _I1 by the second term of Equation 15. In this case, by

, The desired V _IO , In accordance with Eq. 15 and Eq. 16, Of course it can also be 0.

On the other hand, if the above circuit is used, even if the power supply voltage Vcc becomes excessive, the output voltage can be set to a constant value lower than Vcc, which has the advantage of preventing the minute device from being destroyed. But on the other hand, there are cases where it is not always appropriate to conduct a valid aging test.

In a general integrated circuit, after the final fabrication process, a voltage higher than that used in normal operation is deliberately applied to each transistor in the circuit, and an aging test is performed to initially detect a transistor that is likely to malfunction due to a poor gate oxide film or the like. Guaranteed reliability. In order to improve the detection rate of defects by this aging test, it is necessary to apply a voltage slightly lower to each device than the normal device is destroyed. However, in the integrated circuit chip configured to supply a constant power supply voltage through the voltage conversion circuit inside the chip as described above, there is a fear that sufficient aging voltage is not applied to the internal circuit. In this case, voltage conversion as shown in FIG.

The voltage V _I generated in the circuit may be designed to rise when the external power supply voltage Vcc becomes excessively large. In FIG. 44, the internal power supply voltage V _I is maintained at a constant value V _IO from V _CI to V _CE , and when Vcc exceeds V _CE , the external power supply voltage Vcc rises as Vcc rises. In this way, when Vcc is raised above V _CE , V _I also increases. Therefore, in an aging test, when Vcc is raised above V _CE , a voltage higher than V _IO can be applied to the circuit in the chip. This allows you to run valid aging tests.

FIG. 45 shows a specific embodiment for realizing the voltage characteristics shown in FIG. A constant voltage circuit in Fig. 45 F was connected like will insert a resistance R ₁₁₁ between the collector and the terminal D of the bipolar transistor of the output stage J according to the embodiment of Figure 37, the differential amplifier GD and a feedback circuit H is 36 .

Further, a bipolar transistor the collector of the bipolar transistor Q ₁₁₁ to Q _112, and connected to the base of the control wire (5I) the emitter of the bipolar transistor Q _112, the collector was connected to Vcc. Stable point after reaching the V _IO until the bipolar transistor Q ₁₁₂ is onhal V _I is the constant as V _IO, after the bipolar transistor Q ₁₁₂ is onhan of the external supply voltage Vcc, the output voltage V _I In this circuit the output voltage Rises with Vcc. The point V _CE at which the bipolar transistor Q ₁₁₂ is turned on is given by the following equation.

Here, the current i ₁₁ is a current flowing through the resistor R ₁₁₁ and satisfies the following equation.

therefore,

When Vcc rises above V _CE , V _I rises according to the following equation.

As described above, according to the present embodiment, when the external voltage Vcc exceeds V _CE , the voltage V _I rises with Vcc, so that the aging test can be effectively executed.

However, when the temperature dependence of V _IO is designed to be 0, the temperature dependence of V _CE is

On the other hand, the temperature dependence of V _I at Vcc> V _CE is

It becomes Here, when using the circuit of Fig. 42 as the feedback circuit H, = 0

Vcc ＞ V _CE

It becomes

The temperature dependence of V _BE is typically is about -2㎷ / ℃, the temperature dependence of V _I in the temperature dependence of V _CE and V _CE> Vcc is very small. In the case of using the embodiment of Fig. 43 as the feedback circuit H, Equation 14

So, by equation 21, equation 22

Vcc ＞ V _CE

It becomes

Here, by equations 15 and 19

If is set to η,

Is established. Therefore, for example, when V _CE = 6V and V _IO = 4V

V _BE (Q ₁₁₂ ) = V _BE (Q ₉₁ ) = 0. As 8V,? = 3/8, and in Expressions 23a and 23b, And Vcc> V _CE Are each about -1. 25 kPa / ° C and about +1. Since it is 25 kW / ° C, even when the circuit of FIG. 43 is used as the feedback circuit H, the temperature dependency of V _{CE and} the temperature dependency of V _I at Vcc> V _CE are very small. When the circuit of FIG. 43 is used, the value of V _CE is approximately twice that of V _IO , so that the temperature dependence of V _{CE and} the temperature dependence of V _I at Vcc> V _CE can be made almost zero at the same time. Can be. _{I.e., V BE (Q 112) ≒} V BE When a (Q _91), and a V _CE ≒ 2V _IO when η = 1 days by formula 23c, By equation 23a Becomes Further, in the Vcc> V _CE by the expression 23b Becomes

Above-described both the voltage characteristic of Figure 44 or the case of using the circuit of Figure 43 when using the circuit of Figure 42 as a feedback circuit H can be realized with little temperature swing, the normal operation region in Vcc≤V _CE as Vcc or > also in all areas of the aging test of the V _CE, and may cause the voltage V _I with little temperature dependence, it is possible to stably operate an internal circuit group.

Also has a temperature dependency as needed, V _IO as described above is of course possible. In addition, when it is necessary to set the temperature dependency of the aging test region independently of V _IO , as shown in FIG. 37, a collector of Q ₁₁₁ is connected to Vcc so that a current source having a desired temperature dependency of R ₁₁₁ and F for bias of K is separated from F. You should prepare.

In FIG. 45, a bipolar transistor Q ₁₁₂ was used to raise the voltage V _I at Vcc ≧ V _CE . However, of course, it is also possible to replace Q ₁₁₂ with an nMOS transistor so that the gate of the nMOS transistor is connected to the terminal K, the drain is connected to Vcc, and the source is connected to E. At this time, since the terminal K is connected to the gate of the nMOS transistor, it is not necessary to supply a current. Therefore, the design of the constant voltage generation circuit can be facilitated.

According to the embodiment described above, the control line 5I can supply a stable voltage having a desired temperature dependency and not depending on the external power supply voltage in a desired range. Therefore, the circuit in the same chip can be operated stably. However, in the case where the current supplied from the control line 5I is particularly large, in order to prevent voltage variations, a buffer circuit for current amplification is added to the voltage conversion circuit A so that the output 5I 'of the buffer circuit is used as the control line. It is good to use.

Fig. 46 shows one embodiment of the buffer circuit, where C ₁₂₁ and C ₁₂₂ are capacitors for reducing the potential variation of the terminal N _B and the control line 5I '. In Fig. 46, the voltage V _I ′ of (5I ′) is

or

It is represented by

Therefore, in this embodiment

In the region of V _I 'is almost equal to V _I. Due to the use of the embodiment described above in the generation circuit of the V _I, it can also control the temperature dependence of V _I '. In this circuit, since 5I 'is connected to the emitter of the bipolar transistor, it is possible to supply a larger current than the control line 5I'. That is, even when the current supplied to the circuit is large, the voltage V _I ′ can be kept stable.

FIG. 47 shows an example in which the bipolar transistor of FIG. 46 is replaced with a MOS transistor. In this embodiment, V _TH (T _M132 ) is set as the threshold voltage of the MOS transistor.

Vcc≥V _I + V _TH (Q ₁₃₂ )

In the region of V _I ′ is almost equal to V _I.

Since the threshold voltage of the MOS transistor can be easily controlled, it is possible in this embodiment, in the same way as the output voltage V _I V _I, V _I When Vcc is turned from low to stabilize the.

In the above two embodiments, the range of the external voltage where the voltage V _I and the output voltage V _I ′ of the buffer circuit are equal is the forward voltage between the base and the emitter of the bipolar transistor as shown by Equations 26 and 27, or It is limited by the threshold voltage of the MOS transistor. Therefore, for example, even if the output voltage V _I of the voltage conversion circuit is constant at 4 V when the external voltage Vcc is 4 V or more, the buffer output voltage V _I ′ of FIG. 46 is not equal to about 4. 8 V or more. It is not constant at 4V. Therefore, the operation margin of the internal circuit with respect to the external voltage Vcc may be narrowed. In such a case, a buffer circuit as shown in FIG. 48 may be used.

48 shows (5I ') connected to the drain of the p-channel MOS transistor T _M141 , and the source of this MOS transistor is connected to the external power supply Vcc to control the gate G ₁₄₁ to the output voltage of the differential amplifier O. Here, the output voltage V _I of the voltage conversion circuit A and the output voltage V _I ′ of this buffer circuit were input to the input terminals of the differential amplifier, respectively. Here, the capacitor C ₁₄₁ is for suppressing the fluctuation of the output voltage V _I ′. With this arrangement, the voltage V _I output 'by the differential amplifier is maintained at a value equal to the voltage V _I. Therefore, unlike the embodiments of FIGS. 46 and 47, the output voltage V _I ′ can be made the same as the voltage V _I without depending on the external voltage Vcc, so that a stable voltage can be obtained in a wide range of the external voltage Vcc. .

FIG. 49 shows an example of the specific circuit configuration of FIG. In Fig. 49, the terminal P, The reversed signal is applied to each. Hereinafter, the signal P is at a high level, The circuit operation will be described for the case where is at the low level, but the signal P is at the low level, The same is true when is at a high level.

In addition, as will be described with a Vcc of 5V, V _I for a description of the present embodiment to 4V, it is the same even when the other voltage relationships.

In addition, for simplicity, the base-emitter voltage of a bipolar transistor is demonstrated as 0.8V. When V _I is 4V, the base potential V _B153 of the bipolar transistor Q ₁₅₃ becomes _1.6V . At this time, the potential V _I ′ of the control line 5I ′ is 4V, and the base potential V _B154 of the bipolar transistor Q ₁₅₄ is _1.6V . Here, when V _I ′ decreases, V _B154 also decreases, and the collector current of the bipolar transistor Q ₁₅₄ decreases. On the other hand, since the collector current of the bipolar transistor Q ₁₅₃ increases, the current flowing through the resistor R ₁₅₁ increases. As a result, the gate of the MOS transistor T V _{GM141 M141} decreases. Accordingly, the drain current of the MOS transistor T _M141 increases and V _I ′ rises to recover to 4V. On the contrary, when V _I 'rises, V _GM141 rises, MOS transistor T _M141 turns off, and V _I ' falls and recovers to 4V. In addition, since the diodes D ₁₅₃ to D ₁₅₅ are connected in series between the collector and Vcc of the bipolar transistor Q ₁₅₃ , the collector potential does not drop below 2. 6V. On the other hand, since the base potential V _B153 is _1.6 V, the base potential of the bipolar transistor Q ₁₅₃ is always lower than the collector potential. Therefore, the bipolar transistor Q ₁₅₃ does not saturate. The base potential of the bipolar transistor Q ₁₅₄ is V _I ′ -2.4 V, the collector potential is Vcc-2.4 V, and since V _I is usually lower than Vcc, Q ₁₅₄ does not saturate. By the way, when the circuit connected to the control line 5I 'is in the standby state, the current flowing in the 5I' is often small and almost constant. In this case, even if the current flowing through the amplifier is reduced, V _I can be kept constant, and the power consumption can be kept low by reducing the current. This requires increasing the resistance of the resistor R ₁₅₂ than R _151, and the MOS transistors T _M153, T _M154, T _M155 respectively set larger than T _M156, T _M157, T _M158 a gate width of a, and further connected to (5I ') When the circuit is in standby, terminal P, The potential of may be switched to the low level and the high level, respectively.

The output V _I or V _I ′ of the voltage generation circuit described with reference to FIGS. 35 to 49 can also be used as the V _CONT of FIGS. 7 to 10 in addition to the power supply of FIG. 34 and the like. As described above, according to the embodiment of Figs. 35 to 49, since the variation due to the external voltage Vcc and the temperature of V _I and V _I 'can be controlled, the circuit characteristics of Figs. You can keep it constant. Therefore, it is effective when the Vcc or temperature fluctuation becomes a problem in comparison with the fluctuation of the manufacturing conditions.

Up to now, a specific method of controlling the circuit operation has been described, but among these, the means for detecting and controlling the characteristics of the internal circuit have been described mainly on detecting the voltage value as shown in FIG. However, in some cases, a method of detecting and controlling the phase difference of a signal can also be used as follows.

FIG. 50A illustrates a specific embodiment of the configuration of FIG. 2. In this embodiment, the phase time difference Δt of two predetermined pulses φ ₁ and ψ ₂ in the circuit 2 is detected, and accordingly, the operation of the circuit 2 is controlled to keep the operation speed constant.

In Fig. 50, F / F is a set, reset type flip-flop, which outputs a signal? _I having a pulse width equal to the time difference? T between? ₁ and? ₂ . SW _I , SW _R and SW _S are the switches, C _I and C _H are the capacitances, and V _REF is the reference voltage for reference. The operation of this circuit will be described below with reference to FIG. 50B.

First, when ψ ₁ is input, ψ _I is output. As a result, the SW _I is turned on, the capacitor C _I is charged with the constant current i, and the voltage at the terminal 31 of the C _I gradually rises. If? ₂ is input after the? T time elapses,? _I becomes low potential and SW _I is turned off. Therefore, the voltage V _HL of the terminal 31 becomes a voltage proportional to Δt. This voltage is charged to the capacity C _H when ψ _S is input and SW _S is turned on. Here, if C _I >> C _H , the voltage at the terminal 32 is almost equal to V _HL . On the other hand, C _I is discharged at 0 V because SW _R is turned on by ψ _R , and is prepared for the next operation. V _HL charged with C _H is compared with the reference voltage V _REF by the amplifier 7, and outputs a voltage corresponding to the difference to the control line 5, thereby controlling the operating characteristics of the circuit 2. . The circuit 2 is constituted of a circuit as shown in Figs. 7 to 20, and its operating characteristics are changed by the voltage of the control line 5, and finally, the control is performed so that the values of V _REF and V _HL are the same. do. As a result, the circuit characteristics of the circuit 2 are kept constant.

In this embodiment, since the operating characteristic of the circuit 2 is directly detected and its characteristic is controlled, even if the characteristic changes due to factors other than the previously considered variation factor, it is possible to respond to it and control the characteristic with high accuracy. have. Since V _REF and i of the present embodiment dominate the control precision, they need to be highly stable. However, the embodiments of FIGS. 32 and 37 can be used as V _REF , and each embodiment of FIGS. 26 to 33 can be used as i. have.

In addition, although the operating characteristic of the circuit 2 was detected by the time difference of (phi) ₁ , (phi) ₂ , other things, such as detecting an operation current amount and controlling a characteristic, can also be considered.

FIG. 51 applies the embodiment of FIG. 50 to the embodiment of FIG. In this embodiment, the circuit 4 is constituted as a dummy of the circuit 2 by a part of the internal circuit 2 'constituting the circuit 2, and its operating characteristics are output to the outputs ψ ₁ ′ and ψ ₂ ′. It detects by the method similar to FIG. 50, and controls the operation characteristic of the circuit 2. As shown in FIG. As the circuit 2 ', a ring oscillator may be formed using an inverter as shown in FIG. 7, and various circuit types can be selected according to other purposes.

Also in this embodiment, the same effects as in FIG. 50 can be obtained.

In addition, when the base and collector current of the bipolar transistor are supplied from the same power source as shown in Fig. 12 in the above-described embodiments, the collector potential is temporarily lowered than the base potential due to the voltage drop caused by the collector resistance of the bipolar transistor. There may be a case where the saturation may occur. At this time, as shown in Fig. 52, two collector terminals may be provided, C1 may be used as a collector electrode of a bipolar transistor, and a MOS transistor for supplying a base current may be connected to C2. In this way, since the potential of the second collector electrode is lower than that of the original collector C0 of the bipolar transistor, the potential of this and the base connected via the MOS transistor does not become higher than the potential of the collector C0. Therefore, saturation of the bipolar transistor can be effectively prevented. This embodiment can be used without being limited to FIG.

53 is a specific embodiment in which each of the above-described embodiments is applied to a DRAM.

In Fig. 53, MARY is a memory cell array in which memory cells MC are two-dimensionally arranged. The PC is a data line precharge circuit, and the SA is a sense amplifier for amplifying a small signal output from the memory cell to the data line, and is composed of P and N channel MOS transistors. AB is an address buffer circuit for converting the address input Ain into an internal signal, and X-Dec & Driv. And Y-Dec & Driv. Are X decoder drivers and Y decoder drivers, respectively. The DP is a data line precharge voltage generator circuit, SAD, Is a driving circuit of the sense amplifier SA, WC is a write control circuit for writing the data input signal Din to the memory cell according to the instructions of the write signal WE, and the peripheral circuit generates pulse signals necessary for the operation of each circuit according to the external input CE. The circuit MA is a main amplifier which amplifies the read signal on the I / O line, and the embodiment shown in Fig. 19 is applied here. The control circuit 3 outputs a signal in response to variations in manufacturing conditions, use conditions, etc. to the control line 5, thereby controlling the operation of each circuit to stabilize the characteristics. Each circuit is composed of a circuit as shown in FIGS. 7 to 20 so as to be controlled by the output 5 of the circuit 3.

The operation of this circuit starts memory operation when CE is input, and Ain is amplified by AB to supply signals to X-Dec and Y-Dec. When one word line W is selected by X-Dec & Driv. According to this signal, the information charge accumulated in Cs in the memory cell is output to the data line. As a result, a small signal appears on the data line and is amplified by SA. The data line signal selected by Y-Dec & Driv. Is output. This signal is amplified by the MA and output to the outside as Dout. In the write operation, a signal is written to the memory cell by a path opposite to the above via the WC.

In the above configuration, control of various purposes is possible.

First, there is a control method that maintains a constant operation speed or reliability characteristics of the entire circuit, but this has been described in some embodiments. What is necessary is to output the signal suitable for a circuit to the control line 5, and to control each.

Next, a method of controlling according to the purpose for each circuit is considered. In particular, since the memory cell array portion is constructed using the finest element in a DRAM, the device breakdown voltage is low compared to the other, which tends to cause a problem of lowering reliability. Therefore, the control of the memory cell array portion for the purpose of high reliability and the stabilization of the other circuits with the operation speed is considered. The method of keeping the operation speed constant is good according to some already described embodiments. Several methods are considered for the control method of the memory cell array unit. First, there is a method of keeping the electric field of the insulating film thickness of Cs in the memory cell constant. In order to make the information charge Qs large and to operate stably, the larger the Cs is, the better is the thickness t _OXS of the insulating film as the dielectric material. This is because it is the lowest in the chip. In order to compensate for the reliability by keeping the electric field E _OXS constant, the output voltages of SAD, DP, WC, etc. may be controlled in accordance with the variation of the insulating film to control the voltage Vs written to Cs.

At this time, the information charge amount Qs is expressed as follows.

Where ε _OXS is the permittivity and A _OXS is the area of Cs.

Therefore, keeping E _OXS constant keeps Qs constant, improving reliability and stabilizing operation. In addition, since the leakage current in the diffusion layer in the MC increases as the temperature increases, the minimum amount of information charge necessary for the stable operation also needs to be increased. Therefore, there is also a control method in which the Qs, that is, E _OXS are increased to further improve reliability as the temperature increases. In this case, since the gm of the MOS transistor decreases with the temperature rise, it is possible to control the peak value of the data line charge / discharge current without increasing the peak value.

Next, there is a control method focusing on the MOS transistor of the memory cell. This is because the MOS transistor is the finest in the chip, and its breakdown breakdown voltage and hot carrier breakdown voltage are often lower than others. Various breakdown voltages of MOS transistors decrease as the gate length Lg is short and the gate insulating film thickness T _OX becomes thinner. Therefore, as the Lg becomes shorter and the gate insulating film thickness T _OX becomes thinner, the applied voltage of word lines, data lines, etc. may be reduced. The control of the applied voltage can be performed as described above. In addition, as described above, when the temperature decreases, the internal pressure of the hot carrier also decreases. Therefore, when the temperature decreases, the word line voltage, the data line voltage, and the like may be lowered. As a result, stable and highly reliable characteristics can be obtained. Moreover, it is also possible to combine the control method which focused on Cs mentioned above with the control method described here.

According to the embodiment described above, the operation of the DRAM can be controlled according to various purposes. As described above, in the DRAM, it is necessary to use a fine element in order to advance high integration. Although 5V is currently used as the power supply voltage Vcc, it is expected that it will be difficult to apply 5V directly to a micronized device in view of lowering the breakdown voltage of the device in the future to increase the integration into 4M and 16M bits. However, lowering Vcc below 5V is not preferable because it burdens the user in view of compatibility with conventional DRAM. Therefore, in the DRAM, various controls can be executed after the voltage is lower than Vcc by the control circuit to protect the microelements as shown in Figs.

Fig. 54 shows one embodiment of the control circuit including the power supply circuit as described above. In Figure 54 (5I ') to the address buffer, decoder, a clock driver such as the low voltage V _I than Vcc to a peripheral circuit of the "control line for supplying, (5I2) is a voltage higher than V _I, in the word driver V _CH The control lines for supplying the circuits (5I3H) and (5I3L) are the driving circuits SAD of the sense amplifier SA, It is a control line for controlling. In addition, although abbreviate | omitted here, of course, the control circuit 3 contains other necessary control circuits in FIG. Fig. 54 shows an address buffer, a decoder, a clock driver, and the like in accordance with a constant voltage generating circuit F, a bipolar transistor Q ₁₁₂ , a differential amplifier GD, a feedback circuit H, and a reference voltage V _I for generating a stable reference voltage suitable for aging test. low V _I 'comparator O for supplying the MOS transistor T _M141, again word driver such as V _I' than the operating trial high voltage generator for supplying a high voltage V _CH circuit HOP, air trial high voltage generating circuit HST and the data line voltage The driving circuits DRV and DRV ′ which control Vo and the data line charging current. According to this configuration, since V _I ′ is the same as V _I , and V _CH and V _O are also determined by V _I ′, all internal voltages in the DRAM can be controlled by V _I. Therefore, according to the above embodiment, the memory cell array and the peripheral circuits are less likely to receive characteristic changes due to variations in temperature and Vcc, thereby realizing a highly stable DRAM. It goes without saying that the aging test can be executed effectively. When the embodiments of Figs. 37 and 45 are used for the constant voltage circuit F of Fig. 54, the power consumption can be reduced as follows. In other words, in the constant voltage circuit F shown in Figs. 37 and 45, the output voltage V _I1 is determined by the ratio of the resistances as shown in equation (15). The aging voltage characteristic is also determined by the ratio of the resistances as shown in equation (20). For this reason, a characteristic does not change with the absolute value of a resistance, and it is rarely influenced by a manufacturing deviation. Therefore, by uniformly multiplying the absolute value of the resistance by Z times (Z> 0), only the current can be set to a desired value while the resistance ratio remains unchanged. If the current value is made small, in some cases it may be easily affected by noise from other circuits on the same semiconductor substrate. In this case, however, the semiconductor device including the reference voltage generating circuit F may be in an operating state. In this case, the current flowing through the reference voltage generating circuit F may be increased to prevent voltage fluctuations caused by noise or the like. In the standby state, the current may be reduced to reduce power consumption.

55 and 56 are specific embodiments therefor.

In FIG. 55, a pMOS transistor is provided between the electrostatic source terminal D of the reference voltage generating circuit F and the external power supply Vcc. In Fig. 56, an nMOS transistor is provided between the ground terminal of the reference voltage generating circuit F and the ground power supply. According to these embodiments, the current value of the reference voltage generation circuit F can be easily controlled by changing the gate voltage of the pMOS transistor T _M200 or the nMOS transistor T _M210 . For example, in the embodiment of Fig. 55, when the potential of the gate terminal 200 is lowered, the resistance value of the pMOS transistor T _M200 is lowered and the current flowing through the reference voltage generating circuit F increases. In addition, when the potential of the gate terminal 200 is increased, the resistance value of the pMOS transistor T _M200 is increased to decrease the current flowing through the reference voltage generating circuit F. FIG. Therefore, according to the embodiment of Fig. 55, when the semiconductor device including the reference voltage generating circuit F is in the operating state, the potential of the terminal 200 is lowered and the potential of the terminal 200 is increased when the semiconductor device is in the standby state. In this case, it is possible to prevent the voltage value from fluctuating due to noise and to reduce the power consumption during standby. Also in the embodiment of Fig. 56, the same effect can be obtained by increasing the potential of the terminal 210 during operation of the semiconductor device and lowering the potential of the terminal 210 during standby. Since the nMOS transistor is used in the embodiment of FIG. 56, a gate width smaller than that of the pMOS transistor in the embodiment of FIG. 55 can be used, so that the occupied area of the circuit can be reduced. 55 and 56, when the MOS transistor is inserted between the power supply and the reference voltage generator circuit F, the actual voltage applied to the reference voltage generator circuit is reduced by the resistance between the source and drain of the MOS transistor. However, since the output voltage V _I1 of the circuit of FIG. 37 or FIG. 45 does not depend on the power supply voltage and maintains a constant value as in Equation 15, the current can be controlled without changing the voltage characteristic.

As a driving circuit for an address buffer, decoder, clock driver, or the like which operates with the control line 5I 'of FIG. 54 as a power source, in the embodiment as shown in FIGS. 9 to 17, Vcc is set to V _I '. Do it. If necessary, V _CONT in FIGS. 7 and 8 may be set to V _I ′. 7 to 17, a logic circuit such as a NAND circuit used for a decoder or the like is omitted, but it can be easily realized by, for example, replacing the part of the DRIV by NAND in FIG. By the way, a Bi-CMOS circuit can be used where the load capacity is large, but in this case, when the withstand voltage of the bipolar transistor Q _N3 is sufficient in FIGS. 8 and 12, the collector may be left at Vcc. good. At this time, since the collector current is supplied from Vcc, most of the charging current flows from Vcc and V _I 'only needs to supply the base current. The collector potential does not affect the circuit characteristics at all if the bipolar transistor is not saturated, so that the supply current of V _I ′ can be reduced while maintaining the circuit characteristics stably. Thereby, V _I 'can be kept more stable. In the case of the first stage of the address buffer to which the external input signal is directly applied, if the amplitude of the external input signal is insufficient, the through current is large, and if the power of the portion is set to V _I ′, the current of V _I ′ increases and V _I It may become difficult to keep stable '. In that case, it is also possible to operate only the first stage with Vcc. Next, one embodiment for controlling charging and discharging of a data line in FIG. 57 will be described.

In a DRAM, charging and discharging of a pair of data lines by a well-known sense amplifier formed of pMOS and nMOS is performed in accordance with read information of a memory cell (such as a memory cell composed of one MOS transistor and one capacitor). At this time, the charge amount Qc accumulated in the capacitor of the memory cell becomes the product of the data line voltage V _DL and the capacitor Cs of the capacitor. In DRAM, it is preferable to keep the Qc stable in terms of reliability. Therefore, if the data line voltage V _DL can be made independent of the external power supply voltage Vcc and temperature, stable and reliable operation can be assured without depending on external conditions. At the same time, setting V _DL to a value lower than Vcc within a range that does not adversely affect operation can reduce power consumption. For example, in the latest megabit DRAM, it is necessary to simultaneously charge 1024 pairs of data lines at high speed. Since the total capacity of this data line reaches 500 to 1000 mA, the transient current becomes a problem, and the reduction of the transient current is also desirable. In addition, in order to reduce noise caused by charging and discharging of the data lines, it is preferable to perform charging and discharging of the data lines symmetrically.

This embodiment is the same way, and the voltage V _DL and at the same time eliminating the external power source voltage dependency and temperature dependency of V _DL lower than Vcc and V _I 'is controlled by the voltage conversion circuit above the voltage V _DL data lines consumption The above-mentioned transient current and noise are reduced by reducing electric power and controlling the speed of data line charge / discharge. The present embodiment will be described below. Charging of the data line is performed by the driving circuit DRV connected to the common line cl of flip-flop which is a sense amplifier formed including the pMOS.

In this embodiment, this driving circuit is characterized in that it is composed of a current mirror circuit and a comparator. The current mirror circuit is controlled by a kind of inverter consisting of transistors Q ₁ and Q ₂ . When Q ₂ is on and Q ₁ is off, a current mirror circuit is formed between Q ₃ and the constant current source (i / n) and the output drive transistor Q _D , and when Q ₂ is off and Q ₁ is on, Q _D Becomes off. When the current inlet of the current source in the mirror circuit is i / n, the gate width of the MOS transistor is w / n, and the gate width of Q _D is W, the on-current of Q _D becomes constant current i. Even if W or the gate length or the threshold voltage of the transistor changes due to variations in the manufacturing process, if i / n is kept constant, the driving current of Q _D is almost constant. Here, the constant current sources i / n and w / n are used to reduce the current consumption and to reduce the occupied area, and n should be larger.

The comparator compares the output voltage V _I ′ (for example, 4 V) and the output voltage Vo of the voltage conversion circuit. At V _I ′> Vo, the output of the comparator becomes a high voltage, and conversely, when V _I ′ <Vo, it is a low voltage.

The operation will be described under the above preparation.

In a conventional DRAM, during the precharge period, the data line pair is a so-called half precharge method in which the data line pair is set to almost 1/2 of the V _DL , so that the common driving line cℓ or all data line pairs are precharged to V _DL / 2 during the precharge period. . When a pulse is applied to the selected word line in this state, a minute differential read signal appears on each data pair line. This state is shown in FIG. 58 by Do, Representatively shown symmetrically. Thereafter, by the sense amplifier formed of the nMOS transistor and the pMOS transistor, the low voltage side is discharged to 0V and the high voltage side is charged to V _I '. Discharge is performed by the MOS transistor T _N2 . Only charging is described here. cℓ is driven by applying an input pulse ψ. When the input pulse ψ-one (high voltage input), the control circuit the output voltage of the AND is a high voltage, the gate voltage V _G of Q _D are the output voltage Vs of the constant current source, Q _D is the load at a constant current i Drive. As a result, the voltage Vo of the load rises at a constant speed at V _I ′ / 2, but when V _I ′ is exceeded, the comparator operates so that the output of the control circuit AND goes to a low voltage, Q ₁ turns on and Q ₂ turns off. Q _D is turned off and Vo is clamped to approximately V _I '. As a result, the data lines of each data line pair one is filled up with _'I V in / 2' V _I. About discharge When nMOS T _N3 ′ and T _{N2 form} a current mirror, the speed can be controlled like charging.

According to the embodiment described above, since the data line voltage V _DL can be made substantially the same as V _I ', the temperature dependency of the data line voltage V _DL can be set to 0 to eliminate the dependence of the external power supply voltage Vcc within a desired range. In addition, since the data line can be charged with almost constant current, the data line can be charged at high speed without increasing the transient current. By keeping io constant, the influence can be minimized even if there is a fluctuation in the power supply voltage or a manufacturing deviation. In addition, since the data line voltage is suppressed low, power consumption is also reduced. In addition, since the speed of data line charge and discharge can be made the same, noise can be reduced.

Next, an embodiment of the driving circuit of the word line will be described. In a DRAM, the voltage of the word line is approximately 2V higher than the voltage of the data line. If the voltage of the data line is 4 V, for example, the voltage of the word line is required to be approximately 6 V, and a means for boosting the word line to 5 V or more of the value of Vcc is required. For example, the circuit of FIG. 59 can be used as a circuit for driving a word line by V _H boosted to Vcc or more. The generation circuit of V _H will be described later.

First, the circuit operation of FIG. 59 will be described using the voltage waveform diagram of FIG. If E is at high potential and C is at high potential, then through nMOS T11 the potential of F becomes the potential of V _A -V _T11n . Next, when E becomes low, T12 (pMOS) turns on and the potential of F becomes V _H. As a result, T13 (pMOS) is turned off, T14 (nMOS) is turned on, bipolar transistor T15 is turned off, and T16 (nMOS) is turned on, and the output W becomes 0V. Furthermore, when F is increased to a high potential V _H, due to the potential of the A and C is V _A, no work to T11 are turned off because the leak current is lowered and the potential of F from the F to C. On the other hand, when E is at a high potential and C is at a low potential, T11 is on and F is at the same low potential as C. As a result, T13 is turned on, T14 and T16 are turned off so that the node G becomes V _H , and the output W is charged at high potential at high speed. The high potential of this output is V _H -V _BE . In this circuit, as shown by the dotted line in FIG. 60, if the period t _CE from C to the high potential V _A until E becomes the low potential is long, the high potential of F _stays briefly at V _A -V _T11n . As a result, there may be a period in which a through current flows through T13 and T14 so that W stays at an insufficient low potential. Therefore, it is desirable to shorten the time of t _CE . To do this, once C is at high potential, E can be switched to low at the same time. Thereby, the said problem can be solved.

According to this circuit, since a bipolar transistor is used for the output, the word line can be charged to V _H -V _BE at high speed.

In FIG. 59, G may be directly output without using the bipolar transistor T15. At this time, the output voltage is increased up to V _H, may occur if the same V _H and the desired word voltage. For this reason, the design of the power supply G becomes easier than when using a bipolar. In addition, the MOS transistor has the advantage of simplifying the manufacturing process. In the circuit of FIG. 59, the operation speed can be controlled by inserting a MOS transistor between the power supply as shown in FIG.

FIG. 61 is an embodiment of a circuit for obtaining a high voltage of Vcc or more based on the voltage V _I ', and FIG. 62 is an operation waveform diagram thereof. Hereinafter, the operation of the circuit of FIG. 61 will be described with reference to FIG. 62.

The circuit of FIG. This circuit boosts the V _CH terminal in synchronization with the signal. When the signal enters the low level and the DRAM enters the operating state, as shown in Fig. 62 _{,? 1PS} is at a low level _{,? 2PS} is at a high level, and? _1S and? _1SA are shifted to a high level. As a result, G1 and G2 of G1, G2, G3, and G4 precharged to the same potential as Vcc are boosted by MOS capacitors T _MC221 and T _MC222 . As a result, G1 through MOS transistors T _M229 and T _M22A . Current flows from G4 to G3, increasing the potential of G3 and G4. At this time, since G2 is boosted to Vcc or more, the potentials of G3 and G4 can be boosted without being limited to the threshold voltages of the MOS transistors T _M229 and T _M22A . Next, ψ _1S and ψ _1SA are lowered to low level, and ψ _2S and ψ _3S are shifted to high level. As a result, G1 and G2 transition to a low level and G3 and G4 are boosted. At this time, the potential of G2 becomes 0V when ψ _2S is at a high level, so the MOS transistor T _M22B is turned on, and the MOS transistor T _M22A is surely turned off. For this reason, the potential of G2 does not rise by the shift of the timing of (psi) _2S , coupling noise, etc. Thus, a current flows through _GMOS transistor T _M22C at G3 to boost 5I2. At this time, since six diodes are connected in series between the gate of MOS transistor G4 and 5I1 ', the potential of G4 is clamped to V _CL + 6V _BE . As a result, the voltage of V _H is _clamped to V _I '+ 6V _BE -V _T22C with the threshold voltage of the MOS transistor T _M22C as V _T22C . For example, if V _I 'is 4V, V _BE is _0.8V , and V _T22C is _0.8V , it is 8V. In this example, six diodes are used. However, by changing the number, it is possible to prevent V _H from exceeding a certain voltage for V _I ′. For example, in the case of connecting a word driver to V _H , the word line voltage Can be controlled to the desired value. Next, the DRAM When the signal becomes high, ψ _2S and ψ _3S are returned to the low level, ψ _{1PS is set} to high level and ψ _{2PS is set} to low level. As a result, the potential of the G5 and boosted by the MOS capacitor T _MC220, pMOS transistor T _M221 gate voltage of the MOS transistor T _M225, T _M226, T _M227, T _M228 through is boosted above Vcc, by these MOS transistors The potentials of G1, G2, G3, and G4 become Vcc and return to the initial state. In addition, where the MOS transistors _M223 T is to protect the _M224 T to prevent a high pressure is applied to the drain of T _M224. In addition, when diodes are used in series, V _BE has temperature dependency, and therefore V _H has temperature dependency. In order to solve this problem, the clamp circuit may be omitted with the amplitude of ψ _1S to ψ _3S being V _I ′ instead of Vcc.

At this time, in order to set the voltage of 5I2 to a desired value, a circuit as shown in FIG. 63 may be used. In FIG. 63, when V _CH ′ is maintained at a high voltage by a circuit as in FIG. 61, (5I2) The voltage of is output. As V _REF , V _I ′ may be used, or a voltage having temperature dependency that removes the temperature dependency of V _BE of bipolar transistor Q ₆₃₁ may be applied. As described above, according to this embodiment, a voltage higher than Vcc can be obtained at (5I2). In this embodiment Since the step-up in synchronism with the signal V _H for the operation of the DRAM, the low power consumption operation is possible without consuming power by the voltage step-up operation when the air does not have to supply a current from the V _H. However, depending on the DRAM usage conditions, the standby state may be continued for a long time, and the potential of V _H may be lowered due to some leakage. In this case, a circuit for compensating for leakage during standby may be separately provided. To this end, in the embodiments of Figs. 61 to 63, a smaller capacitor or a smaller transistor and a smaller current driving capability are separately provided. It may be operated independently. Alternatively, a circuit as shown in FIG. 64 may be used.

Hereinafter, the operation of the circuit of FIG. 64 will be described using FIG. 65. When the low level is _set , G ₂₄₀ , G ₂₄₁ and V _H are precharged to near Vcc by the MOS transistors T _M240 , T _M241 and T _M243 . Next, when ψ ₀ is raised to a high level, the outputs of the inverters I ₂₄₁ and I _{242 become} high level and low level, respectively. Thus, G ₂₄₀ is boosted above Vcc to flow a current to the G ₂₄₀ increases, the potential of G _240. Next, when ψ ₀ is set at the low level, the outputs of the inverters I ₂₄₁ and I ₂₄₂ are at the low level and the high level, respectively, so that the voltage G ₂₄₁ is further increased and current flows to V _H. As described above, the potential of V _H increases by periodically raising and lowering ψ ₀ . With the rise of V _H , the potentials of G ₂₄₆ and V _G246 also rise due to the diodes QD _{240 to} QD ₂₄₅ while maintaining the relationship of V _H -6V _BE . When the threshold voltage of the MOS transistor T _M246 is -V _T246 , when V _H becomes V _I ′ -V _T246 + 6V _BE or more, V _G246 becomes V _I ′ -V _T56 and T _M246 is turned off, and D ₂₄₇ The potential of becomes 0V by the MOS transistor T _M247 . As a result, the voltage of the output O ₅ of the NAND circuit NA240 is fixed at a high level and the boosting operation is stopped. After that, when the potential of V _H drops by the current I _H flowing out of the control line 5I2 and falls below V _I ′ -V _T246 + 6V _BE , T _M246 is turned on again to start the boost operation of V _H. do.

As described above, according to this circuit, the potential of V _H can be maintained at V _I ′ -V _T246 + 6V _BE higher than Vcc. If V _I ′ is 4V, V _T246 is 0.5V, and V _BE is 0.8V, V _H becomes 8.3V.

As described above, according to the present embodiment, by combining the charge pump circuit and the above-described level shift circuit, the output voltage V _H can be maintained at a constant voltage higher than Vcc.

It goes without saying that the number of diodes QD _{240 to} QD ₂₄₅ for clamping may be increased or decreased in some cases. In some cases, when the current flowing through the QD _{240 to the} QD ₂₄₅ is too large than the V _CH , the QD ₂₄₅ is a bipolar transistor and the collector and the base of Vcc are connected to the output of the QD ₂₄₄ as shown in FIG. 66. The current can be reduced by h _FE .

The number of diodes may be determined so that the difference between the voltages V _H and V _I ′ is a desired value. In addition, the MOS transistor T _M248 can be replaced with another element such as a resistor. In the case of using a MOS transistor, the gate length Lg is made large with respect to the gate width W, whereby a high resistance value can be easily obtained with a relatively small occupation area. In this example, a pn junction diode is assumed as the diode. A pn junction diode can be easily realized by, for example, connecting a base and a collector of a bipolar transistor. For this reason, it can form simultaneously with a bipolar transistor, and can simplify a manufacturing process. At this time, if the resistance is also realized using the base layer of the bipolar transistor, the process can be further simplified. pn junction diode forward voltage V _BE is usually 0. 8V, so much, the difference in the voltage V _H and V _H 'in Example 65, but may take only one value of a 0. 8V as a unit, in some cases _H and V In some cases, it is necessary to set the difference of V _I ′ other than n times (n = 1, 2, ...) of 0.8V. In this case, if a Schottky diode with a forward voltage V _F of about 0.4 V is used,

V _H = V _I ′ -V _T246 + iV _F

The value of V _H can be set in units of 0.4 V. In addition, of course, an nMOS diode as shown in Fig. 67 may be used. In this case, the threshold voltage of the nMOS T _MA is set to V _TMA .

V _H = V _I ′ -V _T246 + iV _TMA

Therefore, the potential difference can be varied in units of V _TMA . In addition, a circuit as shown in FIG. 68 may be used in place of the diode to create an arbitrary potential difference. In FIG. 68, the potential difference between the terminals 3A and 3B is

Therefore, the potential difference can be changed continuously by changing the ratio of R _A and R _B. Various other modifications are possible, but the embodiment shown in Fig. 69 configures the level shift circuit L in Fig. 69 only with nMOS. In this embodiment, the clamp diode is an nMOS diode, and the bipolar transistor Q ₁ and the resistor R are replaced with nMOS T _M51 and T _M52 , respectively. Relationship of V _H and V _I 'in this embodiment by the threshold voltage of the threshold voltage of _M51 T V _TM51, MOS diode to V _TD

V _H = V _I ′ -V _T246 + V _TM51 + nV _TD

The potential difference can be set in units of the threshold voltage V _TD . In this embodiment, nMOS diode T _MD51 ~T current flowing through the _MD5i need not be made larger than necessary, the current supply capability of the nMOS T because the bias current I _N flows through only the _M53 (5I2). In addition, in this embodiment, since it is not necessary to use a bipolar transistor and consists only of a MOS transistor, it is suitable to apply to LSI which consists only of a MOS transistor. The gate voltage, gate length, and gate width of the MOS transistors T _M51 and T _M53 may be determined so that the currents I _R and I _N become desired values. For example, if the value of I _R is set to 10 times with respect to I _L , the fluctuation in the drain current of the MOS transistor T _M51 can be suppressed to about 10%, and V _L can be maintained almost constant. In the above embodiment, when the temperature characteristic of the clamp circuit becomes a problem, the temperature dependence of the clamp can be compensated by giving temperature dependence to the source voltage of the MOS transistor T _M246 .

As described above, the present invention can be applied to not only DRAM but also SRAM. 70 shows an example of an SRAM in which a memory cell is formed using an nMOS transistor and a resistor. In Fig. 70, the above-described control is also performed on the drive circuit and the differential amplifier used for the peripheral circuit, thereby achieving stable and reliable operation. In addition, if the voltage applied to the load resistors R _C1 and R _C2 of the memory cells is supplied from the voltage conversion circuit of the present invention instead of Vcc, the temperature dependence and the external power supply voltage dependency of the memory cell characteristics can be eliminated. Very stable memory operation can be realized. At this time, since the current supplied from R _C1 and R _C2 , that is, the holding current of the memory cell is very small and almost constant DC current, it is easy to keep the voltage constant and accurate. In addition, the data line DL, The stability of the voltage, i.e., the voltage of the write voltage or the word line W, is improved more stably. For that purpose, if the write voltage is determined according to the voltage V _I obtained by the present invention, the temperature dependence and the external voltage dependence can be eliminated, and the reliability can be further improved.

The present invention also applies to logical LSIs other than memory. In FIG. 53, the control circuit detects the characteristics of the peripheral circuit by the control line 6, but the detection can be performed in various places depending on the purpose. For example, the time until the word line is applied to amplify the sense amplifier microsignal is detected, and according to the result, various control such as changing the driving voltage and driving current of the SA to control the operation characteristics of the array unit. There is also a way. Although the main components have been described using MOS transistors and bipolar transistors as examples, the principles of the present invention can be applied as it is to other elements composed of compound semiconductors such as GaAs. Moreover, although the element constant of a MOS transistor was mainly adopted as a factor of a characteristic change, it cannot be overemphasized that the fluctuation | variation of the current amplification ratio, a cutoff frequency, a forward voltage, etc. of a bipolar transistor can also be handled similarly. In addition, in each embodiment, the main purpose is to keep all the characteristics constant. However, according to the present invention, for example, variations in the manufacturing conditions such as gate length and threshold voltage, use of power supply voltage, temperature, etc. may be used. In the case where the fluctuation of the condition causes the semiconductor device to be made high speed, the control may be made faster than that. Alternatively, the condition may be controlled to be made slower when the manufacturing condition and the use condition are changed to make the semiconductor device low speed. In addition, although the above-described embodiment has been described based on the TTL interface, of course, the same applies to other cases such as ECL.

As described above, according to the present invention, a stable and highly reliable semiconductor device can be realized even if there are variations in manufacturing conditions and use conditions. In addition, at the same time, the yield of good products can be maintained at the time of mass production, and therefore, it can be manufactured at a lower cost than a conventional semiconductor device.

As mentioned above, although the invention made by this inventor was demonstrated concretely according to the said Example, this invention is not limited to the said Example, Of course, a various change is possible in the range which does not deviate from the summary.

Claims (33)

Several dynamic memory cells connected to predetermined intersections of several word lines and multiple data line pairs, A plurality of word line driver circuits provided corresponding to each of the plurality of word lines; A voltage generation circuit supplied with an operating voltage and generating a first voltage greater than the operating voltage, The word line driver circuit selected in accordance with the selection signal drives one of the word lines to the first voltage by forming a current path between one of the word lines at an unselected potential and the output of the voltage generator circuit, The voltage generating circuit may include a boosting circuit generating the first voltage greater than the operating voltage at the operating voltage according to a charge pump operation according to a pulse signal supplied to the voltage generating circuit, and the first voltage output by the boosting circuit. And a control circuit for controlling the charge pump operation of the boosting circuit with reference to the level of. The method of claim 1, And the voltage generating circuit outputs the first voltage in any of a period in which the plurality of word lines are in an unselected potential and a period in which one of the plurality of word lines is selected. The method of claim 2, And a period in which one of the plurality of word lines is selected is larger than a period in which the plurality of word lines are in the non-selective potential. The method of claim 1, Each of the plurality of word line driver circuits includes a P-type MOS transistor, The word line driver circuit selected in accordance with the selection signal has a current path between one of the word lines at an unselected potential and the output of the voltage generation circuit due to the conduction of the P-type MOS transistor included in the word line driver circuit. Forming a semiconductor device. The method of claim 4, wherein The voltage generating circuit outputs the first voltage in either the period in which the plurality of word lines are in the non-selective potential and in the period in which one of the plurality of word lines is selected, The first voltage is supplied to a gate of a P-type MOS transistor included in the unselected word line driver circuit, And the P-type MOS transistor included in the selected word line driver circuit supplies the first voltage to the corresponding word line via its source-drain path. The method of claim 5, And a period in which one of the plurality of word lines is selected is larger than a period in which the plurality of word lines are in the non-selective potential. The method of claim 6, The semiconductor device further includes a plurality of sense amplifiers and a plurality of precharge circuits provided corresponding to the plurality of data line pairs. The sense amplifier amplifies the voltage between the corresponding pair of data lines to a second voltage when a signal from the dynamic memory cell is read into the corresponding pair of data lines, The first voltage is greater than the second voltage, And the plurality of precharge circuits precharge the plurality of data line pairs to a voltage of about one half of a second voltage when the plurality of data line pairs are unselected. The method of claim 1, The semiconductor device further includes a plurality of sense amplifiers provided corresponding to the plurality of data line pairs. The sense amplifier amplifies the voltage between the corresponding pair of data lines to a second voltage when a signal from the dynamic memory cell is read into the corresponding pair of data lines, And the first voltage is greater than the second voltage. The method of claim 8, The semiconductor device further includes a plurality of precharge circuits provided corresponding to the plurality of data line pairs. And the plurality of precharge circuits precharge the plurality of data line pairs to a voltage of about one half of the second voltage when the plurality of data line pairs are unselected. The method of claim 1, And the voltage generating circuit further comprises a second boosting circuit for generating the first voltage at the operating voltage. The method of claim 10, And a period in which one of the plurality of word lines is selected is larger than a period in which the plurality of word lines are in the non-selective potential. The method of claim 11, And said second boost circuit is operable in response to a signal instructing access to said plurality of dynamic memory cells. The method of claim 1, And the voltage generating circuit further comprises a voltage clamp circuit for maintaining its output at a predetermined voltage. The method of claim 13, The voltage clamp circuit includes a circuit in which a plurality of diode-connected MOS transistors are connected in series. Several dynamic memory cells connected to predetermined intersections of several word lines and multiple data line pairs, A plurality of word line driver circuits provided corresponding to each of the plurality of word lines, A plurality of sense amplifiers provided corresponding to each of the plurality of data line pairs, A first voltage generating circuit for generating a first voltage smaller than an operating voltage; A second voltage generating circuit generating a second voltage greater than the first voltage, The word line driver circuit selected according to the selection signal drives one of the word lines to the second voltage by forming a current path between one of the word lines at an unselected potential and the output of the second voltage generator circuit. , And the sense amplifier amplifies the voltage between the pair of data lines corresponding to the first voltage when a signal read from the dynamic memory cell is read to the pair of data lines. The method of claim 15, And the second voltage generating circuit outputs the second voltage in any of the periods in which the plurality of word lines are in an unselected potential and a period in which one of the plurality of word lines is selected. The method of claim 16, A semiconductor device in which the supply capability of the output current of the second voltage generating circuit for outputting the second voltage is larger than a period in which one of the plurality of word lines is selected than the period in which the plurality of word lines are in an unselected potential. . The method of claim 15, Each of the plurality of word line driver circuits includes a P-type MOS transistor, The word line driver circuit selected in accordance with the selection signal is connected to the P-type MOS transistor included in the selected word line driver circuit so that one of the word lines at an unselected potential and the output of the second voltage generator circuit are connected. A semiconductor device forming a current path therebetween. The method of claim 18, The second voltage generating circuit outputs the second voltage in any of the periods in which the plurality of word lines are in an unselected potential and a period in which one of the plurality of word lines is selected, The second voltage is supplied to a gate of the P-type MOS transistor included in the unselected word line driver circuit. And the second voltage is supplied to the corresponding word line via a source-drain path of the P-type MOS transistor included in the selected word line driver circuit. The method of claim 19, A semiconductor device in which the supply capability of the output current of the second voltage generating circuit for outputting the second voltage is larger than a period in which one of the plurality of word lines is selected than the period in which the plurality of word lines are in an unselected potential. . The method of claim 15, The semiconductor device further includes a plurality of precharge circuits provided corresponding to the plurality of data line pairs. And the plurality of precharge circuits precharge the plurality of data line pairs to a voltage of about one half of the first voltage when the plurality of data line pairs are unselected. The method of claim 15, The second voltage generating circuit outputs the boosting circuit and the boosting circuit for generating the second voltage greater than the operating voltage at the operating voltage according to the charge pump operation according to the pulse signal supplied to the second voltage generating circuit. And a control circuit for controlling the charge pump operation of the boosting circuit with reference to the level of the second voltage. The method of claim 15, And the second voltage generating circuit further comprises a first boosting circuit and a second boosting circuit for generating the second voltage at the operating voltage, respectively. The method of claim 23, wherein A semiconductor device in which the supply capability of the output current of the second voltage generating circuit for outputting the second voltage is larger than a period in which one of the plurality of word lines is selected than the period in which the plurality of word lines are in an unselected potential. . The method of claim 24, The first boosting circuit is operable in any of a period in which the plurality of word lines are in an unselected potential and a period in which one of the plurality of word lines is selected, And said second boost circuit is operable in a period during which one of said plurality of word lines is selected. The method of claim 25, And said second boost circuit is operable in response to a signal instructing access to said plurality of dynamic memory cells. The method of claim 15, And said second voltage generating circuit further comprises a voltage clamp circuit for maintaining its output at a predetermined potential. The method of claim 27, The voltage clamp circuit includes a circuit in which a plurality of diode-connected MOS transistors are connected in series. The method of claim 12, And the signal indicating the access is a low address strobe signal. The method of claim 26, And the signal indicating the access is a low address strobe signal. (Correction) The method according to any one of claims 15 to 28, The operating voltage is an external power supply voltage supplied from the outside of the semiconductor device. And the second voltage is greater than the operating voltage. (Correction) The method according to any one of claims 1 to 14, And said semiconductor device is a dynamic RAM. (New) The method according to any one of claims 15 to 28, And said semiconductor device is a dynamic RAM.