KR100518096B1 - Control gate driver circuit for nonvolatile memory and memory using it - Google Patents

Abstract

The nonvolatile memory control circuit of the present invention receives an erase voltage, a positive program voltage, and a negative program supply. The control circuit generates a bias voltage through the bias circuit. During the program cycle for the selected memory cell, a negative program supply is provided to the control gate line. During the program cycle for an unselected memory cell, a positive program voltage is supplied to the control gate line. The bias voltage is supplied to the control gate line during the erase cycle for the selected memory cell.

In order to provide a method for improving drain disturbance problems and band-to-band leakage of a nonvolatile memory array, the present invention modifies how the memory array is operated rather than modifying the physical design of the memory array.

In the present invention, since only the operation of the nonvolatile memory array changes, there is no need to change the layout of the memory array or to change the design for each memory cell structure.

Description

Control Gate Driver Circuit for Nonvolatile Memory and Memory Using the Same

Field of invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to non-volatile memory control circuits, and more particularly to non-volatile memory control circuits that provide positive and negative voltages to control gates of memory cells.

Background of the Invention

An electrically erasable and programmable read only memory (EEPROM) is a nonvolatile memory device that is erased and programmed using an electrical signal. EEPROM devices typically include thousands of memory cells, each of which can be individually programmed and erased. In general, an EEPROM cell includes a floating gate transistor and a select transistor. Select transistors in the EEPROM are used to select each EEPROM cell to be erased or programmed. The floating gate transistor in the device is actually a transistor that stores the digital value of each particular memory cell.

For programming and erasing cells, a phenomenon known as Fowler-Nordheim tunneling is commonly used to store positive or negative charges in the floating gate electrodes of floating gate transistors. For example, programming is accomplished by applying a positive voltage to the drain and gate of the select gate transistor while keeping the control gate of the floating gate transistor at ground. As a result, the electron tunnel from the floating gate of the floating gate transistor leaves the floating gate positively charged through the tunnel dielectric to the drain.

One particular configuration of an EEPROM is a flash EEPROM. Flash EEPROMs provide the ability to be electrically erased and programmed and generally have increased circuit density. This increased circuit density is typically achieved at the expense of only being able to block erase the flash EEPROM array. Typically the array is erased in a single step or one flash operation, so it is called a flash EEPROM.

Charge pumps are commonly used to generate the high voltages needed to program and erase the flash EEPROM. The use of charge pumps in applications requiring low power supply voltages is an important issue because lower operating voltage applications are more widely used. However, when the operating voltage drops, charge pumps that can be operated at this voltage are more difficult to design. Currently, the flash EEPROM is operated down to a voltage of approximately 2.7V. Flash EEPROMs operating below 2.7V are highly desirable, but are not currently commercially available. Prior art charge pumps typically have a linear charge pump stage that generates an increased voltage. The linear charge pump includes a number of stages, each stage of which can generally charge a previously generated or available voltage by a limited amount with approximately a positive voltage supply rail Vdd. For example, if three such charge pump stages are used and Vdd is 3V, then the total output voltage four times Vdd is the total available output voltage without providing loading. The inconvenience of using a linear charge pump is that the area efficiency is relatively low. Area efficiency is defined as the total space taken to implement a charge pump compared to the amount of current the implemented charge pump has available at the generated voltage. Therefore, there is a need in the prior art for an efficient charge pump of increased area.

Since the erase and program states of the cell are determined by applying a large voltage to the control gate, it becomes difficult to design a driver circuit that can operate in this voltage range. For example, as the integrated circuit topography is reduced, the high voltage applied between the gate and the source or the drain of the transistor in the driving circuit itself causes reliability problems. In addition, since it is necessary to apply another high voltage, it is difficult to carry out with a small amount of circuit area.

Integrated circuit EEPROM devices are typically implemented in a complementary metal oxide semiconductor (CMOS) technology. Using CMOS technology, transistors of a predetermined conductivity type are generally formed in a substrate, and if a transistor of the opposite conductivity type is desired, an area known as a well or a tub must be formed in the substrate and the well or tube The transistors are sequentially formed in the. However, exposure to such very high voltages can damage parasitic diodes between the well and the substrate. When exposed to a negative voltage, the parasitic diode is forward biased.

For example, if an integrated circuit EPROM is formed on a P-type substrate, a normal N-channel transistor can be formed directly on the substrate, while a P-channel transistor requires an N-type well. However, if an N-channel transistor is formed directly on the substrate, the parasitic PN diode is forward biased upon exposure to a negative program or erase voltage. Thus, the N-channel transistors need to be placed in the P-well and further in the N-well. Such well structures increase the integrated circuit area and are generally undesirable. Thus, there is a need to provide a control gate driver circuit that accumulates widely different voltages but does so with minimal circuit area.

Detailed description of the drawings

In the present invention, the control circuit receives an erase voltage, a positive program voltage and a negative program supply. The control circuit generates a bias voltage through the bias circuit. During the program cycle for the selected memory cell, a negative program supply is provided to the control gate line. During the program cycle for an unselected memory cell, a positive program voltage is supplied to the control gate line. The bias voltage is supplied to the control gate line during the erase cycle for the selected memory cell.

The present invention provides a method for improving drain disturb problems and interband leakage of a nonvolatile memory array. In order to solve these problems, previously known devices modify the placement of memory cells or adjust each memory cell or structure within an array. However, the present invention modifies how the memory array is operated rather than modifying the physical design of the memory array.

Since only the operation of the nonvolatile memory array is changed, there is no need to pay a cost to change the arrangement of the memory array or to change the design for each memory cell structure. The present invention does not involve modifications to the memory array, and therefore is not limited to specific EEPROM cell structures. This allows the program and read techniques of the present invention to be used with various nonvolatile memory array structures.

1, a detailed description of a method of programming a nonvolatile memory cell in accordance with the present invention is provided. 1 shows a memory array 25 each consisting of each memory cell having an isolation transistor and a floating gate transistor. 1 is provided to illustrate the configuration of a nonvolatile memory array, and it is to be understood that the present invention is not limited to the number of memory cells in memory array 25 or such an exact configuration. One of many features of the present invention is that the following operating techniques are compatible with memory cells of various sizes and configurations.

In this particular example, the memory array 25 is arranged such that each row has two rows of memory cells with four cells. The dashed box is used to identify the elements of two specific memory cells in the memory array 25. For the following discussion, memory array 25 includes selected memory cells 10 and unselected memory cells 30. The selected memory cell 10 refers to the memory cell to be programmed, erased or read, and the unselected memory cell 30 is not enabled and is adjacent to the memory array 25 which is potentially affected by drain disturbance. Call the cell.

Each memory cell in the memory array 25 is enabled by a control gate line, an insulating gate line, a source line, and a drain line. All of these signal lines provide the necessary voltages for the appropriate portions of each memory cell during operation of the memory array 25. As described above, embodiments of the present invention are not limited to any particular memory cell configuration. However, for convenience, a specific memory cell structure is provided as an example of a memory cell that can be used in the memory array 25. 2 is an enlarged cross-sectional view of a memory cell 10 that may be used to implement each memory cell location.

As shown in FIG. 2, the memory cell 10 includes two transistors, an insulating transistor 22 and a floating gate transistor 23. The structure and fabrication of memory cell 10 is described in US Pat. No. 5,471,422, incorporated herein by reference and issued to Chang on November 28, 1995. Isolation transistor 22 has a gate terminal 19 which is used to modulate the channel between source terminal 12 and drain terminal 13. The floating gate transistor has a gate terminal 21 electrically insulated from the floating gate structure 18 by a dielectric material 17, the gate terminal 21 having a channel between the source terminal 13 and the drain terminal 14. It is used as a control gate to modulate. Note that the drain terminal 13 of the insulating transistor 22 also acts as the source terminal of the floating gate transistor 23. Transistors 22 and 23 are both formed on common dielectric layer 16 providing electrical isolation between substrate 11 and gate terminal 19 and floating gate structure 18.

Previously known nonvolatile memory arrays typically include memory cells comprised of a single floating gate transistor that stores the logic state of each memory cell. Such memory arrays are generally configured such that the drain voltages of all transistors in a particular column are shared and the gate voltage is shared by all transistors in a common row. To program each memory cell, a negative voltage is applied to the gate terminal, a source line is grounded, and a positive voltage is applied to the drain line. In an array configuration, only the selected floating gate transistor has a negative voltage on the gate and a positive voltage on the drain, thus creating a large voltage difference to facilitate programming. However, it is already known that other floating gate transistors in the same column as the memory cell being programmed also have a positive voltage on the drain. However, the unselected memory cells do not have a negative voltage applied to the gate terminal. Therefore, it does not have a voltage difference as large as that of the memory cell being programmed, but a voltage difference large enough to continue to cause drain disturb problem.

The programming technique of the present invention solves this drawback of the previously known memory array by reducing the voltage difference given to all unselected memory cells. Referring again to FIG. 1 for the following example, the selected memory cell 10 is programmed while the unselected memory cell 30 is left unobstructed. Note that most signal lines are used to provide a voltage potential to this structure and are therefore intentionally identified by a structural element number as used in FIG. In order to program the memory cell 10 selected according to the present invention, a negative voltage of about -5V to -15V is applied to the gate terminal 21 which is the control gate line. The drain line 14 is used to apply a positive voltage of about 0.1V to 10V to the drain terminal 14 of the floating gate transistor 23. The insulated gate line 19 is typically grounded to 0V or has a voltage low enough to turn the isolation transistor 22 OFF. The source line 12 shared by both the selected memory cell 10 and the non-selected memory cell 30 has a voltage potential of about -5V to 5V.

Now, the present invention differs from the prior art by applying different voltages to the terminals of the unselected memory cells 30 when the selected memory cells 10 are being programmed and verified. Instead of grounding the gate terminal of the unselected transistor, a voltage of about 0.1V to 10V is applied to the unselected memory cell 30 using the control gate line 32. Since the voltage potential at the gate terminal 32 is about 0.1V to 20V higher than that at the gate terminal 21, the problem of drain interference in the unselected memory cell 30 is greatly improved. As in the prior art, a positive voltage is applied to the gate terminal of the unselected gate as opposed to ground, so that the vertical field is significantly reduced along the drain terminal of the unselected gate.

It should also be pointed out that the programming techniques of the present invention cannot be used with previously known memory arrays having a single floating gate transistor in each memory cell. Since these previously known memory cells do not have isolation transistors, a single floating gate transistor is exposed to all voltages given to the memory array. If a positive voltage is applied to the gate terminal of an unselected memory cell, the voltage induces a channel between the source and the drain of all floating gate transistors. This current flow not only consumes a lot of power, but also allows unselected transistors to be programmed due to hot carrier injection (HCI).

The programming technique of the present invention not only protects unselected memory cells from drain disturbance issues, but also reduces the amount of current flowing from the charge pump. By reducing the vertical electric field at the drain terminals of all unselected memory cells, the amount of current delivered from the substrate to the drain terminals is significantly reduced. This actually reduces the amount of current required to be provided by the charge pump during the program sequence. Therefore, the present invention allows a nonvolatile memory array to be designed using a small charge pump that reduces the final fabrication cost of the memory array.

The present invention also provides an improved technique for reading the memory array 25 once the selected memory cell 10 is programmed. In order to read the value stored in the selected memory cell 10, a voltage of about 0.1 V to 5 V is placed on the drain line 14 and the control gate line 21. The power supply voltage Vdd is placed on the insulated gate line 19, and the source line 12 is grounded. Once the voltage is set, the current through the floating gate transistor 23 is measured to determine the state of the memory cell 10.

The previously known read technique commonly grounds the gate terminal of a memory location that is not selected during a read operation. There is some limited amount of leakage current through each memory cell even at ground potential. In large array configurations, this parasitic leakage increases the power consumption of the read operation. However, the present invention places a known voltage level at the isolation transistor gate terminal of an unselected memory cell to ensure that such memory cell is not conductive. For example, the insulating gate line 31 is grounded to prevent the non-selected memory cell 30 from being conductive. This not only reduces the amount of current required by the charge pump, but also reduces power consumption of the memory array 25. This feature of the present invention allows the control gate of an unselected memory location to be at any voltage potential. Unselected memory locations are electrically isolated by the isolation transistors and therefore do not contribute to leakage current.

3 is provided to illustrate a particular set of conditions for both selected and unselected memory cells during program, erase, and read operations. Note that this particular example is within the scope provided by the present invention and should not be considered as limiting FIG. 3 in any way when determining the boundaries of the applicant's invention.

4 illustrates a memory module 400 in accordance with the present invention in partial block diagram and partial plan view form. The memory module 400 generally includes a control and preliminary decoding unit 410, a low voltage word decoding unit 420 and 460, a high voltage word decoding unit 430 and 470, a high voltage preliminary decoding unit 432 and 472, and a bit cell array. 440 and 480, and also includes a sense amplifier unit 450. The control and preliminary decoding section 410 is an input for receiving address and control information called "address / control", a bidirectional terminal for conducting a signal called "data", and also a low voltage word decoding section 420, 460. And an output connected to the high voltage preliminary decoding unit 432 and 472 and the sense amplifier 450. The low voltage word decoding units 420 and 460 have outputs connected to the bit cell array 440 and the bit cell array 480 so as to provide a signal to the selection gate of the transistor in the bit cell arrays 440 and 480. The high voltage preliminary decoding units 432 and 472 have outputs connected to the high voltage word decoding unit 430 and the high voltage word decoding unit 470, respectively. The high voltage word decoder 430 and the high voltage word decoder 470 are connected to the bit cell arrays 440 and 480.

The memory module 400 is a flash EEPROM memory array having a bit cell array 440 on the left half and a bit cell array 480 on the right half. Each bit cell array includes memory cells located at the intersections of rows represented by both control gate lines and selection gate lines, and columns represented by bit lines. The bit line is connected to the input of the corresponding sense amplifier section 450 to select eight columns. During the read mode, the sense amplifier unit 450 senses a signal from eight selected bit lines, provides the sensed signal to the control and preliminary decoding unit 410, and outputs DATA in response. During the program mode, DATA is passed through the control and preliminary decoding section 410 to the sense amplifier section 450 and driven with eight selected bit lines for programming to the corresponding memory cell. Since two representative memory cells 10 and 30 that are identical to the memory cell of FIG. 1 are described in FIG. 4, the same reference numerals are designated. Note that in this description, the terms "select gate" and "insulated gate" are used interchangeably. The drain terminal 14 and the drain terminal of another memory cell positioned in the same column are connected to a bit line connected to the sense amplifier unit 450. The bit cell current, commonly referred to as " IBIT, " indicated in the direction of flow to the selected memory cell, is associated with the read cycle, which is useful for understanding the operation of the read cycle in more detail later.

In the described embodiment, memory module 400 is a module applied for connection to a microcontroller core that is part of a microcontroller (not shown). However, it is apparent that the memory module 400 may also be applied as being a single chip flash memory. The control and preliminary decoding block 410 is adapted to be connected to the internal bus of the microcontroller, and includes a bidirectional connection to the data portion of the internal bus of the microcontroller and the input receiving therefrom. DATA may include any number of signals depending on the organization of memory module 400, but in the described embodiment includes eight data signals.

The control and preliminary decoding block 410 performs several functions. The control and preliminary decoding unit 410 includes various registers for enabling other operations of the memory module 400. Such operations include, but are not limited to, charge pump enable, write enable, and erase enable. In addition, the control and preliminary decoding block 410 includes logic to perform some of the decoding functions required to receive the address / control and decode the address entirely. The control and preliminary decoding block 410 also includes a switching function for routing various power signals including voltages associated with the charge pump 1120, which will be described later in FIG. 11. In response to the read or program cycle, the control and preliminary decoding block 410 provides the predecoded address to the low voltage word decoding blocks 420 and 460 for further decoding. Additional decoding is further performed such that the fully decoded select gate drive signal can be output therefrom.

In addition, the low voltage word decoding blocks 420 and 460 provide the predecoded signals to the high voltage word decoding blocks 430 and 470 across the bit cell arrays 440 and 480. For example, FIG. 4 illustrates an example signal referred to as a " predecoded signal " that the low voltage word decoder 420 provides to the high voltage word decoder 430 across the bit cell array 440. As shown in FIG. By separating the low and high voltage decoders between the two ends of the array and transmitting the predecoded signals on signal lines fixed in the available gaps of the memory cells in the array, memory 400 reduces the circuit area required for decoding.

High voltage preliminary decoding blocks 432 and 472 provide high voltage signals for use in high voltage word decoding blocks 430 and 470, respectively. Each of the high voltage preliminary decoding blocks 432 and 472 receives three input power supply voltages including + 5V, + 15V, and -12V, and additionally receives a portion of an address and various control signals. The high voltage preliminary decoding blocks 432 and 472 responsively provide the high voltage predecoded address signals to the high voltage word decoding blocks 430 and 470, respectively. The high voltage word decoding blocks 430 and 470 receive predecoded signals from both the high voltage word decoding blocks 420 and 460 and the high voltage preliminary decoding blocks 432 and 472 to actually drive the transistor control gates in the selected row. . The control gate is driven to an appropriate voltage as described with reference to FIG. 3 above.

Each bit cell array 440, 480 includes each bit cell located at a unique intersection of a word line and a bit line within each half portion of the memory module 400. For example, the bit cell arrays 440 and 480 are organized into 256 word lines versus 512 bit lines, respectively. Note that a unique control and select gate signal is used for each word line. Each of the 512 bit lines provides a bit line signal to the sense amplifier unit 450. Each pair of bitcells corresponding to the memory cells 10 and 30 in FIG. 1 is shown in the bit cell array 440 and is indicated by the same reference numerals.

The sense amplifier section 450 includes 64 sense amplifiers and has a bidirectional connection to the control and preliminary decoding section 410. Each of the 64 sense amplifiers is connected to eight bit lines and performs an eight-to-one multiplex function during the read mode based on the decoding information from the preliminary decoding unit 410. Note that one to eight demultiplex functions occur during program or erase mode. The eight multiplexed outputs from the 64 sense amplifiers are further selected to provide an 8-bit output. In accordance with one aspect of the invention, some of the sense amplifiers are further used to store data during program cycles, saving integrated circuit area, as will be described in more detail below with reference to FIG.

During the read cycle, the control and preliminary decoding block 410 receives an input address and a control signal that specifies the read cycle. During that cycle, the control and preliminary decoding block 410 determines whether a byte of memory cells is selected from the left or right half array so that only array 440 or array 480 is active. During the read cycle, the control gates of all memory cells are kept at a constant voltage level. In the embodiment described, this constant level is equal to the supply voltage referred to as "V _SS " + the P-channel threshold indicated by "V _TP " + a small additional voltage of approximately 200 nV. V _SS is a slightly negative or grounded supply power voltage terminal with a nominal value of approximately 0V. In an unselected memory cell, the insulated gate is held at 0 V, while in the selected memory cell the insulated gate is driven to the value of the power supply voltage terminal, referred to as " V _DD . V _DD is a slightly positive power supply voltage terminal with a nominal value of 2.7V, but its actual value can be lowered to approximately 1.8V according to the present invention. This voltage selects one word line of the bit cell array. For example, when the word line where the memory cell 10 is present is selected, the selection gate 1 "SGI" is driven at a voltage of V _DD and the control gate 1 "CG1" is maintained at a constant level. As a result, the conductance of the memory cell 10 is operated to discharge the bit line 14. However, when the control gate CG2 of the memory cell 30 is maintained at a constant DC level, the isolation gate is driven to approximately 0V.

During the program cycle known as the write cycle, the control and preliminary decoding block 410 receives an address and control signal indicating that the write cycle is in progress and provides the decoded address signal as in the read cycle. However, the data flow is reversed during the recording cycle. A sense amplifier in the sense amplifier section 450 performs additional functions by latching input data and driving the input data to the selected bit line. During the write cycle, the memory cell on the selected word line has an isolation gate driven at 0V and a control gate driven at -12V by the appropriate high voltage word decoding block 430 or 470. However, the memory cell on the unselected word line has an isolation gate driven at 0V and a control gate insulated at 3.5V. Note that the voltage of 3.5V is obtained by reducing the 5V charge pump by an amount equal to the N-channel transistor threshold "V _TN " of the appropriately sized N-channel transistor. During the read cycle, the isolation gate voltage determines whether the memory cell 10 is on the active word line, while in the program mode the control gate voltage determines whether the cell 10 is on the active word line.

During the erase cycle, the selected word line, that is, the selected block of the word lines or the entire bit cell array is erased. Note that the option selection for erasing varies from one embodiment to the next. During the erase cycle, the voltage driven to the control gate determines whether the memory cells in the selected word line are erased. The memory cell in the selected word line has a control gate driven at 15V by the high voltage word decoding block 430 or 470 for a sufficient amount of time. Note that 15 V applied to the control gate of the memory cell at the selected word line should be maintained for approximately 50 ms. In memory modules 400 adapted to be used with the microcontroller core, 50 ms is determined by the microcontroller core to ensure that the memory module 400 is not accessed until this time has elapsed. However, when memory module 400 is implemented as a standalone memory, it is desirable to include a on-chip timer that measures the time elapsed during the erase mode. During the erase mode, the isolation gate of the selected word line is driven to a voltage of V _DD . In addition, during the erase mode, all bit lines are held at a voltage of 0V. Keeping the isolation gate at a value of V _{DD results} in more uniform tunneling across the channel, improving reliability.

5 illustrates a decoding and sense amplifier unit (sense amplifier) 500 of the memory module 400 of FIG. 4 in the form of a partial block diagram, a partial logic diagram, and a partial configuration diagram. The sense amplifier 500 is represented by the sense heavy amplifiers SA1 through SAN described in FIG. 4. Sense amplifier 500 includes decoding logic 510 and 520, P-type MOS transistors 542, 544, 562, 564, inverters 546 and 566, current sources 548, 550, 568, 570, and also voltage Comparator 530 is included. The decoding logic 510 includes a plurality of N-type MOS transistors including transistors 512 and 513, a selection circuit 515, and a threshold voltage comparator 511. The transistor 512 has a gate and a first current electrode and a second current electrode which receive one of a plurality of bit lines from the bit cell array 440. The transistor 513 has a gate and a first current electrode and a second current electrode which receive one of a plurality of bit lines from the bit cell array 440. The selection circuit 515 has a plurality of transfer gates including the transfer electrodes 518 and 517. The transfer gate 518 is connected to a node 531, referred to as "INA", a positive and negative control electrode connected to the control and decoding unit 410, a first current electrode connected to the second current electrode of the transistor 513, and Has a second current electrode. The transfer gate 517 is a positive and negative control electrode connected to the control and decoding unit 410, a first current electrode connected to the second current electrode of the transistor 512, and a second current connected to the node INA 531. Has an electrode.

Decoding logic 520 has a number of N-type MOS transistors, including transistors 522 and 523, selection circuit 525, and threshold voltage generator 521. Transistor 522 has a first current electrode and a second current electrode that receive one of a plurality of bit lines from gate, bit cell array 480. Transistor 523 has a first current electrode and a second current electrode that receive one of a plurality of bit lines from gate, bit cell array 480. The selection circuit 525 has a plurality of transfer gates, including the transfer gates 528 and 527. The transfer gate 528 is connected to a node 532 called "INB", a positive and negative control electrode connected to the control and decoding unit 410, a first current electrode connected to the second current electrode of the transistor 523. Has a second current electrode. The transfer gate 527 has a positive and negative control electrode connected to the control and decoding unit 410, a first current electrode connected to the second current electrode of the transistor 522, and a second current electrode connected to the node INB. .

Transistor 542 has a gate, a source and a drain connected to V _DD . The transistor 544 has a gate connected to the node INA 531, a source connected to the drain of the transistor 542, and a drain connected to the node INA. Inverter 546 has an input terminal for receiving a signal called " right array enable " 584, and an output terminal coupled to the gate of transistor 542. Current source 548 has an enable input terminal that receives signal left array enable 580, a first current terminal coupled to V _DD , and a second current terminal coupled to node INA 531. Current source 550 has an enable input terminal that receives signal right array enable 584, a first current terminal coupled to node INA 531, and a second current terminal coupled to V _SS .

P-type MOS transistor 562 has a gate, a source and a drain connected to V _DD . P-type transistor 564 has a gate connected to node INA, a source connected to the drain of transistor 562, and a drain connected to terminal INA. Inverter 566 has an input terminal that receives left array enable 580 and a second output coupled to the gate of transistor 562. Current source 568 has an enable signal that receives a signal called " right array enable 584 ", a first current terminal coupled to V _DD , and a second current terminal coupled to node INB. Current source 570 has an enable terminal for receiving a signal called " left array enable 580 ", a first current terminal coupled to ground, and a second current terminal coupled to node INA. The voltage comparator 530 is a control input terminal for receiving a signal called "comparison enable 582", a first input terminal connected to the node INA, a second input terminal connected to the node INB, "DATA OUT". 534 " has an output terminal for providing a signal.

Sense amplifier 500 represents one sense amplifier portion of sense amplifier 450. The element described in sense amplifier 500 is part of the sense amplifier associated with the read mode.

During the time of the read cycle in operation, the voltage levels of nodes 531 and 532 on one side of voltage comparator 530 are equalized to V _DD by a circuit not shown in FIG. 5. The sense amplifier 500 detects the appropriate stored data state in the bit cell in the voltage comparator 530 by generating different charge ratios between the node INA 531 and the node INB 532 and in response the signal DATA OUT. 534 may be driven.

If node (INA) 531 is selected to receive information from bit cell array 440 and the non-conductive bit cell of array 440 is selected, node (INA) 531 has no charge rate. As a result, a node (INB) 532 that is not selected to receive information from the bit cell array 480 is allowed to charge at a predetermined rate, so that a voltage comparator is used at node (INA) 531 than at node (INA) 531. Allow detecting a lower voltage at INB) 532. Based on the comparison, voltage comparator 530 provides signal DATA OUT 534 with a high logic level or low logic level signal as specified by the system.

When node INA 531 is selected to receive information from bit cell array 440 and the conductive bit cell of array 440 is selected, a discharge rate is generated at node INA 531. The sense amplifier 500 is designed such that the discharge rate at node INA 531 is greater than the discharge rate at node INB 532. This difference in discharge rate allows the voltage comparator 530 to detect a lower voltage at node INA 531 than at node INB 532. As a result, the voltage comparator 530 detects a state complementary to the read when the non-conductive bit cell is read.

The discharge rate of the node (INB) 532 that acts as a reference when data is read from the bit cell array 440 is the current source that is enabled when the left array enable 580 is asserted to indicate the beginning of the read cycle. 570 is controlled at a substantially fixed rate. In addition, activation of signal left array enable 580 enables current source 548 to provide current to charge node INA 531 at a predetermined rate when selected. The rate at which current source 548 provides charging to node INA 531 is such that the node maintains a pre-charged V _DD voltage when non-conductive bit cells are selected in array 440. In addition, the rate at which current source 548 provides charging to node INA 531 is such that the rate of discharge at node INA 531 is discharged at node INB 532 when a conductive bit is detected. The discharge ratio and size of the current source 570 are different so as to be larger than the ratio.

The relationship of current sources 548 and 570 allows voltage comparator 530 to sense the conductive state of the bit cell when node INB 532 and node INA 531 are discharged. This relationship is useful when operating at high operating frequencies in that discharge occurs over a relatively short time period. Over time, if nodes 531 and 532 are allowed to be fully discharged to 0V, sense amplifier 500 cannot read conductive bit cells, thereby preventing voltage comparator 530 from reading correct data. To solve this problem, the sense amplifier 500 includes a clamping circuit formed of a P-channel transistor 564 and an enable P-channel transistor 562 connected with a diode. Transistors 562 and 564 clamp node (INB) 532 to a predetermined voltage, thereby preventing current source 570 from completely discharging node 532. As a result, when nodes 531 and 532 finish discharging in a slow system, node INB 532 maintains a higher voltage level than node INA 531 such that the voltage difference is greater than voltage comparator 530. Can be detected. Conversely, when the non-conductive bit is read, node (INB) 532 is at a lower voltage than node (INA) 531.

In order to sense data in the manner described above, it is necessary to convert the current sensed from the bit cells in the array 440 to the voltage at the node INA 531. The sense amplifier 500 achieves this sensing in a manner that allows operation at very low supply voltages by separating the current-voltage conversion function from the loading function and distributing it to the other side of the selection circuit 515. The sense amplifier 500 allows for low voltage operation by ensuring that the amount of voltage drop sensed by the voltage comparator 530 is optimized, as opposed to prior art with lower currents to generate a voltage drop.

The voltage translation relationship between these components begins when the transfer gate 517 is selected. Note that the transmission gate 517 is one of eight transmission lines in the left bit decoding block 519 that is controlled by the decoding logic to select one of the eight bit gates from the bit cell array 440. Once selected, current sensed from the selected bit line is allowed to flow through the N-channel transistor 512 biased to a level 2 N-channel threshold above V _SS by the voltage reference 511. This allows the N-channel transistor 512 to be operated in a manner similar to a common gate amplifier with low input impedance and relatively high output impedance. The low input impedance characteristic of transistor 512 allows the bit line side of transistor 512 to be precharged quickly at the beginning of the read cycle, and the high impedance output characteristic combined with the very high impedance characteristic of current source 548 is a node. Allow high voltage gain across transistor 512 for (INA) 531.

As a result of the distribution of the sense amplifier function, the transistor 512 in this embodiment provides a lower impedance than that provided by the prior art for the bit line. The advantage of locating the current-voltage converter in this way is that there is less voltage drop across the transfer gate 517, requiring less bit line charge time or smaller precharge transistors. Another advantage of the present invention over the prior art is the fact that node INA 531 is charged to V _DD prior to the start of the read cycle. As a result, when the transfer gate 517 is selected, the P-channel gate to source voltage of the transistor gate 517 is a full power supply V _DD . This allows the P-channel portion of the voltage transfer gate 517 to be fully conductive. In the prior art, the gate-to-source is limited to the bit line operating level, which provides a gate drive very close to the threshold of the V _DD -device. As a result, the prior art transmission gates operate near the blocking. In the present invention, node INA 531 is allowed to be completely discharged to ground during a slow operating memory cycle. If there is no N-channel portion of the gate, this is not allowed to occur.

In the above discussion focused on reading from the memory array portion 440, when data is read from the memory array portion 480, the circuit operates in a similarly reflected form.

FIG. 6 illustrates a timing diagram of various signals associated with the read cycles of conductive and nonconductive memory cells, which is useful for understanding the operation of the sense amplifier 500 of FIG. The horizontal axis represents time in each graph section. Conductive bit reads and nonconductive bit reads are represented by three graph parts, respectively. The first graph part represents the voltage in vertical access, the second graph part represents the current, and the third graph part represents the comparator output state.

FIG. 6 illustrates the signal relationships discussed with reference to FIG. 5 for conductive bit reads and non-conductive bit reads. Although the relationship values of the signals described in FIG. 6 are useful for understanding the operation of the memory module 400, they are not necessarily drawn to scale. When data is read at node INA 531 during conductive bit reading as described above, the voltage level at node INB 532 is discharged at a different rate than the signal at node INA 531. It is not completely discharged to ground. As a result, the voltage comparator 530 detects the voltage between the node INA 531 and the node INB 532 which is distorted only by the internal voltage offset of the comparator 530, thereby detecting the voltage of the selected memory cell. The status can be read.

Similarly, graph 600 includes an indication of the memory cell current associated with the bit cells of array 440, referred to as “IBIT” 612; Display of current through current sources 548 and 568, referred to as " SI " And display of current through current sources 550 and 570, referred to as " SI " Similarly, graph 600 is also provided with graph information for non-conductive bit reads.

7 illustrates a programming driver 700 used in the memory module 400 of FIG. 4 in a block diagram form. The programming driver 700 forms part of the sense amplifier 500 of FIG. 5 and includes both devices common to the read cycle and devices unique to the write cycle. The programming driver 700 includes a portion of the voltage comparator 530 of FIG. 5, the program driver 710, the decoders 720 and 760, and the forced circuits 740 and 780. Some of the voltage comparators 530 associated with the programming driver 700 include isolation circuits 730 and 770 and a balanced latch 750. Isolation circuit 730 has an input coupled to node 731 and an output coupled to node INA 531. Isolation circuit 770 has an input and a terminal INB connected to node 771. The balance latch 750 includes a control input terminal for receiving signals referred to as "READ LATCH", "READ LATCHB", "PROGRAM LATCH", and "PROGRAM LATCHB", a data input terminal connected to the nodes 731 and 771, and a signal DATA. It has an output terminal for providing an OUT 534.

The forced circuit 740 has an input terminal for receiving a signal called "DATAL" and an output terminal connected to the node 731. The forced circuit 780 has an input terminal for receiving a signal called "DATAR" and an output terminal connected to the node 771. Program driver 710 is a voltage reference input terminal that receives a charge pumped reference voltage called " VPGM ", a first input terminal " IN1 " connected to node 731, " connected to node 771 ". A second input terminal called IN2 ", a first output terminal called" OUT1 "for providing a first output signal called" VOUTL "," OUT2 "for providing a signal called" VOUTR " It has a second output terminal called.

In operation, the programming driver 700 includes elements common to the sense amplifier 500 of FIG. 5 to save circuit area. As shown in FIG. 7, the voltage comparator 530 is also used during the program mode and includes a balanced latch 750 and two isolation circuits 730 and 770. The balance latch 750 receives data driven from the forced circuits 740 and 780 to the selected bit line. In the program mode, signals DATAL and DATAR are both driven, but in a complementary fashion. Which of the signals DATAL and DATAR are true and which is complementary depends on the selected array half. This state is stored in the latch when signals called "PGM LATCH" and "PGM LATCHB" are activated. The latched data is received by the program driver 710 which provides an appropriate voltage level to the bit line decoder in which the selected bit line is located. Similarly, when the right bit cell array 480 is selected during the write mode, the forced circuit 780 drives the appropriate state with the latch 740, and the program driver 710 sends the appropriate signal to the bit line decoder 760. To provide.

Program driver 710 is adapted to receive signals on nodes 731 and 771 at inputs IN1 and IN2 and to provide output voltages referred to as OUT1 and OUT2 respectively. The voltage at OUT1 and OUT2 is at a voltage level greater than the received voltage. The larger voltage level is determined by the input voltage signal VPGM which is approximately 5V. Because of the operation of the program driver 710, the voltage comparator 530 requires the isolation circuits 730, 770 to prevent the higher voltage signals OUT1, OUT2 from damaging the circuit of the balanced latch 750. In addition, during the program cycle, the current demand of the selected memory cell has a significant effect on the voltage of the VPGM, so it is important to power the balance latch 750 from a stable V _DD supply that is separate from the VPGM. Reuse of the voltage comparator 530 allows a reduction in circuit area and allows the program drive function to be made within a relatively small pitch, i.e., within the 8-bit gap associated with the sense amplifier.

FIG. 8 illustrates certain circuits used to implement the programming driver 700 of FIG. 7 and part of the sense amplifier 500 of FIG. 5 in partial logic and partial configuration diagrams. Since the circuit of FIG. 8 is a specific example of such a circuit, there is not necessarily a one-to-one correspondence between the signal of FIG. 8 and the signal of FIG. 5. For example, signal comparison enable 582 in FIG. 5 is implemented using the complementary signals SALATB and SALAT in FIG. Signal DATA OUT 534 is implemented with the complementary signals DATAL and DATAR of FIG. 8 forming part of the bus. Signals CDECL and CDECR in FIG. 8 are node INA 531 and node INB 532 in FIG. 5, respectively. Other elements corresponding to those of FIGS. 5 and 7 are identified with the same reference numerals.

9 illustrates a control gate driver circuit 900 in accordance with the present invention in the form of a partial block diagram, a partial logic diagram, and a partial configuration diagram. The control gate driver circuit 900 represents a portion of the high voltage word decoding unit 430 of FIG. 4. The control gate driver circuit 900 includes an isolation circuit / level shifter 910, a voltage reference switch 912, a P-type MOS transistor 925, 932, 934, 936, a bias circuit 920, an eraser. A voltage source 914, a positive program voltage source 916, a negative program voltage source 930, a pulse circuit 940, and a high voltage row decoder 950.

Isolation circuit / level shifter 910 is a first input terminal for receiving a signal referred to as "program / erase decode" 964, a second input terminal for receiving a signal referred to as "read signal" 962, One voltage reference terminal, a second voltage reference terminal connected to a ground potential, and an output terminal. The voltage reference switch 912 is an output terminal connected to provide a voltage reference output to a first input voltage reference terminal, a second input voltage reference terminal, a third input voltage reference terminal, and a first voltage reference terminal of the isolation circuit 910. Has

Transistor 925 has a gate connected to ground potential, a drain connected to ground potential, a source connected to a first input voltage reference terminal of voltage reference switch 912, and a bulk terminal. The bias terminal 920 has a first terminal connected to the source of the transistor 925 and a second terminal connected to the bulk terminal of the transistor 925. The bias terminal 920 includes resistors 921 and 922. The resistor 921 has a first terminal connected to V _DD and a second terminal connected to the bulk electrode of the transistor 925. The resistor 922 has a first terminal connected to the second terminal of the transistor 921 and a second terminal connected to the source of the transistor 925.

The erase voltage source 914 has a first terminal connected to the ground reference potential and a second terminal connected to the second voltage reference input of the voltage reference switch 912. Positive program voltage source 916 has a first voltage terminal connected to a ground potential reference and a second voltage reference terminal connected to a third input voltage reference terminal of voltage reference switch 912. Transistor 936 includes a gate connected to the ground reference potential, a first current electrode connected to the output terminal of the isolation circuit 912, a second current electrode connected to the control gate of the transistor along the selected row, and a bulk electrode connected to the first current electrode. Has Transistor 934 has a gate, a first current electrode, a second current electrode connected to a second current electrode of transistor 936, and a bulk electrode connected to a first current electrode of transistor 936. Transistor 932 has a gate, a first current electrode, a second current electrode connected to a first current electrode of transistor 934, and a bulk electrode connected to a first current electrode of transistor 936. Negative programming voltage source 930 has a first terminal connected to a ground voltage source and a second terminal connected to a first current electrode of transistor 932. The pulse circuit 940 has an input that receives a signal called a "decoded address" and has a first output terminal connected to the gate of the transistor 932 and a second output terminal connected to the gate of the transistor 934. The high voltage row decoder 950 has an input for receiving a signal called "address" 960 and an output for providing a decoded address signal to the pulse circuit 940.

As shown in FIG. 9, the control gate driver circuit 900 includes a high voltage preliminary decoding block 432 and a portion of the high voltage word decoder 430. However, in other embodiments, the designation of these functions may be different. Therefore, it is important to recognize the function that is performed entirely by the control gate driver circuit 900.

In operation, the control gate driver circuit 900 drives the control gate as specified in FIG. 3 and further described with reference to FIG. 4. During the read mode, the voltage reference switch 912 is set to the first position to be electrically connected to the source of the transistor 925. In addition, during read mode, the read signal 962 is activated such that the isolation circuit / level shifter 910 provides a voltage at the output terminal that is equal to the voltage at the first voltage reference terminal. This voltage is equal to the P-channel threshold voltage of transistor 925 plus a small amount added. The small amount added is determined by the relative size of resistors 921 and 922 and the characteristics of transistor 925. The bias circuit 920 uses the body effect of the MOSFET to cause the threshold of the transistor 925 to be slightly increased, so that the voltage at the source of the transistor 925 to which the diode is connected is conductive so that the voltage of the transistor 936 is conductive. Slightly higher than the voltage required at the source. Since the difference in bias between transistor 925 and transistor 936 is increased, transistor 936 is slightly conductive. This control to make transistor 936 slightly conductive is achieved by biasing the bulk of transistor 925 slightly above the source via bias circuit 920 and matching between transistors 925 and 936. Preferably, transistors 925 and 936 are given the same gate width and gate length magnitude and face the same direction in the integrated circuit. In addition, a good small additional voltage is selected to ensure that the transistor 936 is conductive for all expected process variations.

During the erase mode, the voltage reference switch 912 is set to the second position to electrically connect the erase voltage source 914 and the first voltage reference terminal of the isolation circuit / level shifter 910. Since the read signal 962 is inactive during the erase mode, it is determined by the program / erase decode signal 964 whether the isolation circuit / level shifter 910 provides + 15V to the control gate. The program / erase decode signal 964 represents a logical combination of the predecoded signal and the program / erase signal received from the low voltage word decoding block 420 or 460. If the program / erase decode signal 964 is active during the erase mode, the control gate driver 900 drives the corresponding control gate to the + 15V level generated by the erase voltage source 914.

During the program mode, the voltage reference switch 912 is set in the third position to electrically connect the positive program voltage source 916 and the first voltage reference terminal of the isolation circuit / level shifter 910. Unlike the erase mode, the program / erase decode signal 964 is activated during the program mode when the corresponding control gate is not located in the selected row. When driving an unselected row, the isolation circuit / level shifter 910 drives a voltage, such as 3.5V, provided by the positive program voltage source 916. The 3.5V signal applied to the first current electrode of transistor 936 causes transistor 936 to conduct, thereby supplying a voltage of 3,5V to the control gate of the cell that is not selected to program.

When the program / erase decode signal 964 is deactivated to indicate that the corresponding control gate is located in the selected row, the isolation circuit / level shifter 910 drives V _SS to the first current electrode of the transistor 936 to drive the transistor. Make 936 non-conductive. At the same time, the high voltage row decoder 950 activates the signal decoded address into the pulse circuit 940. The pulse circuit 940 makes the transistors 932 and 934 conductive, so that a negative program voltage source 930 is connected to the control gate. When selected in this form, the transistor 936 acts as an isolation transistor to prevent -12V provided by the negative program source 930 from reaching the output terminal of the isolation circuit / level shifter 910.

By providing the cells not selected to program the 3.5V bias, the control gate driver circuit 900 serves two purposes. First, it reduces some of the bit cell junction leakage currents that are affected by the electric field near the edges of the floating gate. This reduction in leakage current actually reduces the current demand from the programming power supply. Control gate driver circuit 900 also uses a 3.5V bias at the control gate that is not selected to mitigate the electric field across the oxidation tunnel of the cell that is not selected at the bit line selected to program. This reduces the rate at which the bit line voltage interferes with the data state stored in the unselected cells of the bit lines being programmed.

The negative program voltage source 930, the positive program source 916, and the erase voltage source 914 are common to both the left half bit cell array 440 and the right half bit cell array 480. Within the high voltage word decoding block 430 are four transistors, of which the transistor 932 is representative. Further, the transistor corresponding to the transistor 934 corresponds to each word line.

Instead of providing a continuous activation signal to the selected word line during the program mode, the pulse circuit 940 provides a pulse train to the selection transistors 932 and 934 to gradually represent a program voltage of -12V at the selected word line. Since the circuit connecting the negative program source 930 is not in the critical speed path of the read load, there is no need to maximize the speed that allows the pulse circuit 940 to gradually represent the -12V required. In addition, transistors 932 and 934 can be made smaller. In the described embodiment, transistor 934 is small enough to fit within the gap of the memory cell. Moreover, such pulsed operation allows the capacitor in the charge pump to operate with or generate a negative program voltage source 930 to be made smaller as well.

10 illustrates in block diagram form a particular circuit used to implement a portion of the pulse circuit 940 of FIG. Note that this circuit is just one example and that other circuits may be used. 10 also describes transistor 934 and P-channel transistor 1002. Transistor 1002 is similar to transistor 934 but drives the control gate at a different word line than transistor 934. Transistor 934 provides a control gate drive signal referred to as "CG0", while transistor 1002 provides another control gate signal referred to as "CG1". Since this is a particular implementation of the invention, there is not necessarily a one-to-one correspondence between the signal of FIG. 10 and the signal of FIG. 9.

FIG. 11 illustrates a charge pump 1120 used to generate a power supply voltage to the control gate drive circuit 900 of FIG. 9 in accordance with the present invention in partial block diagram and partial configuration diagram form. The charge pump 1120 includes a nonlinear stage 1130, a reference voltage generation stage 1140, and linear stages 1150, 1160. The voltage reference generation circuit 1140 is connected to the first voltage reference terminal V _DD and makes a reference voltage called "V _Z ". V _DD is a larger positive supply voltage terminal with a nominal value of 2.7 V, but can be much lower. The stage 1130 is connected to V _DD and receives a reference voltage (V _Z ) and a signal called "program / erase control", and also a signal called "program voltage 1" and "ΦA", "ΦB". , &Quot; ΦC "," ΦD " Linear stage 1150 receives signals ΦC, ΦD, and program voltage 1 to generate an output signal called " erasure voltage ". Linear stage 1160 receives signals ΦA and ΦB and generates a signal called " program voltage 2 ". As specified in FIG. 3, program voltage 1 is approximately 5V and program voltage 2 is approximately -12V, so they are suitable for use in programming the EEPROM cell of FIG. The erase voltage is also set to approximately 15.5V.

Nonlinear stage 1130 is a regulated voltage having an input connected to V _DD , an input called “V _Z ” for receiving a voltage reference signal, and an output for providing an output voltage that approximately doubles the voltage received at the input. Dual stage 1132; Voltage dual stage 1134 having an input connected to the output of the stage 1132, an input called "V _Z " for receiving a voltage reference signal, and an output for providing an output voltage that approximately doubles the voltage received at the input. ); An input connected to the output of the stage 1134, an input called "V _Z " for receiving a voltage reference signal, an output for providing a signal program voltage 1, a voltage dual stage with phase signals Φ A, Φ B, Φ C, Φ D (1136).

Preferably, the voltage V _Z is selected to limit the stage making the output greater than 5V as required by the program voltage 1. In an embodiment of the invention, each stage receives the same voltage reference when both receive the same voltage V _Z. In other embodiments, different reference voltages may be used for each stage. Adjusted voltage double stage 1136 generates a series of drive signals having a voltage amplitude approximately equal to program voltage 1. This drive signal is used to provide timing and power to the linear stages 1150, 1160.

The voltage reference generator circuit 1140 includes a regulated voltage double stage 1142 coupled to the regulated voltage double stage 1144. Stage 1144 is connected to linear stage 1146. The stage 1146 is connected to a current shorted regulated circuit 1148 connected to a power supply voltage terminal called "V _SS ". V _SS generally has a nominal value of 0V, which is a lower potential than V _DD . Regulated voltage double stages 1142 and 1144 are used in unregulated form. Like stage 1144, stage 1142 doubles the voltage provided at the input. Similarly, linear stage 1146 is also unadjusted. However, one skilled in the art will understand that one of the stages 1142, 1144, 1146 needs to have secondary regulation to prevent breakage of the transistors imparted to it. It is understood that the stages 1142, 1144, and 1146 can be various combinations of linear and voltage dual stages that depend on current and area limitations for predetermined applications. For the charge pump 1120, the stages 1142, 1144, 1146 generate a voltage V _Z sufficient to bias the diode 1148 to insulate break, thereby providing a reference voltage V _Z.

The linear stages 1150 and 1160 are used to generate an erase voltage and a program voltage 2, respectively. Stages 1150 and 1160 are Dickson type linear charge pumps already known in the art.

12 illustrates voltage dual stage 1132 in partial block diagram and partial configuration diagram form. Note that the voltage double stage 1132 can be used as one of the other voltage double stages of FIG. Voltage dual stage 1132 includes capacitors 1282 (C1), 1292 (C2), 1204 (C3), P-type transistors 1283, 1284, 1285, 1286, 1293, 1294, 1295, 1296, 1202, N Channel transistors 1287, 1297, 1206, and also a level shifter 1270. Capacitor C1 has a first electrode and a second electrode. The P-type transistor 1283 has a control electrode for receiving a signal called "CK3", a first current electrode, a second current electrode connected to the first electrode of the capacitor C1, and an N- connected to the first current electrode. It has a type bulk terminal. Transistor 1284 is connected to receive a signal called " CK7 ", a control electrode, a first current electrode, a second current electrode connected to the first electrode of capacitor C1, and a N- connected to the bulk terminal of transistor 1283. P-type transistor 1285 is a control electrode connected to receive a signal referred to as "CK6", a first current electrode connected to a second current electrode of transistor 1284, referred to as "V _IN ". The second transistor has a second current electrode connected to receive the input voltage, and an N-bulk terminal connected to the N-bulk terminal of the P-type transistor 1283. The P-type transistor 1286 receives a signal called "CK5". And a control electrode connected to receive the first current electrode connected to the second current electrode of the transistor 1285, a second current electrode connected to the second electrode of C1, and an N-bulk terminal connected to receive the input voltage V _IN . Transistor 1287 has "CK1" And a control electrode connected to receive a signal referred to therein, a first current electrode connected to the second current electrode of the transistor 1286, and a second current electrode connected to the first voltage reference terminal, which is referred to as "CK8". Has a control electrode connected to receive a losing signal, a first current electrode connected to a first current electrode of transistor 1284, a second current electrode, and an N-bulk terminal connected to an N-bulk terminal of P-type transistor 1283. P-type transistor 1295 includes a control electrode connected to a control electrode of transistor 1286, a first current electrode connected to a second current electrode of transistor 1294, a second current electrode connected to receive V _IN , a transistor ( And an N-bulk terminal connected to the N-bulk terminal of 1283. The P-type transistor 1296 includes a control electrode connected to the control electrode of the transistor 1285, and a first electric current connected to the second current electrode of the transistor 1285. Electrode, the N- has a bulk terminal connected to receive a second current electrode, V _IN. Transistor 1297 has a control electrode connected to receive a signal referred to as "CK2", a first current electrode connected to a second current electrode of transistor 1296, and a second current electrode connected to a first voltage reference terminal. C2 has a first electrode connected to the second current electrode of transistor 1294 and a second electrode connected to the second current electrode of transistor 1296. Transistor 1293 is a control node coupled to receive a clock signal referred to as " CK4 ", a first current electrode coupled to a first current electrode of transistor 1283, a second current electrode coupled to a first electrode of C2, a transistor ( 1283), which has an N-bulk terminal connected to the N-bulk terminal.

Transistor 1202 includes a control electrode connected to a first voltage reference terminal, a first current electrode connected to a first current electrode of transistor 1283, a second current electrode connected to a first current electrode of transistor 1294, and a transistor 1283. Has an N-bulk terminal connected to the N-bulk terminal. Capacitor C3 has a first electrode connected to the second current electrode of transistor 1202 to provide a signal referred to therein as an " unregulated output voltage ", and a second electrode connected to the first voltage reference terminal. Transistor 1206 has a control electrode connected to receive the voltage V _Z , a first current electrode connected to the first electrode of C3, and a second current electrode for providing an output referred to as a “regulated output voltage”. The level shifter 1270 is connected to the first terminal electrode of the transistor 1206, receives V _IN , Φ 1 to Φ 4, and also provides signals CK3, CK4, CK5, CK6, CK7, CK8.

In operation, the voltage reference circuit 1140 provides a reference voltage V _Z to each voltage double stage 1132, 1134, 1136 of the nonlinear stage 1130. Since only V _Z provides a voltage reference, only a minimal amount of charge needs to be provided by the circuit 1140. Non-linear stage 1130 provides a program voltage 1, thus providing the charging required by an external load (not shown). By using a non-linear stage, a first stage with a thinner dielectric layer can be formed on the semiconductor device because of the significantly lower voltage at this first stage. The thinner dielectric allows the capacitor to have a higher capacitance, as will be described later with reference to FIG. This allows the charge pump to use less semiconductor area.

FIG. 13 illustrates a timing diagram of a signal useful for understanding the operation of the voltage dual stage 1132 of FIG. 12. 12 illustrates the timing relationship of signals CK1-CK8 and φ1-Φ4 that control the operation of the regulated voltage double stage 1142 of FIG. 12. Referring now to FIG. It is activated or deactivated during a certain time or part of a clock cycle. The clock cycle portion is referred to as t1, t2, t3 and t4. CK1 is highly active during t1 and t2. CK4 is underactive during t1. CK6 is in a low activation state during time t1. CK8 is underactive during the period t1. CK2 is in a high activation state during periods t3 and t4, and CK3 is in a low activation state during t3. CK5 is underactive during t3. CK7 is underactive during the period t3. The arrows in FIG. 13 indicate when edges occur at substantially similar times during t2 or t4, but note that they follow another edge that occurs at substantially the same actual time. For example, the rising edge of CK4 at time t2 occurs after the rising edge of CK6 during time t2. This effectively ensures that the transistor controlled by CK6 transitions before CK4, which is inactive. CK1 and CK2 transition to the low activation state at the end of times t2 and t4, respectively. The timing of FIG. 13 allows capacitors 1242 and 1292 to be charged in another way by the input signal while providing a regulated output voltage through transistor 1206.

During t1, once a steady state condition is obtained, capacitor C1 is charged and capacitor C2 is discharged. Since the transistors 1285 and 1287 are driven to the active state while the transistors 1284, 1286 and 1283 are driven to the inactive state, charging of the capacitor C1 is easy. This connects capacitor C1 between V _IN and the first voltage reference while isolating capacitor C1 from the rest of circuit 1132. As a result, charge flows to C1 until it is charged to voltage V _IN , or until the cycle is over. During t3, capacitor C2 is charged in a similar manner to V _IN .

During t1, C2 generates the double voltage needed to provide an unregulated output voltage. This is facilitated by transistors 1293, 1296, 1294 driven in an active state while transistors 1297, 1295, 1284, 1286 are driven in an inactive state. This connects C2 between the unregulated output voltage terminal and V _IN , insulating capacitor C2 from the rest of circuit 1132. The voltage produced at the first electrode of transistor 1294 representing the unregulated output voltage is the sum of the voltage across V _IN and C2. As mentioned above, the voltage across C2 is approximately V _IN, thus providing a doubled or redundant V _IN voltage. The unregulated output voltage is regulated by transistor 1206 biased by voltage V _Z which is essentially constant to provide a regulated output voltage. During t3, capacitor C1 is connected between V _IN and the output terminal in a similar manner.

During time t2, it is necessary to keep transistor 1287 in an active state to prevent charge from being injected at the electrodes common to transistors 1286 and 1287. This ensures that the electrode remains at ground, thereby ensuring that the drain to substrate junction represented by the electrode is not forward biased. For example, by ensuring that transistors 1284, 1285, 1286 are fully transitioned before tuning transistor 1287 to inactive state, it prevents the possibility of substrate biasing forward biased. Similarly, when transistors 1294, 1295, 1296 transition during time t4, transistor 1297 remains active to prevent the same effect at the node common to transistors 1296, 1297.

Transistors 1283, 1284, 1285, 1293, 1295, 1202 have a common N-bulk terminal. According to one embodiment of the invention, the N-bulk terminals are substantially N-wells. This N-well is charged to unregulated output voltage through transistors 1283 and 1293 that are active during times t3 and t1, respectively. Transistor 1202 is a weak transistor used to ensure that the N-well voltage does not rise significantly above the regulated output voltage and stays there for a long time period. For example, there is a situation where at start-up or when the output load is applied to the output of the charge pump, the N-well is significantly charged to a voltage above the unregulated output voltage. This voltage difference makes the MOS transistor less conductive than the others. If continued, this condition will reduce the overall output of the pump. Therefore, transistor 1202 ensures that the voltage difference is simply a temporary characteristic. By driving the N-bulk to an unregulated output voltage and not charging and discharging it to all cycles, the efficiency is increased because no charge is lost due to the capacitive excitation associated with the well.

It is possible to have a time period in which CK4 is transitioned and CK1 is not transitioned during the times t2 and t4. During this time it is not possible for the regulated output voltage to receive a voltage from transistor C1 or C2, so that capacitor C3 is needed to bridge the gap during this time period and level during t2 and t4. Supply the charge required by the shifter 1270. In general, when the time denoted by t2 is much smaller than t1, the capacitor C3 becomes much smaller than the capacitors C1 and C2. Similarly, C3 provides the voltage needed during time t4.

The level shifter 1270 receives the signals Φ 1 to Φ 4 as shown in FIG. 13. Φ 1 represents an activation signal during time t 1. Signal Φ 2 represents an activation signal during time period t2. Signal Φ 3 represents the activation period for time t 3. Signal φ4 represents the activation signal for time t4. These signals are combined to generate appropriate activation and deactivation signals for CK1 through CK8. CK1 and CK2 have an inactive low voltage of zero or ground and an active high voltage reference of V _DD . CK3 through CK8 have a low signal such as zero or ground when activated or deactivated, and the high state is equal to the unregulated output voltage that appears at the first electrode of capacitor C3 when activated or deactivated. In addition, CK1 and CK2 are generated by combining signals? 1 and? 2 and signals? 3 and? 4, respectively. As such, the level shifter applies the appropriate voltage level needed to drive the stage in the charge pump 1120 of FIG.

Referring back to FIG. 11, stages 1142 and 1144 are performed using the adjusted voltage dual stage circuit 1132 of FIG. 12. However, block 1144 is shown to drive two signals .phi.5 and .phi.6 to drive a Dickson type stage 1146. Because of the requirements of the Dickson stage 1146, the signals Φ 5 and Φ 6 should be substantially equal to the bias or output voltage of the stage 1144. If this condition is met, the Dickson stage 1146 with three internal stages provides an output voltage that is four times the input voltage, but in any case is limited to the breakdown voltage of the diode 1148.

Stages 1132, 1134, 1136 of nonlinear stage 1130 use the regulated voltage dual stage circuit 1132 of FIG. 12. In each of these cases, the regulated voltage V _Z limits the voltage generated by any stage to 5V. The final stage of nonlinear stage 1130 provides additional phase signals Φ A, Φ B, Φ C, and Φ D. This signal is generated from circuit 1132 using two N and P transistor pairs (not shown) connected between the regulated output voltage node and ground. Timing is controlled by the timing signal of FIG. The selected N and P transistor pairs are actually controlled by the program / erase control signals. The selected N and P transistor pairs will generate the complementary output signals needed to allow the Dickson type charge pumps 1150 and 1160 to operate. It should be noted that the operations of the stages 1150 and 1160 are mutually exclusive in that only one stage is driven at a predetermined time.

The following equation can be used to estimate the capacitor values of C1 and C2 for each adjusted voltage double stage 1132, 1134, 1136, 1142, 1148:

Q = Iout / Freq;

V (n) = V _DD * (Vout / V _DD ) ** (n / N);

Vc (n) = 2 * V (n-1) -V (n);

C (n) = QE12 * ((2 ** (N−n) * (eff ** (n-1-N) / Vc (n));

Ctotal (N) = sum of all C (n), n = 1 to N.

Where: V _DD is the supply voltage,

N is the number of stages in the charge pump;

Iout is the desired output current;

Vout is the desired output voltage,

eff is the efficiency of the circuit;

Freq is the frequency at which the charge pump is exchanged.

Equation 1 shows the amount of charge available at the charge pump output. Equation 2 represents the voltage at the output of predetermined stage n when the stage is scaled to provide a uniform stage-to-stage voltage gain. Equation 3 is the variation in voltage during the pump cycle that includes the charging and discharging of a capacitor such as C1 or C2 and across the capacitor of a predetermined stage. Equation 4 is the total capacitance of the charge pump represented by pF and the predetermined stage. The value C (n) is the sum of the capacitances of C1 and C2. In general, C1 and C2 are substantially similar. For example, the required output current for a 1.8 V V _DD and a three-stage charge pump is 1 μA, the required output voltage is 4.5 V, and a capacitor for the first stage at a clock signal of 1 MHz and a circuit efficiency of 98%. Simple output current is 3.7 pF per μA. Stage 2 has a capacitor requirement of 1.3 pF per μA of output current and stage 3 has a capacitor requirement of 0.5 pF per μA of output current. This is the required capacitor value for the combined capacitance of C1 and C2.

The capacitance value chosen as described above represents the advantage of using the nonlinear charge pump of the present invention. The capacitor of stage 1 is considerably larger than the capacitor required for stage 2 or stage 3 combined. This relationship is shown in FIG. 14, which describes the capacitance associated with each stage of the charge pump 1120 of FIG. 11 in graphical form. The advantage is that the operating voltage of the first stage is considerably lower than the second and third stages, whereby a thinner dielectric layer can be used in the formation of the capacitor C1. For example, in one embodiment of the present invention, the dielectric layer of capacitor C1 may be the same thickness as the oxide tunnel dielectric material used in the bit cell. This allows the formation of capacitors with much smaller surface area than using thick film dielectric materials as required in stages C2 and C3 because of the higher voltages involved.

While the present invention has been described in the context of preferred embodiments, it will be apparent to those skilled in the art that the present invention may be modified in various ways and may assume many embodiments other than those specifically set forth and described above. For example, different voltage levels may be used to program the memory cell, or different numbers of control gates may be controlled by the control circuit. Accordingly, all modifications of the invention that fall within the true intent and scope of the invention are intended to be covered by the appended claims.

1 illustrates a memory array.

2 is a cross-sectional view of a memory cell that may be used in connection with the present invention.

3 is a diagram illustrating one method for operating a memory array in accordance with the present invention.

4 illustrates a memory module in accordance with the present invention in the form of a partial block diagram and a partial plan view;

FIG. 5 illustrates a portion of a decoding and sense amplifier associated with a read of the memory module of FIG. 4 in the form of a partial block diagram, partial logic diagram, and partial configuration diagram. FIG.

6 is a timing diagram of various signals associated with read cycles of conductive and nonconductive memory cells.

FIG. 7 illustrates a programming driver for use in the memory module of FIG. 4 in block diagram form. FIG.

8A and 8B illustrate particular circuits that may be used to implement some of the circuits described with reference to FIGS. 5 and 7 in the form of partial logic diagrams and partial configurations.

9 illustrates a control gate driver circuit in accordance with the present invention in the form of a partial block diagram, a partial logic diagram, and a partial configuration diagram.

FIG. 10 illustrates a specific circuit that may be used to implement a portion of the pulse circuit of FIG. 9 in schematic form.

FIG. 11 illustrates a charge pump used to generate a power supply voltage for the control gate driver circuit of FIG. 9 in accordance with the present invention in partial block diagram and partial configuration diagram form.

FIG. 12 illustrates one of the voltage dual stages of FIG. 11 in the form of a partial block diagram and a partial configuration.

13 is a timing diagram of a signal useful for understanding the voltage double stage operation of FIG.

14 illustrates the capacitance associated with each stage of the charge pump of FIG. 11 in graphical form.

* Explanation of symbols for the main parts of the drawings *

900: control gate driver circuit 910: isolation circuit / level shifter

920: bias circuit 930: negative program voltage source

940: pulse circuit 950: decoder

1120: charge pump 1130: nonlinear stage

1140: voltage reference generating circuit 1150, 1160: linear stage

Claims (4)

A control gate driver circuit 900 for providing a voltage to a control gate of an erasable and programmable nonvolatile memory cell during a read mode. A predetermined conductive pass transistor having a gate electrode connected to a first voltage reference terminal, a first current electrode, a second current electrode connected to the control gate, and a bulk electrode connected to the first current electrode; 936); And A bias circuit 920 having an output terminal connected to a first current electrode of the pass transistor, wherein the bias circuit generates a voltage on the output terminal and ensures that the pass transistor is conductive regardless of process variations. And the bias circuit (920), wherein the voltage is substantially equal to a threshold voltage plus an additional voltage of the pass transistor. A control gate driver circuit 900 for providing a voltage to a control gate of an erasable and programmable nonvolatile memory cell during a program mode. A program voltage source 930 having a reference terminal for providing a voltage for programming a nonvolatile memory cell; A predetermined conductivity type pass transistor (932, 934) having a control electrode, a first current electrode connected to the reference terminal, and a second current electrode for driving the control gate; A pulsed circuit 940 having a pulsed output terminal coupled to a control electrode of said pass transistors 932 and 934 and a data input for receiving at least one data signal, said pulsed circuit being coupled to said pulsed output terminal at least. The pulse circuit 940, providing a pulsed representation of one data signal; And A decoder 950 having an address input for receiving an address signal and a decoded output coupled to a data input of the pulse circuit 940, wherein the decoder decodes the address input during the program mode. Control gate driver circuit 900. The method of claim 2, The voltage is generated by the charge pump 1120, the charge pump, A nonlinear stage 1130 having a voltage input terminal connected to a power supply voltage terminal and a voltage output terminal for providing a regulated voltage, wherein the nonlinear stage 1130 is a plurality of series connected regulated voltage redundancy stages. The non-linear stage (1130), including (1132, 1134, 1136); And And a linear stage (1150) having a voltage input terminal connected to said voltage output terminal of said non-linear stage (1130) and an output terminal for providing said voltage. A control gate driver circuit 900 having a control gate voltage terminal for providing a control gate voltage to a control gate of an erasable and programmable nonvolatile memory cell, the circuit comprising: Read voltage terminal 962; An erase voltage terminal 914; Program selection voltage terminal 916, Program unselected voltage terminal 964; A first decoding unit 910, which receives address and control signals and is connected to the read voltage terminal, the erase voltage terminal, the program unselected voltage terminal, and has a first voltage output, wherein the first decoding unit 910 ) Is associated with a control gate of a memory cell, the first decoding unit supports a plurality of modes based on the address and control signals, wherein the modes include: An erase mode connecting the erase voltage terminal to the first voltage output when the memory cell is selected and the control signals indicate an erase mode; A program selection mode, wherein the first decoding unit 910 connects the read voltage terminal to the first voltage output when the memory cell is selected and the control signals indicate an erase mode; A program non-select mode, wherein the first decoding unit 910 connects the program select voltage terminal to the first voltage output when the memory cell is not selected and the control signals indicate an erase mode; and The first decoding section (910) comprising a read mode, wherein the first decoding section (910) connects the read voltage terminal to the first voltage terminal when the control signal indicates a reading; A second decoding section 950 for receiving address and control signals, coupled to the program selection voltage terminal, the second decoding section 950 having a second voltage output, the second decoding section being associated with the control gate of the memory cell, A second decoding unit (950) for providing the program selection voltage to the second voltage output when the memory cell is selected and the control signals indicate a program mode; And A control electrode connected to a first voltage reference, a first current electrode connected to the first voltage output, a second current electrode connected to the second voltage output and providing the control gate voltage terminal, a bulk connected to the second current electrode Control gate driver circuit 900 comprising a transistor 936 with electrodes.

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