KR100255955B1 - Flash memory device and programmble method thereof - Google Patents

Abstract

PURPOSE: A flash memory device and a program method thereof are provided to improve a program performance. CONSTITUTION: The flash memory device includes: a plurality of bit lines; a cell array(100) including a plurality of memory cells including electrically erasable programmable transistors comprising a floating gate and a control gate and accumulating charges to the floating gate or emitting the accumulated charges; buffers to latch data bits applied from the external in response to a latch signal; a unit(170) generating a program activation signal to perform a program operation; drivers to drive corresponding bit lines with voltage levels corresponding to the data bits latched in the buffers in response to the program activation signal; a unit(180) generating an input/output point signal sequentially indicating the latched data bits in response to an oscillation signal, where the buffers output data bit sequentially to the driver by the input/output point signal; a unit(190) generating a short pulse signal when a data bit corresponding to the input/output point signal is a data bit indicating a program state; and a unit(200) generating a control signal(ONfin) to activate the program activation signal generation unit when the short pulse signal is generated as many as the number to be programmed at one time.

Description

Flash memory device and programming method thereof

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a flash memory device having electrically erasable and programmable cells and a program method thereof.

Flash memory devices have received a lot of attention from users who demand high processing speed because they are much faster in program and read operations than nonvolatile semiconductor memory devices that can electrically program and erase. have. Flash memory devices may be classified into NAND type and NOR type flash memory devices. A cell array of the NOR flash memory device has a structure in which a plurality of memory cells are arranged in parallel on one bit line, whereas a cell array of the NAND flash memory device has a plurality of memory cells in one bit line. It has a structure that is arranged as.

1, there is shown a cross-sectional view showing the structure of a typical flash memory cell. As shown in Fig. 1, a flash memory cell has a source 3 and a drain 4 formed of N + impurities with a channel region interposed therebetween on a surface of a P-type semiconductor substrate 2, and 100 kHz on the channel region. A floating gate 6 formed with the following thin insulating film 7 interposed therebetween, and an insulating film (for example, an ONO film) 9 on the floating gate 6. In addition, a control gate 8 is formed. Power terminals Vs are applied to the source 3, the drain 4, the control gate 8, and the semiconductor substrate 2 to apply voltages required for program, erase, and read operations, respectively. ), (Vd), (Vg), and (Vb) are connected.

According to a conventional flash memory program operation, a flash memory cell is programmed by causing hot electron injection to the floating gate 8 in the channel region adjacent to the drain region 4. The electron injection grounds the source region 3 and the P-type semiconductor substrate 2, applies a high high voltage (eg, + 10V) to the control gate electrode Vg, and then drains the drain region. This is achieved by applying a suitable amount of voltage (for example, 5V to 6V) to generate hot electrons in (4). When a flash memory cell is programmed according to this voltage application condition, that is, a negative charge is sufficiently accumulated in the floating gate 6, (-) accumulated (or trapped) in the floating gate 6 The charge increases the threshold voltage of the programmed flash memory cell during a series of read operations.

Typically, the voltage application condition of the read operation applies a positive voltage (e.g., 1V) to the drain region 4 of the flash memory cell, and applies a predetermined voltage (e.g., to its control gate 8) Power supply voltage, or about 4.5V), and 0V to its source region 3. When a read operation is performed in accordance with the above conditions, its threshold voltage is increased by the hot electron injection method described above, that is, the programmed flash memory cell is moved from its drain region 4 to its source region 3. Injection of current is prevented. At this time, the programmed flash memory cell is said to be " off ", and its threshold voltage typically has a distribution between about 6V and 7V.

Subsequently, according to the erase operation of the flash memory cell, the memory cell is erased by generating F-N tunneling (Fowler-Nordheim tunneling) to the control gate 8 in the semiconductor substrate 2, that is, the bulk region. In general, the FN tunneling applies a negative high voltage (e.g., -10V) to the control gate 8 and generates FN tunneling between the bulk region 2 and the control gate 8. By applying an appropriate amount of voltage (eg 5V). At this time, its drain region 4 is maintained in a high impedance state (e.g., a floating state) in order to maximize the effect of the erase. When voltages corresponding to such an erasing condition are applied to corresponding power terminals Vg, Vd, Vs, and Vb, a strong electric field is formed between the control gate 8 and the bulk region 2. do. This results in the F-N tunneling described above, as a result of which negative charge in the floating gate 6 of the programmed cell is released into its source region 3.

Typically, the F-N tunneling occurs when an electric field of 6-7 MV / cm is formed between the insulating film 7. This is possible because the thin insulating film 7 of 100 kPa or less is formed between the floating gate 6 and the bulk region 2. The discharge (or discharge) of the negative charge from the floating gate 6 to the bulk region 2 by the erase method according to the FN tunneling means that the erase of the erased flash memory cell is performed during a series of read operations. It serves to lower the solder voltage.

In a general flash memory cell array configuration, each bulk area is connected to a plurality of cells together for high integration of the memory device, so that when the erase operation is performed according to the above-described erase method, the plurality of memory cells are simultaneously erased. . The erasing unit is determined according to the area in which each bulk area 2 is separated. {For example, 64K byte: hereinafter referred to as a sector.} During a series of read operations, a flash memory cell whose threshold voltage is lowered by the erase operation is applied with a constant voltage to the control gate 8. In this case, a current path is formed from the drain region 4 to the source region 3. Such a flash memory cell is said to be "on" and its threshold voltage has a distribution between about 1V and 3V. Table 1 shows the voltage levels applied to the respective power supply terminals Vg, Vd, Vs, and Vb during the program, erase, and read operations of the flash memory cell.

TABLE 1

Operation mode Vg Vd Vs Vb program + 10V + 5V to + 6V 0 V 0 V Cattle -10V Floating Floating + 5V Reading + 4.5V + 1V 0 V 0 V

2 is a diagram illustrating a state of a memory cell during a program operation. In general, program operation results in a large number of bits that can be programmed at one time due to the large amount of current (eg 400 μA) flowing from the drain terminal to the connected source terminal to which the memory cell is powered by about 5 volts. Because it is limited, it is performed in byte units (ie 8 bits) or word units (ie 16 bits). In the above program operation, 3.2 mA (400 μA × 8) current is consumed when the program is executed in byte unit, and 6.4 mA (400 μA × 16) current is consumed when the program is executed in the word unit.

However, in order to generate a voltage of about 5V applied to the drain terminal of the memory cell by using the pump circuit inside the chip during the program operation, a large number of charge pump circuits (called an internal drain pump) are used. Required. In this case, as the number of charge pump circuits increases, the layout area of the chip increases. The operation of the circuit for driving the charge pump circuit causes a large amount of active current flowing from the power supply voltage to the ground potential.

Therefore, to solve this problem, the technique of performing program operation four times in 4-bit units in order to program one word is described by AMD (advanced micro devices), which uses "A 2.7V only" of 96 'VLSI circuit. 8Mb × 16 NOR Flash Memory ”(p172-p173). However, when the program operation is performed using the technique disclosed in the above document, a problem occurs that the program performance is degraded. Thus, AMD has proposed a special program algorithm to solve the problem again.

3, there is shown a block diagram showing the configuration of a conventional flash memory device using such a program algorithm. When entering a program operation, the data input buffers Dinbuf0 to Dinbuf15 store program data bits corresponding to the external input / output pins I / O0 to I / O15, respectively. It is determined whether to apply a positive program voltage to the drain terminal of the selected memory cell. The data input buffers Dinbuf0 to Dinbuf15 are divided into four groups. Each of these groups is selected by program activation signals S0-S3 generated in a program control state machine 10.

Also, three detectors (low byte detector), (high byte detector) and (word detector) 12, 14 and 16 are data bits stored in the data input buffers Dinbuf0 to Dinbuf15. It is used to optimize the program time by controlling the number of bits to be programmed. If the number of bits to be programmed is four or less, the output signals 4bdetL, 4bdetH and 4bdetW of the detectors 12 to 16 are all set to a high level, otherwise If not, they are all kept at low level.

Referring to Fig. 4, there is shown a diagram to illustrate the concept of output signals 4bdetL, 4bdetH and 4bdetW of detectors 12, 14 and 16. 5 is a diagram showing the change of the program activation signal according to all possible word program conditions.

The program control state device 10 receives the outputs 4bdetL, 4bdetH, and 4bdetW of the detectors 12, 14, and 16 as inputs, and activates the program activation signals S0 to (4). S3) occurs. If the output signals 4bdetL, 4bdetH and 4bdetW of the detectors 12 to 16 are all at the low level, they are stored in the low byte and the high byte. It means that each contains four or more data bits to be programmed. At this time, the apparatus 10 activates the program activation signals S0 to S3 according to an appropriate timing sequence. And if the output signals 4bdetL, 4bdetH, and 4bdetW of the detectors 12, 14, and 16 are at high level, the total data bits to be programmed of the word in which both the lower byte and the upper byte are added together; Means four or less. At this time, the device 10 activates (S0) to (S3) simultaneously.

In addition, to compensate for the ramp-up time of the charge pump circuit, as shown in FIG. 5, the initial pulse is maintained as long as 4.8 μs, and is programmable as the output of the charge pump circuit. After reaching the right amount of voltage, the next pulse is held at 2.6µs. That is, the program pulse can vary from 4.8 μs to 12.6 μs depending on the shape of the pattern. The above technique has a program time of up to 16 μs, including a program verify time of 3.4 μs and other overhead time. As described above, according to the conventional program method, at least four data bits to be programmed are included in the lower byte (I / O0) to (I / O7) and the upper byte (I / O8) to (I / O15). If the program operation is performed four times, the overall program performance of the flash memory device is degraded.

It is therefore an object of the present invention to provide a flash memory device having improved program performance and a program method thereof.

1 is a cross-sectional view showing the structure of a typical flash memory cell;

2 illustrates a state of a memory cell during a program operation;

3 is a block diagram showing the configuration of a conventional NOR flash memory device;

4 is a diagram illustrating a concept of output signals of the detectors of FIG. 3;

5 shows a change in program activation signal according to all possible word program conditions;

6 is a block diagram showing a configuration of a NOR flash memory device according to the present invention;

7 is a block diagram showing a detailed configuration of the data input buffer circuit and the write driver circuit of FIG.

8 is a circuit diagram showing a data input buffer circuit according to a preferred embodiment of the present invention;

9A and 9B are circuit diagrams showing a circuit configuration of a counting unit in the program control circuit of Fig. 6;

10 is a circuit diagram showing one counter circuit in the counter portion of FIG. 9A;

11 is a block diagram showing a configuration of a comparison unit of FIG. 6;

12 is a block diagram showing a configuration of a program control signal generator of a program control circuit according to the present invention;

13 is a circuit diagram showing a detailed circuit of the flip-flop of FIG.

14 is a flowchart showing a program method of a flash memory device according to a preferred embodiment of the present invention;

15 is an operation timing diagram showing timing of signals for a program operation according to a preferred embodiment of the present invention;

16 is a view for comparing the program performance according to the prior art and the present invention,

* Explanation of symbols on the main parts of the drawings

100: cell array 110: row and column address buffer

120: row decoder 130: column decoder

140: column pass gate circuit 150: data input buffer circuit

160: write driver circuit 170: program activation signal generation circuit

180: counter 190: comparison

200: program control signal generator 210: program control circuit

According to one aspect of the present invention for achieving the above object, a flash memory device comprising: a plurality of bit lines; A cell array including a plurality of memory cells; Each of the memory cells has a floating gate and a control gate, and includes transistors electrically erasable and programmable by accumulating charge or releasing the accumulated charge in the floating gate; Buffers for respectively latching data bits applied from outside in response to the latch signal; Means for generating a program activation signal for performing a program operation; Drivers for driving bit lines corresponding to voltage levels corresponding to the data bits latched in the buffers in response to the program activation signal; Means for sequentially generating an input / output pointer signal representing each of the latched data bits in response to an oscillation signal; The buffers sequentially output data bits latched thereto by the input / output pointer signal to corresponding drivers; Means for generating a short pulse signal when the data bit corresponding to the input / output pointer signal is a data bit indicating a program state; Means for generating a control signal (ON _fin ) for activating said program activation signal generating means when said short pulse signal is generated by one programmable number.

In this embodiment, the control signal generating means is initialized by a synchronized signal when the program activation signal is deactivated.

In this embodiment, the latch signal is a signal synchronized with the write enable signal.

In this embodiment, each of the buffers comprises: a first latch for latching a corresponding data bit in response to the latch signal; And a second latch for receiving and latching the data bit from the first latch in response to the input / output pointer signal.

According to another feature of the invention, a plurality of bit lines; A cell array including a plurality of memory cells; Each of the memory cells has a floating gate and a control gate, and includes transistors electrically erasable and programmable by accumulating charge or releasing the accumulated charge in the floating gate; Buffers for respectively latching data bits applied from outside in response to the latch signal; Means for generating a program activation signal for performing a program operation; Drivers for driving bit lines corresponding to voltage levels corresponding to the data bits latched in the buffers in response to the program activation signal; The program operation for the one programmable data bits is performed after the one programmable data bits of the data bits representing the program state from the least significant bit are supplied to the corresponding drivers from the least significant bits respectively. Means for controlling buffers and means for generating said program activation signal.

In this embodiment, the program control means comprises: means for sequentially generating an input / output pointer signal representing each of the latched data bits in response to an oscillation signal; Means for generating a short pulse signal when the data bit corresponding to the input / output pointer signal is a data bit indicating a program state; Means for generating a control signal (ON _fin ) for activating said program activation signal generating means when said short pulse signal is generated by one programmable number, so that said buffers are data latched to it by said input / output pointer signal; The bits are sequentially output to the corresponding driver.

In this embodiment, the control signal generating means is initialized by a signal synchronized when the program activation signal is deactivated.

In this embodiment, the latch signal is a signal synchronized with the write enable signal.

In this embodiment, each of the buffers comprises: a first latch for latching a corresponding data bit in response to the latch signal; And a second latch for receiving and latching the data bit from the first latch in response to the input / output pointer signal.

According to another feature of the invention, a plurality of bit lines; A cell array including a plurality of memory cells; Buffers for respectively latching data bits applied from outside in response to the latch signal; A program activation signal generation circuit for generating a program activation signal for performing a program operation; 17. A method of programming a flash memory device comprising drivers for driving bit lines corresponding to voltage levels corresponding to the data bits latched in the buffers in response to the program activation signal. Sequentially generating input and output pointer signals respectively representing the signals; Sequentially outputting data bits latched in the buffers to corresponding drivers in response to the input / output pointer signal; Generating a short pulse signal when the data bit corresponding to the input / output pointer signal is a data bit indicating a program state; And generating a control signal (ON _fin ) for activating the program activation signal generating means when the short pulse signal is generated by one programmable number.

By such an apparatus and method, it is possible to control that only the bits of the program state from the least significant of the data bits latched in the data buffers are transferred to the corresponding write drivers.

Reference drawings according to embodiments of the present invention will be described in detail with reference to FIGS. 6 to 16.

)를 발생하여 프로그램 동작을 수행한다. 이로써, 플래시 메모리 장치의 프로그램 성능이 향상된다.Referring to FIG. 6, the novel flash memory device of the present invention provides a program controlling circuit 210, which program bits are respectively latched in buffers (Dinbufi). The buffers (Dinbufi) and program activation are performed such that a program operation is performed on the one-time programmable data bits after supplying data bits of a one-time programmable state from the least significant bit of DINi to corresponding drivers WDi. A control signal ON _fin for controlling the signal generation circuit 170 is generated. The program activation signal generation circuit 170 is controlled by the program control signal ON _fin to activate the program activation signal (WDi) for activating the drivers WDi.

To execute the program operation. This improves the program performance of the flash memory device.

6, there is shown a block diagram showing the configuration of a flash memory device according to the present invention. The flash memory device of the present invention includes a memory cell array 100, a row and column address buffer circuit 110, a row decoder 120, a column decoder ( column decoder 130, Y-pass gate circuit 140, data input buffer circuit 150, write driver circuit 160, program activation A program enable signal generating circuit 170, and a program control circuit 210.

The memory cell array 100, the row and column address buffer circuit 110, the row decoder 120, the column decoder 130, and the column pass gate circuit 140 are well known to those who have acquired the general knowledge in this field. As is known, the description of them is omitted here.

)에 동기된 신호이다. 즉, 상기 신호 (nD_lch)상기 신호 (

)가 활성화되고 소정의 시간이 경과한 후 활성화되고 상기 (

)가 비활성화될 때 비활성화되는 특성을 갖는다. 그리고, 상기 데이터 입력 버퍼 회로 (150)는 상기 프로그램 제어 회로 (210)로부터 출력되는 입출력 포인터 신호 (IO_fgi)에 따라 상기 기입 드라이버 회로 (160)로 상기 저장된 데이터 비트들을 순차적으로 출력한다.The data input buffer circuit 150 _latches data bits DINi (where i = 0 to 15) applied from the outside through input / output pins (not _shown ) in response to the signal nD _lch . Here, the signal nD _lch is a write activation signal (

This is a signal synchronized with). That is, the signal nD _lch the signal (

Is activated and after a predetermined time has elapsed,

) Is deactivated when deactivated. The data input buffer circuit 150 sequentially outputs the stored data bits to the write driver circuit 160 according to the input / output pointer signal IO _fgi output from the program control circuit 210.

)에 응답하여 상기 열 패스 게이트 회로 (140)에 의해서 선택되는 비트 라인들을 상기 데이터 비트들에 해당하는 전압 레벨들로 구동한다.The write driver circuit 160 receives data bits DINi sequentially output from the data input buffer circuit 150 and receives a program activation signal (

Drive the bit lines selected by the column pass gate circuit 140 to voltage levels corresponding to the data bits.

The program control circuit 210 divides the data bits DINi latched in the data input buffers into one programmable group of data bits representing a program state from the least significant bit to correspond to the data bits of the group. The data input buffer circuit 150 and the program activation signal generation circuit 170 are controlled so that the bit lines are driven at voltage levels corresponding to the data bits. The program control circuit 210 includes a count section 180, a comparating section 190, and a program control signal generating section 200.

)에 의해서 초기화된다. 상기 입출력 포인터 신호 (IO_fgi)는 최하위 비트에 관련된 입출력 핀으로부터 상기 발진 신호 (OSC)에 따라 순차적으로 2진 데이터 비트로서 활성화되는 특성을 갖는다. 아울러, 상기 신호 (IO_fgi)가 인가되는 상기 데이터 입력 버퍼 회로 (150)는 상기 신호 (IO_fgi)가 활성화될 때 대응되는 데이터 입력 버퍼에 래치된 데이터 비트를 대응되는 기입 드라이버로 출력한다. 이에 관한 설명은 이후 설명된다.The counting unit 180 generates the input / output pointer signal IO _fgi for indicating the input / output pins, respectively, in response to the oscillation signal OSC, and outputs a signal indicating a program operation mode (

Is initialized by The input / output pointer signal IO _fgi has a characteristic of being activated as a binary data bit sequentially in accordance with the oscillation signal OSC from the input / output pin associated with the least significant bit. In addition, the data input buffer circuit 150 to which the signal IO _fgi is applied outputs data bits latched to the corresponding data input buffer to the corresponding write driver when the signal IO _fgi is activated. Description of this will be described later.

Subsequently, the comparison section 190 compares the input and output pointer signal (IO _fgi) the data bits (DINi) and the output pointer signal (IO _fgi) latched to the output buffer corresponding to the sequentially the data The short pulse signal SRB is generated when the bits DINi are data bits representing a program state. The program control signal generator 200 performs a program operation when the short pulse signal SRB is generated by a number corresponding to the number of programmable data bits (eg, 4 bits or less) once. Generate a control signal (ON _fin ) that informs you.

)는 활성화되며, 그 결과 상기 신호 (

)에 제어되는 기입 드라이버 회로 (160)는 상기 데이터 입력 버퍼 회로 (150)로부터 출력된 데이터 비트들에 해당하는 전압 레벨로 상기 열 패스 게이트 회로 (140)을 통해 비트 라인들을 구동하게 된다. 계속해서, 상기 데이터 비트들에 대한 프로그램 동작이 완료됨에 따라 상기 신호 (

)가 비활성화될 때 발생되는 신호 (

)에 의해서 상기 프로그램 제어 신호 발생부 (200)는 초기화된다.When the control signal ON _fin is applied to the program activation signal generating circuit 170, the program activation signal (

) Is activated, resulting in the signal (

The write driver circuit 160, which is controlled by the < RTI ID = 0.0 > 1, < / RTI > Subsequently, as the program operation on the data bits is completed, the signal (

Signal that is generated when) is deactivated

The program control signal generator 200 is initialized.

Referring to FIG. 7, a configuration diagram for describing the data input buffer circuit 150 and the write driver circuit 150 of FIG. 6 in more detail is shown.

)에 동시에 활성화됨에 따라 열 패스 게이트 회로 (140)에 의해서 선택된 비트 라인들을 상기 입출력 포인터 신호 (IOfgi)에 의해서 전달된 데이터 비트들에 대응되는 전압 레벨들로 구동한다.Referring to FIG. 7, the data input buffer circuit 150 includes 16 data input buffers in which data bits DINi, i = 0 to 15 from the outside are applied through input / output pins by a signal nD _lch . Dinbuf0) to (Dinbuf15). The write driver circuit 160 includes write drivers WDi corresponding to the data input buffers Dinbuf0 to Dinbuf15, respectively. The data input buffers Dinbuf0 to Dinbuf15 correspond to the data bits LDi sequentially latched by corresponding input / output pointer signals IOfgi output from the program control circuit 210 of FIG. 6. Output to write drivers (WDi). Subsequently, the write drivers WDi receive the signal from the program activation signal generator 170 of FIG.

As shown in FIG. 2, the bit lines selected by the column pass gate circuit 140 are driven to voltage levels corresponding to the data bits transmitted by the input / output pointer signal IOfgi.

8 is a circuit diagram showing a data input buffer circuit according to a preferred embodiment of the present invention. Referring to FIG. 8, as illustrated in FIG. 7, the data input buffer circuit 150 includes a plurality of data input buffers (Dinbufi) corresponding to the input / output pins, respectively. 150 illustrates only a circuit corresponding to one of the data input buffers DinbufI, but the other buffers have the same configuration.

Referring again to 8, the data input buffer (Dinbufi) comprises a NOR gate (G52), three inverters (IV27), (IV28) and (IV35) which input the corresponding data bits (DINi) and the signal (nCE _f ). ), A first latch 152 controlled by the signal nD _lch and composed of inverters IV29, IV30 and IV31 and a transfer gate G53, and a signal IOfgi and controlled by inverters ( And a second latch 154 consisting of IV32, IV33 and IV34 and a transfer gate G54 and connected to the corresponding write driver WDi via the inverter IV35. The data input buffer Dinbufi having the above configuration _latches the data bit DINi applied from the outside in response to the signal nD _lch in the first latch 152 and then corresponds to the data bit DINi. When the input / output pointer signal IOfgi is activated, the data bits stored in the first latch 152 are transferred to the corresponding write driver WDi through the inverter IV35. Here, the signal nCE _f is applied as a signal for preventing current consumption in standby.

9A and 9B, a circuit diagram showing a circuit configuration of the counter portion in the program control circuit of FIG. 6 is shown. 10 is a circuit diagram showing one counter circuit in the counter 180 of FIG. 9A. As shown in Figs. 9A and 9B, the counting unit 180 is composed of a counter 182 and a decoder 184.

)에 동기된 4 개의 카운터들 (182a), (182b), (182c) 및 (182d)로 구성되며, 상기 카운터들 (182a), (182b), (182c) 및 (182d)은 프로그램 모드를 알리는 신호 (

)의 반전된 신호에 의해서 초기화된다. 상기 카운터들 (182a), (182b), (182c) 및 (182d)은 전단의 카운터 출력의 주기를 2배로 출력하도록 구성되어 있다. 이러한 구성에 의해서, 상기 카운터들 (182a), (182b), (182c) 및 (182d)의 병렬 출력들 (IOp0)∼(IPp3)은, 도 15에 도시된 바와같이, 발진 신호 (OSC)을 기준으로 배주기 신호로서 출력된다.Referring again to FIG. 9A, the counter 182 is an oscillation signal (OSC) and its complementary signal (

It consists of four counters 182a, 182b, 182c and 182d synchronized to the above, and the counters 182a, 182b, 182c and 182d indicate the program mode. signal (

Is initialized by the inverted signal of. The counters 182a, 182b, 182c and 182d are configured to double the period of the counter output of the front end. By this arrangement, the parallel outputs IOp0 to IPp3 of the counters 182a, 182b, 182c and 182d are configured to generate the oscillation signal OSC as shown in FIG. It is output as a cycle signal as a reference.

The counter 182 includes two NAND gates G1 and G2, four transfer gates G3 to G6 and two inverter circuits IV1, as shown in FIG. It consists of (IV2). Since the operation thereof is well known to those who have acquired the general knowledge in this field, the description thereof is omitted.

9B, the decoder 184 receives the signals IOp0 to IPp3 output from the counter 182 and outputs an input / output pointer signal IOfgi for indicating the input / output pins, respectively. Here, the signal IOfgi is activated sequentially in accordance with the toggle of the signal OSC, which is activated first after the signal IOfg0 is activated before the oscillation signal OSC is toggled, as described above. The output signals IOfg1 to IOfg15 are output. The oscillation signal OSC is held in the hold state when the control signal ON _fin is generated, although not shown in the drawing.

The decoder 184 is a binary output from the inverters IV7 to IV22 and the NAND gates G7 to G22 and the counter 182 so as to correspond to the signals IOfg0 to IOfg15. Output signals IOfg0 to IOfg15 that decode the signals IOp0 to IOp3 using inverters IV3 to IV6 for inverting the counter signals IOp0 to IOp3. do. Here, it will be apparent to those skilled in the art that the circuit configuration shown in FIGS. 9A and 9B may be modified differently. Therefore, the circuit configurations as an example thereof are referred to Figs. 9A and 9B.

)로서 출력된다.Referring to FIG. 11, a block diagram showing the configuration of the comparison unit of FIG. 6 is shown. The comparison unit 190 includes a determination unit 192, a pulse generator 194 and two inverters IV23 and IV24. The determination unit 192 receives the data bits DINi applied to the data input buffer circuit 150 and the input / output pointer signal IOfgi that are sequentially activated and output from the counting unit 180. Comparing a pointer signal (IOfgi) with the data bit (DINi) generates a detection signal (Det) that is activated when the data bit (DINi) is a data bit indicating a program state (here, defined as '1'). do. That is, when the signal IO _fg0 is activated, the signal Det that transitions to the high level is output when the corresponding data bit DIN0 indicates a program state (eg, '1'). The pulse generator 194 generates a short pulse signal SRG having a predetermined width when the detection signal Det transitions from a low level to a high level. Subsequently, the short pulse signal SPG is output as the signal SRB through the inverter IV23 and the complementary signal (SB) of the signal SRB through the inverters IV23 and IV24.

Is output as

The determination unit 192 may include NAND gates G23 to G38 that input and output corresponding input / output pointer signals IOfgi and data bits DINi, and NAND corresponding to one group of four from the least significant bit. Four NAND gates G39 to G43 that input the gates G23 to G26, G27 to G30, G31 to G34, and G35 to G38; NOR gates G41 and G44 having two NAND gates G39 and G40 and G42 and G43 of the four NAND gates G39 to G43, And one NAND gate G45 that receives the outputs of the NOR gates G41 and G44.

12 is a block diagram showing a configuration of a program control signal generator of a program control circuit according to the present invention.

)에 동기된 4 개의 플립플롭들 (DFF0)∼(DFF3)에 의해서 순차적으로 오른쪽으로 상기 전원 전압 (Vcc)의 하이 레벨을 이동시키게 된다. 따라서, 상기 신호들 (SRB) 및 (

)이 4 번에 걸쳐 펄스로서 입력되면 상기 쉬프트 레지스터 (SR)의 출력 신호 (ON_fin)는 로우 레벨에서 하이 레벨로 천이된다. 다시말해서, 외부로부터 입력된 데이터 비트들 (DINi)은 상기 비교부 (190)에서 순차적으로 검사되어 프로그램될 데이터로서 논리적으로 '1'의 수가 4 개가 되면 상기 쉬프트 레지스터 (SR)의 출력 신호 (ON_fin)는 하이 레벨이 됨을 알 수 있다. 여기서, 상기 신호 (ON_fin)은 도 6의 프로그램 활성화 신호 발생부 (170)로 인가됨으로써 그것의 출력 신호 (

)가 활성화되고, 그 결과 프로그램 동작이 수행된다.Referring to FIG. 12, the program control signal generator 200 includes four flip-flops DFF0 to DFF3, and is configured by the short pulse signal SRB output from the comparator 190 of FIG. 6. It acts as a shift register (SR) to move right one step at a time. That is, since the input of the shift register SR is a high level which is a power supply voltage Vcc, the resistor SR is the short pulse signal SRB and its complementary signal (

The four flip-flops DFF0 to DFF3 synchronized to the second level sequentially move the high level of the power supply voltage Vcc to the right. Thus, the signals SRB and (

) Is input as a pulse four times, the output signal ON _fin of the shift register SR transitions from a low level to a high level. In other words, the data bits DINi input from the outside are sequentially inspected and programmed in the comparing unit 190, and when the number of logically '1' becomes four, the output signal ON of the shift register SR is ON. _fin ) is high level. Here, the signal ON _fin is applied to the program activation signal generator 170 of FIG.

) Is activated, and as a result, a program operation is performed.

)가 비활성화될 때 발생된 숏 펄스 신호 (

)에 의해서 초기화되며, 도 13에 도시된 바와같이, 각각의 플립플롭들 (DFF0)∼(DFF3)은 도 10의 그것과 동일한 회로 구성을 갖는다.Thus, the program operation is limited to the maximum number of bits to be programmed to four, which means that the memory cell can be programmed even by the operation of the layout-limited charge pump circuit. At this time, the scanning operation on the input / output pointer signal IO _fgi is stopped while the program operation is in progress. Afterwards, the flip-flops DFF0 to DFF3 of the shift register SR receive signals from the program activation signal generator 170 of FIG. 6.

Short pulse signal generated when

13, each of the flip-flops DFF0 to DFF3 has the same circuit configuration as that of FIG.

14 is a flowchart illustrating a program method of a flash memory device according to an exemplary embodiment of the present invention. 15 is a timing diagram showing waveforms of signals for a program operation according to an exemplary embodiment of the present invention. And, Figure 16 is a view for comparing the program performance according to the prior art and the present invention. 14 and 15, the program operation according to the present invention is described below with reference to the reference figures 6 to 13 and 16.

)가 활성화되면, 상기 신호 (

)가 활성화되고 소정 시간이 경과한 후 활성화되는 신호 (nD_lch)에 응답하여 외부로부터 인가되는 데이터 비트들 (DINi)은 각각 대응되는 데이터 입력 버퍼들 (Dinbufi)의 제 1 래치 (152)에 저장된다. 이것은 도 14의 입력 데이터 래치 단계 (S10)에서 수행된다.Program command, i.e., write enable signal (

) Is activated, the signal (

) And the data bits DINi applied from the outside in response to the activated signal nD _lch after a predetermined time elapses are stored in the first latch 152 of the corresponding data input buffers DINbufi, respectively. do. This is done in the input data latch step S10 of FIG.

Subsequently, in the next step S20, scanning of the input / output pointer, that is, the input / output pin starts. That is, the counter 180 of the program control circuit 210 sequentially activates the input / output pointer signal IOfgi representing the input / output pins in response to the oscillation signal OSC. Before the oscillation signal OSC toggles, the signal IOfg0 indicating the input / output pin corresponding to the least significant bit is activated first. Here, as the signal IOfgi is sequentially activated, the data bits LDi latched in the buffer Dinbufi are transferred from the corresponding data input buffer Dinbufi to the corresponding write driver WDi.

Then, the data bits latched in the data input buffers (Dinbufi) in the step (S10) are compared with the signal (IOfgi) sequentially activated in the comparison step (S30). When the data bit is in a program state, the comparator 190 of FIG. 6 generates a short pulse signal SRB.

)을 발생하게 된다.Then, it is determined whether the number of once programmable data bits is equal to a predetermined number (4 in the preferred embodiment), and if the number of programmable data bits is four, the next program operation is performed. That is, as shown in FIG. 6, when the number of data bits is four, a control signal ON _fin for notifying a program operation is generated from the program control signal generator 210. Therefore, the program activation signal generator 170 of FIG. 6 may generate a program activation signal (synchronized with the signal ONfin).

) Will occur.

)가 발생될 때까지 순차적으로 활성화된 상기 신호 (IOfgi)에 제어되는 데이터 입력 버퍼들 (Dinbufi)은 그것에 래치된 데이터 비트들 (LDi)을 대응되는 기입 드라이버들 (WDi)로 출력하기 때문에, 상기 신호 (IOfgi)에 의해서 현재까지 전달된 데이터 비트들에 대응되는 비트 라인들을 프로그램 상태에 대응되는 전압 레벨들로 구동하게 된다. 이로써, 이 분야의 통상적인 지식을 습득한 자들에게 잘 알려진 프로그램 동작이 수행된다.After that, the program activation signal (

Since the data input buffers Dinbufi controlled to the signal IOfgi, which are activated sequentially, outputs the data bits LDi latched thereto to the corresponding write drivers WDi. The bit lines corresponding to the data bits transmitted to date by the signal IOfgi are driven to voltage levels corresponding to the program state. In this way, program operations that are well known to those who have acquired the general knowledge in this field are performed.

)에 동기된 신호 (

)에 의해서 프로그램 제어 신호 발생부 (200)는 초기화된다.Here, while the program operation is performed, although not shown in the figure, the circuit generating the oscillation signal OSC is held by the signal ON _fin , and thus the input / output pointer scanning operation step (S20) during the program operation. ) Is stopped. When the program operation is completed, as shown in FIG. 15, the signal (

Signal synchronized to

), The program control signal generator 200 is initialized.

When a program operation is performed through this series of operations, as shown in FIG. 16, since four program cycles are performed in the conventional case, only three program cycles are performed in the present invention, thereby improving program performance. It can be obvious.

As described above, when the programmable data bits are detected by scanning the data bits to be programmed from the least significant bit, the program performance of the flash memory device may be improved by performing a program operation.

Claims (10)

In a flash memory device, A plurality of bit lines; A cell array including a plurality of memory cells; Each of the memory cells has a floating gate and a control gate, and includes transistors electrically erasable and programmable by accumulating charge or releasing the accumulated charge in the floating gate; Buffers for respectively latching data bits applied from outside in response to the latch signal; Means for generating a program activation signal for performing a program operation; Drivers for driving bit lines corresponding to voltage levels corresponding to the data bits latched in the buffers in response to the program activation signal; Means for sequentially generating an input / output pointer signal representing each of the latched data bits in response to an oscillation signal; The buffers sequentially output data bits latched thereto by the input / output pointer signal to corresponding drivers; Means for generating a short pulse signal when the data bit corresponding to the input / output pointer signal is a data bit indicating a program state; And means for generating a control signal (ON _fin ) for activating said program activation signal generating means when said short pulse signal is generated by one programmable number. The method of claim 1, And the control signal generating means is initialized by a synchronized signal when the program activation signal is deactivated. The method of claim 1, And the latch signal is a signal synchronized with a write activation signal. The method of claim 1, Each of the buffers comprises: a first latch for latching a corresponding data bit in response to the latch signal; And a second latch for receiving and latching the data bit from the first latch in response to the input / output pointer signal. A plurality of bit lines; A cell array including a plurality of memory cells; Each of the memory cells has a floating gate and a control gate, and includes transistors electrically erasable and programmable by accumulating charge or releasing the accumulated charge in the floating gate; Buffers for respectively latching data bits applied from outside in response to the latch signal; Means for generating a program activation signal for performing a program operation; Drivers for driving bit lines corresponding to voltage levels corresponding to the data bits latched in the buffers in response to the program activation signal; The program operation for the one programmable data bits is performed after the one programmable data bits of the data bits representing the program state from the least significant bit are supplied to the corresponding drivers from the least significant bits respectively. Means for controlling buffers and means for generating the program activation signal. The method of claim 5, The program control means, Means for sequentially generating an input / output pointer signal representing each of the latched data bits in response to an oscillation signal; Means for generating a short pulse signal when the data bit corresponding to the input / output pointer signal is a data bit indicating a program state; Means for generating a control signal (ON _fin ) for activating said program activation signal generating means when said short pulse signal is generated by one programmable number, so that said buffers are data latched to it by said input / output pointer signal; Flash memory device to sequentially output the bits to the corresponding driver. The method of claim 6, And the control signal generating means is initialized by a synchronized signal when the program activation signal is deactivated. The method of claim 6, And the latch signal is a signal synchronized with a write enable signal. The method of claim 6, Each of the buffers comprises: a first latch for latching a corresponding data bit in response to the latch signal; And a second latch for receiving and latching the data bit from the first latch in response to the input / output pointer signal. A plurality of bit lines; A cell array including a plurality of memory cells; Buffers for respectively latching data bits applied from outside in response to the latch signal; A program activation signal generation circuit for generating a program activation signal for performing a program operation; A program method of a flash memory device including drivers for driving bit lines corresponding to voltage levels corresponding to the data bits latched in the buffers in response to the program activation signal. Sequentially generating an input / output pointer signal representing each of the latched data bits; Sequentially outputting data bits latched in the buffers to corresponding drivers in response to the input / output pointer signal; Generating a short pulse signal when the data bit corresponding to the input / output pointer signal is a data bit indicating a program state; And generating a control signal (ON _fin ) for activating the program activation signal generating means when the short pulse signal is generated as many as one programmable number to perform a program operation.

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