KR19990012428A - Flash memory device and its programming method - Google Patents

Abstract

A flash memory device according to the present invention includes: a plurality of bit lines; A cell array including a plurality of memory cells; Buffers for respectively latching data bits applied from the outside in response to a latch signal; A circuit for generating a program activation signal for performing a program operation; Drivers for driving bit lines corresponding to the voltage levels corresponding to the data bits latched in the buffers in response to the program enable signal; After the data bits respectively latched in the buffers are supplied from the least significant bit to actuators corresponding to one-time programmable data bits of data bits representing a program state, a program operation for the once programmable data bits is performed Buffers and a circuit for controlling the program activation signal generating circuit.

Description

A flash memory device and its programming method (flash memory device and programming method thereof)

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a flash memory device having electrically erasable and programmable cells and a method of programming the same.

Since a flash memory device is much faster in program and read operations than a nonvolatile semiconductor memory device capable of electrically programming and erasing operations, have. A flash memory device can be classified into a NAND type and a NOR type flash memory device. The cell array of the NOR type flash memory device has a structure in which a plurality of memory cells are arranged in parallel on one bit line while a cell array of the NAND type flash memory device has a structure in which a plurality of memory cells are connected in series As shown in Fig.

Referring to FIG. 1, a cross-sectional view illustrating a structure of a general flash memory cell is shown. As shown in FIG. 1, the flash memory cell includes a source 3 and a drain 4 formed on the surface of a P-type semiconductor substrate 2 with a channel region therebetween and made of N + impurities, A floating gate 6 formed with a thin insulating film 7 therebetween and an insulating film (for example, an ONO film) 9 on the floating gate 6 And a control gate 8 is formed. The source 3, the drain 4, the control gate 8 and the semiconductor substrate 2 are provided with power supply terminals Vs (Vs) for applying voltages required in programming, erasing and reading operations, ), (Vd), (Vg), and (Vb) are connected.

According to the program operation of the conventional flash memory, the flash memory cell is programmed by causing hot electron injection to occur in the floating gate 8 in the channel region adjacent to the drain region 4. The electron injection is performed by grounding the source region 3 and the P-type semiconductor substrate 2, applying a high voltage (for example, + 10V) to the control gate electrode Vg, (For example, 5 V to 6 V) in order to generate hot electrons in the cathode 4. When the flash memory cell is programmed according to the voltage application conditions, that is, when a negative charge is sufficiently accumulated in the floating gate 6, the negative (-) charge accumulated in the floating gate 6 The charge serves to increase the threshold voltage of the programmed flash memory cell during a series of read operations.

Typically, the voltage application condition of the read operation is such that a positive voltage (for example, 1 V) is applied to the drain region 4 of the flash memory cell and a predetermined voltage (for example, A power supply voltage or about 4.5 V), and then applying 0 V to its source region 3. When the read operation is performed according to the above-described conditions, the programmed flash memory cell has its drain voltage increased by the hot electron injection method described above, that is, from its drain region 4 to its source region 3 Current is prevented from being injected. At this time, the programmed flash memory cell is said to be off, and its drain voltage is typically between about 6V and 7V.

Subsequently, the erase operation of the flash memory cell causes F-N tunneling (F-N tunneling) from the semiconductor substrate 2, that is, the bulk region, to the control gate 8, thereby erasing the memory cell. Generally, the FN tunneling is used to apply a negative high voltage (e.g., -10 V) to the control gate 8 and to generate FN tunneling between the bulk region 2 and the control gate 8 By applying a suitable amount of voltage (for example, 5 V). At this time, its drain region 4 is kept in a high impedance state (for example, a floating state) in order to maximize the effect of erasing. Applying voltages according to such erase conditions to corresponding power terminals Vg, Vd, Vs and Vb creates a strong electric field between the control gate 8 and the bulk region 2 do. This causes the F-N tunneling to occur, so that the negative charge in the floating gate 6 of the programmed cell is discharged into its source region 3.

Typically, the F-N tunneling occurs when an electric field of 6 to 7 MV / cm is formed between the insulating films 7. This is possible because the thin insulating film 7 of 100 Å or less is formed between the floating gate 6 and the bulk region 2. The negative charge is discharged (or emitted) from the floating gate 6 to the bulk region 2 by the erase method according to the FN tunneling, because the drain of the erased flash memory cell during the series of read operations It serves to lower the solder voltage.

In a general flash memory cell array configuration, each of the bulk areas is connected together for high integration of the memory device, so that when a cancellation operation is performed according to the above-mentioned erase method, a plurality of memory cells are simultaneously erased . The erase unit is determined according to the area in which each of the bulk areas 2 is separated. (For example, 64 Kbytes: hereinafter referred to as a sector). While a series of read operations are performed, the flash memory cell whose drain threshold voltage is lowered by the erase operation applies a constant voltage to the control gate 8 A current path is formed from the drain region 4 to the source region 3. This flash memory cell is said to be turned on, and its drainsolted voltage has a distribution between about 1V and 3V. Table 1 shows the voltage levels applied to the power supply terminals Vg, Vd, Vs and Vb during programming, erasing and reading operations for the flash memory cell.

[Table 1]

Operation mode Vg Vd Vs Vb program + 10V + 5V to + 6V 0V 0V Bog -10V Floating Floating + 5V Reading + 4.5V + 1V 0V 0V

2 is a view showing a state of a memory cell during a program operation. In general, the program operation is performed in a memory cell in which the number of bits that can be programmed at one time due to the large amount of current (e.g., 400 [mu] A) flowing from the drain terminal to the connected source terminal, to which about 5 volts of power is applied (I.e., 8 bits) or word units (i.e., 16 bits). 3.2mA (400μA × 8) current is consumed when the program is executed in byte unit, and 6.4mA (400μA × 16) is consumed when the program is executed in word unit.

However, in order to generate a voltage of about 5 V applied to the drain terminal of the memory cell during the program operation by using the pump circuit inside the chip, a large number of charge pump circuits (also referred to as an internal drain pump) Is required. In this case, as the number of charger pump circuits increases, the layout area of the chip increases. Also, due to the operation of the circuit for driving the charger pump circuit, a large amount of active current flowing from the power supply voltage to the ground potential is generated.

Therefore, in order to solve such a problem, a technology for performing a program operation four times in 4-bit units to program one word has been developed by advanced micro devices (AMD) in a 96 VLSI circuit of A 2.7 V only 8 Mb × 16 NOR Flash Memory (p172-p173). However, when the program operation is performed using the techniques disclosed in the above document, the program performance is deteriorated. Therefore, in order to solve this problem again, AMD has proposed a special program algorithm.

Referring to FIG. 3, a block diagram illustrating a configuration of a conventional flash memory device using such a program algorithm is shown. The data input buffers Dinbuf0 to Dinbuf15 store the program data bits corresponding to the external input / output pins I / O0 to I / O15, respectively, And determines whether to apply a positive program voltage to the drain terminal of the selected memory cell. The data input buffers Dinbuf0 to Dinbuf15 are divided into four groups. The groups are selected by the program activation signals S0 to S3 generated in the program control state machine 10.

In addition, three (low byte) detectors, (word detectors) 12, (14) and (16) are connected to the data input buffers Dinbuf0 to Dinbuf15 / RTI > is used to control the number of bits to be programmed to optimize the program time. If the number of bits to be programmed is 4 or less, the output signals 4bdetL, 4bdetH and 4bdetW of the detectors 12-16 are all set to high level, All remain at a low level.

4, there is shown a diagram for illustrating the concept of the output signals 4bdetL, 4bdetH, and 4bdetW of the detectors 12, 14, and 16. 5 is a diagram showing changes in the program activation signal according to all possible word program conditions.

The program control status device 10 receives the program activation signals S0 to S6 by receiving the outputs 4bdetL, 4bdetH and 4bdetW of the detectors 12, 14, S3. If all of the output signals 4bdetL, 4bdetH and 4bdetW of the detectors 12 to 16 are low level, a low byte and a high byte Each of which includes at least four data bits to be programmed. At this time, the device 10 activates the program activation signals S0 to S3 according to a proper timing sequence. If the output signals 4bdetL, 4bdetH and 4bdetW of the detectors 12, 14 and 16 are at the high level, the sum of the lower byte and the upper byte together, Quot; means that there are four or less. At this time, the device 10 simultaneously activates (S0) to (S3).

In order to compensate for the ramp-up time of the charger pump circuit, the initial pulse is maintained as long as 4.8 mu s as shown in Fig. 5, and the program which is the output of the charger pump circuit After reaching the proper amount of voltage, the next pulse is maintained at about 2.6 μs. That is, the program pulse may vary from 4.8 μs to 12.6 μs depending on the pattern type. The above description has a maximum program time of 16 μs including a program verify time of 3.4 μs and another overhead time. Thus, according to the above-described conventional programming method, at least four data bits to be programmed are included in the lower bytes I / O0 to I / O7 and the upper bytes I / O8 to I / The program operation of the entire flash memory device is deteriorated because the program operation must be performed four times.

It is therefore an object of the present invention to provide a flash memory device with improved program performance and a program method thereof.

1 is a cross-sectional view showing the structure of a general flash memory cell;

FIG. 2 illustrates a state of a memory cell during a program operation; FIG.

3 is a block diagram showing a configuration of a conventional NOR flash memory device;

4 is a diagram illustrating a concept of output signals of the detectors of FIG. 3;

5 is a diagram showing changes in a program activation signal according to all possible word program conditions;

6 is a block diagram showing the configuration of a NOR flash memory device according to the present invention;

FIG. 7 is a block diagram showing a detailed configuration of the data input buffer circuit and the write driver circuit of FIG. 6; FIG.

FIG. 8 is a circuit diagram showing a data input buffer circuit according to a preferred embodiment of the present invention; FIG.

9A and 9B are circuit diagrams showing a circuit configuration of a coefficient section in the program control circuit of Fig. 6;

FIG. 10 is a circuit diagram showing one counter circuit in the counting portion of FIG. 9A; FIG.

11 is a block diagram showing the configuration of the comparison unit of FIG. 6;

12 is a block diagram showing a configuration of a program control signal generating unit of the program control circuit according to the present invention;

13 is a circuit diagram showing a detailed circuit of the flip-flop of FIG. 12;

FIG. 14 is a flow chart showing a programming method of a flash memory device according to a preferred embodiment of the present invention; FIG.

15 is an operation timing diagram showing the timing of signals for a program operation according to a preferred embodiment of the present invention;

16 is a diagram for comparing program performance according to the related art and the present invention,

DESCRIPTION OF REFERENCE NUMERALS

100: cell array 110: row and column address buffer

120: row decoder 130: column decoder

140: thermal pass gate circuit 150: data input buffer circuit

160: write driver circuit 170: program activation signal generating circuit

180: counting section 190: comparing section

200: a program control signal generator 210: a program control circuit

According to an aspect of the present invention, there is provided a flash memory device including: a plurality of bit lines; A cell array including a plurality of memory cells; Each of the memory cells having a floating gate and a control gate and including electrically erasable and programmable transistors by accumulating charge on the floating gate or discharging the accumulated charge; Buffers for respectively latching data bits applied from the outside in response to a latch signal; Means for generating a program activation signal for performing a program operation; Drivers for driving bit lines corresponding to the voltage levels corresponding to the data bits latched in the buffers in response to the program enable signal; Means for sequentially generating an input / output pointer signal representative of said latched data bits in response to an oscillating signal; The buffers sequentially output the data bits latched in the input / output pointer signal to the corresponding driver; Means for generating a short pulse signal when a data bit corresponding to the input / output pointer signal is a data bit representing a program state; And means for generating a control signal (ON _fin ) for activating the program activation signal generating means when the short pulse signal is generated by a one-time programmable number.

In this embodiment, the control signal generating means is initialized by a signal synchronized when the program activation signal is inactivated.

In this embodiment, the latch signal is a signal synchronized with the write enable signal.

In this embodiment, each of the buffers comprises: a first latch for latching a corresponding data bit in response to the latch signal; And a second latch for receiving and latching the data bit from the first latch in response to the input / output pointer signal.

According to another aspect of the present invention, there is provided a semiconductor memory device including: a plurality of bit lines; A cell array including a plurality of memory cells; Each of the memory cells having a floating gate and a control gate and including electrically erasable and programmable transistors by accumulating charge on the floating gate or discharging the accumulated charge; Buffers for respectively latching data bits applied from the outside in response to a latch signal; Means for generating a program activation signal for performing a program operation; Drivers for driving bit lines corresponding to the voltage levels corresponding to the data bits latched in the buffers in response to the program enable signal; After the data bits respectively latched in the buffers are supplied from the least significant bit to actuators corresponding to one-time programmable data bits of data bits representing a program state, a program operation for the once programmable data bits is performed Buffers and means for controlling the program activation signal generating means.

In this embodiment, the program control means comprises: means for sequentially generating an input / output pointer signal each representing the latched data bits in response to an oscillating signal; Means for generating a short pulse signal when a data bit corresponding to the input / output pointer signal is a data bit representing a program state; And means for generating a control signal (ON _fin ) for activating the program activation signal generating means when the short pulse signal is generated by a one-time programmable number, wherein the buffers are provided with data So that the bits are sequentially output to the corresponding drivers.

In this embodiment, the control signal generating means is initialized by a synchronized signal when the program activating signal is inactivated.

In this embodiment, the latch signal is a signal synchronized with the write enable signal.

In this embodiment, each of the buffers comprises: a first latch for latching a corresponding data bit in response to the latch signal; And a second latch for receiving and latching the data bits from the first latch in response to the input / output pointer signal.

According to another aspect of the present invention, there is provided a semiconductor memory device including: a plurality of bit lines; A cell array including a plurality of memory cells; Buffers for respectively latching data bits applied from the outside in response to a latch signal; A program activation signal generating circuit for generating a program activation signal for performing a program operation; And a driver for driving bit lines corresponding to the voltage levels corresponding to the data bits latched in the buffers in response to the program enable signal, the method comprising: Sequentially generating an input / output pointer signal indicating the input / output pointer signal; Sequentially outputting the data bits latched in the buffers to the corresponding driver in response to the input / output pointer signal; Generating a short pulse signal when a data bit corresponding to the input / output pointer signal is a data bit indicating a program state; And generating a control signal (ON _fin ) for activating the program activation signal generating means when the number of the short pulse signals is once programmable, thereby performing a program operation.

With such an apparatus and method, it is possible to control so that only the bits of the program state from the least significant bit of the data bits latched in the data buffers are transferred to the corresponding write drivers.

Reference will now be made in detail to the preferred embodiments of the present invention with reference to the accompanying drawings.

Referring to FIG. 6, the novel flash memory device of the present invention provides a program controlling circuit 210, which receives data bits latched in buffers Dinbufi, (DINi) to the corresponding drivers (WDi) after the data bits of the program state that are once programmable from the least significant bit of the data bits DINi, And generates a control signal (ON _fin ) for controlling the signal generating circuit 170. The program activation signal generating circuit 170 is controlled by the program control signal ON _{fin to} generate a program activation signal for activating the drivers WDi ) To perform the program operation. This improves the program performance of the flash memory device.

Referring to FIG. 6, a block diagram illustrating a configuration of a flash memory device according to the present invention is shown. The flash memory device of the present invention includes a memory cell array 100, a row and column address buffer circuit 110, a row decoder 120, a column decoder a column decoder 130, a Y-pass gate circuit 140, a data input buffer circuit 150, a write driver circuit 160, A program enable signal generating circuit 170, and a program control circuit 210. [

The memory cell array 100, the row and column address buffer circuit 110, the row decoder 120, the column decoder 130 and the thermal pass gate circuit 140 are well known to those skilled in the art. As is known, descriptions thereof are omitted here.

The data input buffer circuit 150 _latches externally applied data bits DINi (where i = 0 to 15) through input / output pins (not _shown ) in response to the signal nD1ch. Here, the signal nD _lch is a write enable signal ). That is, the signal (nD _lch ) Is activated and is activated after a predetermined time has elapsed and the ( Lt; / RTI > is deactivated. The data input buffer circuit 150 sequentially outputs the stored data bits to the write driver circuit 160 according to the input / output pointer signal IO _fgi output from the program control circuit 210.

The write driver circuit 160 receives the data bits DINi sequentially output from the data input buffer circuit 150, The bit lines selected by the column pass gate circuit 140 are driven to voltage levels corresponding to the data bits.

The program control circuit 210 divides the data bits DINi latched in the data input buffers into a programmable group of data bits representing a program state from the least significant bit to correspond to the data bits of the group And controls the data input buffer circuit 150 and the program activation signal generation circuit 170 such that bit lines to be programmed are driven at voltage levels corresponding to the data bits. The program control circuit 210 includes a count section 180, a comparating section 190, and a program control signal generating section 200.

The counting unit 180 generates the input / output pointer signal IO _fgi for indicating the input / output pins in response to the oscillation signal OSC, and outputs a signal ). The input / output pointer signal IO _fgi has a characteristic of being sequentially activated as binary data bits according to the oscillation signal OSC from an input / output pin associated with the least significant bit. In addition, the data input buffer circuit 150 to which the signal IO _fgi is applied outputs the data bits latched in the corresponding data input buffer to the corresponding write driver when the signal IO _fgi is activated. An explanation thereof will be described later.

Subsequently, the comparison section 190 compares the input and output pointer signal (IO _fgi) the data bits (DINi) and the output pointer signal (IO _fgi) latched to the output buffer corresponding to the sequentially the data And generates a short pulse signal SRB when the bits DINi are data bits representing a program state. When the short pulse signal SRB is generated by a number corresponding to the number of data bits that can be programmed once (for example, 4 bits or less), the program control signal generator 200 performs a program operation And generates a control signal (ON _fin ) indicating the ON state.

When the control signal (ON _fin ) is applied to the program activation signal generation circuit 170, the program activation signal Is activated, and as a result the signal ) Drives the bit lines through the thermal pass gate circuit 140 at a voltage level corresponding to the data bits output from the data input buffer circuit 150. [ Subsequently, as the program operation for the data bits is completed, the signal ) ≪ / RTI > The program control signal generator 200 is initialized.

Referring to FIG. 7, a configuration diagram for illustrating the data input buffer circuit 150 and the write driver circuit 150 of FIG. 6 in more detail is shown.

7, the data input buffer circuit 150 is a signal _(lch nD) 16 of the data input buffer data bits from the outside (DINi, i = 0~15) is applied through the input-output pins by the ( Dinbuf0 to Dinbuf15. The write driver circuit 160 includes write drivers WDi corresponding to the data input buffers Dinbuf0 to Dinbuf15, respectively. The data input buffers Dinbuf0 to Dinbuf15 latch the data bits LDi sequentially latched by the corresponding input / output pointer signals IOfgi output from the program control circuit 210 of FIG. And outputs it to the write drivers WDi. Subsequently, the write drivers WDi receive signals (see FIG. 6) from the program activation signal generator 170 And drives the bit lines selected by the thermal pass gate circuit 140 to the voltage levels corresponding to the data bits transferred by the input / output pointer signal IOfgi.

8 is a circuit diagram showing a data input buffer circuit according to a preferred embodiment of the present invention. Referring to FIG. 8, the data input buffer circuit 150 includes a plurality of data input buffers (Dinbufi) corresponding to input / output pins, as shown in FIG. 7, 150 only illustrate circuits corresponding to one of the data input buffers Dinbuf1, but the remaining buffers have the same configuration.

Referring again to FIG. 8, the data input buffer Dinbufi includes NOR gate G52 having a corresponding data bit DINi and a signal nCE _f as input, three inverters IV27, IV28, and IV35 ), to be controlled to the signal (nD _lch) inverters (IV29), (IV30) and (IV31), and a transfer gate (G53) to the configured first is controlled to first latch 152, and signal (IOfgi) inverter ( And a second latch 154 formed of a transfer gate G54 and a transfer driver WDi through the inverter IV35. The data input buffer Dinbufi having such a configuration _latches the data bit DINi applied from the outside in response to the signal nDlch to the first latch 152 and then outputs the data bit DINi corresponding to the data bit DINi The data bits stored in the first latch 152 are transferred to the corresponding write driver WDi through the inverter IV35 when the input / output pointer signal IOfgi is activated. Here, the signal nCE _f is applied as a signal to prevent current consumption during standby.

Referring to Figs. 9A and 9B, a circuit diagram showing a circuit configuration of a coefficient section in the program control circuit of Fig. 6 is shown. FIG. 10 is a circuit diagram showing one counter circuit in the counting unit 180 of FIG. 9A. As shown in FIGS. 9A and 9B, the counting unit 180 includes a counter 182 and a decoder 184.

Referring again to FIG. 9A, the counter 182 receives the oscillation signal OSC and its complementary signal The counters 182a, 182b, 182c, and 182d are made up of four counters 182a, 182b, 182c, and 182d that are synchronized to the program mode signal ( ) ≪ / RTI > The counters 182a, 182b, 182c, and 182d are configured to output twice the cycle of the counter output of the previous stage. With this arrangement, the parallel outputs IOp0 to IPp3 of the counters 182a, 182b, 182c and 182d are set to the oscillation signal OSC as shown in Fig. And output as a multiplication signal based on the reference.

The counter 182 includes two NAND gates G1 and G2 as well as four transfer gates G3 to G6 and two inverter circuits IV1 and G2, (IV2). The operation thereof is well known to those of ordinary skill in the art, so an explanation thereof is omitted.

9B, the decoder 184 receives the signals IOp0 through IPp3 output from the counter 182 and outputs an input / output pointer signal IOfgi for indicating the input / output pins, respectively. Here, as described above, the signal IOfgi is activated first before the oscillation signal OSC is toggled, and then sequentially activated according to the following toggle of the signal OSC, And outputs the signals IOfg1 to IOfg15. The oscillation signal OSC is held in a hold state when the control signal ON _fin is generated, although it is not shown in the figure.

The decoder 184 outputs the inverters IV7 to IV22 and the NAND gates G7 to G22 corresponding to the signals IOfg0 to IOfg15 and the binary And outputs signals IOfg0 to IOfg15 obtained by decoding the signals IOp0 to IOp3 using inverters IV3 to IV6 for inverting the counter signals IOp0 to IOp3 do. It will be apparent to those skilled in the art that the circuit configurations shown in Figs. 9A and 9B can be modified differently. Therefore, referring to Figs. 9A and 9B, a circuit configuration as an example thereof.

Referring to Fig. 11, there is shown a block diagram showing the configuration of the comparison unit of Fig. The comparator 190 includes a discriminator 192, a pulse generator 194 and two inverters IV23 and IV24. The determination unit 192 receives the data bits DINi applied to the data input buffer circuit 150 and the input / output pointer signal IOfgi sequentially output from the counting unit 180, A pointer signal IOfgi is compared with the data bit DINi to generate a detection signal Det which is activated when the data bit DINi is a data bit representing a program state (herein, defined as '1') do. That is, when the signal IO _fg0 is activated, it outputs the signal Det which transits to the high level when the corresponding data bit DIN0 indicates the program state (for example, '1'). The pulse generator 194 generates a short pulse signal SRG having a predetermined width when the detection signal Trans is transitioned from a low level to a high level. Subsequently, the short pulse signal SPG is output as a signal SRB through the inverter IV23, and the complementary signal of the signal SRB through the inverters IV23 and IV24 .

The determination unit 192 includes NAND gates G23 to G38 for receiving the input / output pointer signal IOfgi and the data bit DINi, Four NAND gates G39 to G43 which are supplied with the gates G23 to G26, G27 to G30, G31 to G34 and G35 to G38 as inputs, NOR gates G41 and G44 which receive two NAND gates G39 and G40 among the four NAND gates G39 to G43 as inputs and G42 and G43, And one NAND gate G45 for receiving the outputs of the NOR gates G41 and G44.

12 is a block diagram showing the configuration of a program control signal generator of the program control circuit according to the present invention.

12, the program control signal generator 200 includes four flip-flops DFF0 to DFF3 and is controlled by the short pulse signal SRB output from the comparator 190 of FIG. 6 And operates as a shift register (SR) for shifting to the right by one step. That is, since the input of the shift register SR is a high level which is the power supply voltage Vcc, the register SR outputs the short pulse signal SRB and its complementary signal The high level of the power supply voltage Vcc is sequentially shifted to the right by the four flip-flops DFF0 to DFF3 synchronized with the flip-flops DFF0 to DFF3. Therefore, the signals SRB and Is input as a pulse over four times, the output signal (ON _fin ) of the shift register SR transitions from a low level to a high level. In other words, the data bits DINi input from the outside are sequentially checked by the comparator 190 and the data to be programmed is written into the shift register SR when the number of logical '1' _fin ) is at a high level. Here, the signal ON _fin is applied to the program activation signal generator 170 of FIG. 6 so that its output signal Is activated, and as a result, the program operation is performed.

Thus, the program operation is limited to four maximum number of bits to be programmed, which means that the memory cell can be programmed by the operation of the charger pump circuit limited in layout. At this time, while the program operation is being performed, the scanning operation for the input / output pointer signal IO _fgi is stopped. Then, the flip-flops DFF0 to DFF3 of the shift register SR receive the signal (see FIG. 6) from the program activation signal generator 170 ) Is deactivated, the short pulse signal ( ). As shown in FIG. 13, each of the flip-flops DFF0 to DFF3 has the same circuit configuration as that of FIG.

14 is a flowchart showing a programming method of a flash memory device according to a preferred embodiment of the present invention. 15 is a timing chart showing waveforms of signals for a program operation according to a preferred embodiment of the present invention. FIG. 16 is a diagram for comparing program performance according to the related art and the present invention. Referring to Figs. 14 and 15, the program operation according to the present invention will be described below with reference to Figs. 6 to 13 and Fig.

A program command, that is, a write enable signal ( Is activated, the signal < RTI ID = 0.0 > Is applied to the first latch 152 of the corresponding data input buffers _Dinbufi in response to a signal _nD1ch which is activated after a predetermined time has elapsed, do. This is performed in the input data latching step S10 of Fig.

Subsequently, in the next step S20, scanning of the input / output pointers, that is, the input / output pins, starts. That is, the counting unit 180 of the program control circuit 210 sequentially activates the input / output pointer signal IOfgi indicating the input / output pins in response to the oscillation signal OSC. The signal IOfg0 indicating the input / output pin corresponding to the least significant bit is first activated before the oscillation signal OSC is toggled. As the signal IOfgi is sequentially activated, the data bits LDi latched in the buffer Dinbufi are transferred from the corresponding data input buffer Dinbufi to the corresponding write driver WDi.

Then, the data bits latched in the data input buffers Dinbufi in the step S10 are compared with the signal IOfgi sequentially activated in the comparison step S30. When the data bit is in a program state, the comparator 190 of FIG. 6 generates a short pulse signal SRB.

If the number of programmable data bits is equal to a predetermined number (4 in the preferred embodiment), the program operation of the next step is performed if the number of programmable data bits is four. 6, if the number of data bits is four, a control signal (ON _fin ) for notifying the program operation is generated from the program control signal generation unit 210. [ Therefore, the program activation signal generator 170 of FIG. 6 generates the program activation signal (FIG. 6) synchronized with the signal ONfin ).

Thereafter, the program activation signal ( Since the data input buffers Dinbufi controlled to the sequentially activated signal IOfgi output the data bits LDi latched thereto to the corresponding write drivers WDi, The bit lines corresponding to the data bits transmitted to the present by the signal IOfgi are driven at the voltage levels corresponding to the program state. Thus, program operations well known to those of ordinary skill in the art are performed.

Since the circuit generating the oscillation signal OSC is held in the hold state by the signal ON _fin during the program operation, although not shown in the figure, the input / output pointer scanning operation step S20 ) Is stopped. When the program operation is completed, as shown in FIG. 15, ) ≪ / RTI > The program control signal generator 200 is initialized.

When the program operation is performed through such a series of operations, as shown in FIG. 16, four program cycles are performed in the conventional case, whereas in the present invention, only three program cycles are performed. It is obvious that it can be.

As described above, when the data bits to be programmed are scanned from the least significant bit and the once programmable data bits are detected, the program performance of the flash memory device can be improved by performing the program operation.

Claims (10)

In a flash memory device, A plurality of bit lines; A cell array including a plurality of memory cells; Each of the memory cells having a floating gate and a control gate and including electrically erasable and programmable transistors by accumulating charge on the floating gate or discharging the accumulated charge; Buffers for respectively latching data bits applied from the outside in response to a latch signal; Means for generating a program activation signal for performing a program operation; Drivers for driving bit lines corresponding to the voltage levels corresponding to the data bits latched in the buffers in response to the program enable signal; Means for sequentially generating an input / output pointer signal representative of said latched data bits in response to an oscillating signal; The buffers sequentially output the data bits latched in the input / output pointer signal to the corresponding driver; Means for generating a short pulse signal when a data bit corresponding to the input / output pointer signal is a data bit representing a program state; And means for generating a control signal (ON _fin ) for activating the program activation signal generating means when the short pulse signal is generated by a one-time programmable number. The method according to claim 1, Wherein the control signal generating means is initialized by a synchronized signal when the program activation signal is inactivated. The method according to claim 1, Wherein the latch signal is a signal synchronized with the write enable signal. The method according to claim 1, Each of the buffers comprising: a first latch for latching a corresponding data bit in response to the latch signal; And a second latch for receiving and latching the data bits from the first latch in response to the input / output pointer signal. A plurality of bit lines; A cell array including a plurality of memory cells; Each of the memory cells having a floating gate and a control gate and including electrically erasable and programmable transistors by accumulating charge on the floating gate or discharging the accumulated charge; Buffers for respectively latching data bits applied from the outside in response to a latch signal; Means for generating a program activation signal for performing a program operation; Drivers for driving bit lines corresponding to the voltage levels corresponding to the data bits latched in the buffers in response to the program enable signal; After the data bits respectively latched in the buffers are supplied from the least significant bit to actuators corresponding to one-time programmable data bits of data bits representing a program state, a program operation for the once programmable data bits is performed Buffers and means for controlling the program activation signal generating means. 6. The method of claim 5, Wherein the program control means comprises: Means for sequentially generating an input / output pointer signal representative of said latched data bits in response to an oscillating signal; Means for generating a short pulse signal when a data bit corresponding to the input / output pointer signal is a data bit representing a program state; And means for generating a control signal (ON _fin ) for activating the program activation signal generating means when the short pulse signal is generated by a one-time programmable number, wherein the buffers are provided with data And sequentially output the bits to a corresponding driver. The method according to claim 6, Wherein the control signal generating means is initialized by a synchronized signal when the program enable signal is inactivated. The method according to claim 6, Wherein the latch signal is a signal synchronized with a write enable signal. The method according to claim 6, Each of the buffers comprising: a first latch for latching a corresponding data bit in response to the latch signal; And a second latch for receiving and latching the data bits from the first latch in response to the input / output pointer signal. A plurality of bit lines; A cell array including a plurality of memory cells; Buffers for respectively latching data bits applied from the outside in response to a latch signal; A program activation signal generating circuit for generating a program activation signal for performing a program operation; And a driver for driving bit lines corresponding to the voltage levels corresponding to the data bits latched in the buffers in response to the program enable signal, Sequentially generating input / output pointer signals each representing the latched data bits; Sequentially outputting the data bits latched in the buffers to the corresponding driver in response to the input / output pointer signal; Generating a short pulse signal when a data bit corresponding to the input / output pointer signal is a data bit indicating a program state; Generating a control signal (ON _fin ) for activating the program activation signal generating means when the short pulse signal is generated by a number that can be programmed once, thereby performing a program operation.