CN114203242A - NOR type flash memory programming circuit - Google Patents
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- CN114203242A CN114203242A CN202111459053.6A CN202111459053A CN114203242A CN 114203242 A CN114203242 A CN 114203242A CN 202111459053 A CN202111459053 A CN 202111459053A CN 114203242 A CN114203242 A CN 114203242A
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- 239000002784 hot electron Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 230000005641 tunneling Effects 0.000 description 4
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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Abstract
The invention discloses a NOR flash memory programming circuit, which comprises a power supply voltage detection circuit, a charge pump output end and a charge pump output end, wherein the power supply voltage detection circuit is used for detecting the programming working power supply voltage of the charge pump output end; the address decoding unit is used for selecting a memory unit needing programming operation in the NOR-type memory array and providing a current channel from the output end of the charge pump to the memory unit needing programming; the higher the real-time programming working power supply voltage is, the larger the maximum allowable connection quantity of current channels from the charge pump output end of the address decoding unit to the bit line of the storage unit needing programming corresponding to the same word line in one programming pulse is. The NOR flash memory programming circuit can reduce the area of a chip and can effectively program the NOR flash memory even if the voltage of a programming working power supply connected to the input end of a charge pump is greatly changed.
Description
Technical Field
The present invention relates to semiconductor circuit technology, and more particularly, to a NOR flash memory programming circuit.
Background
NOR FLASH and NAND FLASH use Floating Gate field effect transistor (Floating Gate FET) as basic memory cell to store data, the Floating Gate FET has 4 terminal electrodes, which are Source, Drain, Control Gate and Floating Gate, respectively, the first 3 terminal electrodes are the same as common MOSFET, the difference is only Floating Gate, FLASH uses whether Floating Gate stores charge to represent digit 0 ' and ' 1 ', when charge is injected into Floating Gate, there is conducting channel between D and S, reading from D electrode to ' 0 '; when there is no charge in the floating gate, there is no conducting channel between D and S, reading a '1' from the D pole.
In FLASH memory, two common techniques for injecting charge into a floating gate are hot electron injection (hot electron injection) and F-N tunneling (Fowler Nordheim tunneling); techniques for removing charge from a floating gate typically use F-N tunneling (Fowler Nordheim tunneling).
The write operation is a process of injecting charge into the floating gate, NOR FLASH injects charge into the floating gate by hot electron injection (this method has low charge injection efficiency and therefore the write rate of NOR FLASH is low), and NAND FLASH injects charge into the floating gate by F-N tunneling. Before writing operation, the FLASH must erase the original data (i.e. remove the charge in the floating gate), i.e. read out after FLASH erase is '1'.
The erase operation is the process of removing charge from the floating gate, and both NOR FLASH and NAND FLASH remove the charge from the floating gate by F-N tunneling.
During reading operation, the voltage applied on the control gate is very small, the charge quantity in the floating gate cannot be changed, namely, the original data in the FLASH cannot be changed during reading operation, namely, when the floating gate has charges, a conductive channel exists between the D electrode and the S electrode, and 0' is read from the D electrode; when there is no charge in the floating gate, there is no conducting channel between D and S, reading a '1' from the D pole.
In the NOR FLASH structure, the basic memory cells under each Bit Line (Bit Line) are connected in parallel, and when a Word Line (Word Line) is selected, the Word Line can be read, that is, Bit reading (Random Access) can be realized, and the NOR FLASH memory has a high reading rate. This parallel architecture determines many of the characteristics of NOR FLASH. (1) The parallel structure of the basic storage unit determines that the metal wire occupies a large area, so that the NOR FLASH has low storage density and cannot be applied to application occasions requiring large-capacity storage, namely code-storage and data-storage. (2) The parallel structure of the basic memory cells determines that the NOR FLASH has the characteristics that the memory cells can be independently addressed and the reading efficiency is high, so that the NOR FLASH is suitable for code-storage, and a program can directly run in the NOR (namely, the NOR FLASH has the characteristics of a RAM). (3) NOR FLASH writes use hot electron injection and are less efficient, and therefore NOR write rates are lower and are not suitable for frequent erase/write applications.
NOR FLASH (NOR FLASH) memory devices are widely used in products such as mobile phones, palm top computers, home appliances, automobiles, and the like. The NOR FLASH storage device is different in application scenes and does not work under a fixed voltage, the voltage range is generally 1.6V-3.6V, and the driving capability of the charge pump drive during programming can cover the requirements under different voltages. At a high supply voltage, the drive capability of the charge pump is relatively sufficient due to the relatively high voltage, and at a low supply voltage, the drive capability of the charge pump is deteriorated at the same stage number as the charge pump. So we typically design the charge pump with the worst drive capability at design time.
In a conventional NOR FLASH memory device, a programming method generally employs a channel-hot-electron programming mechanism (channel-hot-electron programming mechanism) for programming, and each memory cell consumes about 100uA of programming current during programming. One-time programming generally adopts a Word (16bits) mode for programming. In order to satisfy the requirement of programming even at a low voltage, the driving capability of the charge pump for programming must satisfy the driving capability of 16 × 100uA ═ 1.6mA, so that effective programming can be performed.
For a particular charge pump, its minimum drive capability is fixed at a certain voltage condition. Then at different voltages there is a different minimum drive capability. As shown in fig. 1, which is an example of a curve of the minimum driving capability of the charge pump for different programming power supply voltages, under the lowest power supply voltage of 1.6V, the programming charge pump also needs to provide at least 1.6mA of working current (assuming that one bit needs 100uA of working current calculation, 16bits are programmed at the same time), but under a high power supply working voltage, the charge pump is in an overdrive state, consuming more power supply charges. Due to the charge pump with large driving capability, a large area needs to be consumed, the area of a chip is wasted, and the production cost of the chip is increased.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a NOR flash memory programming circuit, which can reduce the chip area and can effectively program a NOR flash memory even if the programming operation power supply voltage connected to the input terminal of a charge pump is greatly changed.
In order to solve the above technical problem, the NOR flash memory programming circuit provided by the present invention comprises a power supply voltage detection circuit, a charge pump, an address decoding unit, and a programming control circuit;
the power supply voltage detection circuit is used for detecting the programming working power supply voltage at the input end of the charge pump;
the address decoding unit is used for selecting a memory cell needing programming operation in the NOR type memory array and providing a current channel from the output end of the charge pump to the memory cell needing programming;
the programming control circuit controls the maximum allowable connection quantity of the charge pump output end of the address decoding unit to the current channel of the bit line of the storage unit which corresponds to the same word line and needs to be programmed according to the real-time programming working power supply voltage of the charge pump input end detected by the power supply voltage detection circuit in a one-time programming pulse, namely, the maximum allowable connection quantity of the storage unit which corresponds to the same word line and is programmed is controlled, the higher the real-time programming working power supply voltage is, the larger the maximum allowable connection quantity of the charge pump output end of the address decoding unit to the current channel of the bit line of the storage unit which corresponds to the same word line and needs to be programmed is in the one-time programming pulse, namely, the more the maximum allowable quantity of the storage unit which corresponds to the same word line and is programmed in the one-time programming pulse.
Preferably, the current channel includes a voltage regulator for regulating the level of the programming voltage output by the charge pump to the bit line of the memory cell to be programmed.
Preferably, if the maximum allowable number in one programming pulse is smaller than the maximum number of memory cells to be programmed at the time corresponding to the same word line, in one programming pulse, the maximum allowable number of memory cell bit lines to be programmed at the time corresponding to the word line are programmed at first, and then in the next or more than one subsequent programming pulse, other memory cells to be programmed, which are not programmed at the maximum allowable number or are smaller than the maximum allowable number, corresponding to the word line are sequentially controlled to be programmed until all the memory cells to be programmed at the time corresponding to the word line are programmed.
Preferably, the programming working power supply voltage is divided into M +2 intervals from low to high; the 0 th interval is smaller than the rated lowest programming working power supply voltage, and the M +1 th interval is larger than the rated highest programming working power supply voltage;
the memory cells which correspond to the same word line and need to be programmed sequentially have M groups, the M group has N or less than N memory cells, and N, M are positive integers;
in one programming pulse, when the real-time programming working power supply voltage at the input end of the charge pump is in the ith interval, the programming control circuit switches on a current channel from the output end of the charge pump of the address decoding unit to a bit line of a storage unit needing programming corresponding to the 1 st group to the ith group of the word line, wherein i is a positive integer less than or equal to M; and in the next programming pulse, controlling and switching on current channels from the output end of the charge pump of the address decoding unit to the bit lines of the rest storage units which are required to be programmed and correspond to other groups of the word lines according to the real-time programming working power supply voltage, wherein the number of the current channels switched on by the bit lines each time is i × N or a positive integer smaller than i × N.
Preferably, N is an even number.
Preferably, the programming control circuit outputs a low voltage alarm signal when the real-time programming working power supply voltage at the input end of the charge pump is in the 0 th interval.
Preferably, the programming control circuit outputs the high-voltage warning signal when the real-time programming working power supply voltage at the input end of the charge pump is in the (M + 1) th interval.
The NOR type flash memory programming circuit dynamically adjusts the maximum allowable number of the memory cells corresponding to the same word line which can be programmed in one programming pulse according to different programming working power supply voltages, thereby fully utilizing the driving capability of the programming charge pump when the programming working power supply voltage is higher, not sacrificing the chip programming time when the programming working power supply voltage is higher, achieving the effect of the same programming practice under the smaller charge pump area, and achieving the purpose of reducing the area of the programming charge pump and the chip; when the programming working power supply voltage is lower, the maximum allowable number of the storage units corresponding to the same word line which can be programmed in one programming pulse is reduced through dynamic adjustment, one or more programming pulses are increased, the purpose of successful final programming is achieved, and the NOR type flash memory can be effectively programmed even if the programming working power supply voltage connected to the input end of the charge pump is greatly changed under the condition of limited driving capability of the charge pump.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the present invention are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is an example of a lowest charge pump drive capability curve for different programming supply voltages;
FIG. 2 is a schematic diagram of an embodiment of a NOR flash programming circuit of the present invention;
FIG. 3 shows an embodiment of a NOR-type flash memory programming circuit according to the present invention, which is capable of programming all 16 memory cells connected to the same word line at a time when the programming operation power supply voltage is high enough;
FIG. 4 is a schematic diagram of a NOR flash memory programming circuit according to an embodiment of the present invention, wherein programming of all memory cells connected to the same word line is completed by two programming pulses when the programming power supply voltage is low;
FIG. 5 is a graph of the driving capability of the charge pump at different programming power supply voltages for an embodiment of the NOR flash programming circuit of the present invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
As shown in fig. 2, the NOR flash memory programming circuit includes a power voltage detection circuit, a charge pump, an address decoding unit, and a programming control circuit;
the power supply voltage detection circuit is used for detecting the programming working power supply voltage at the input end of the charge pump;
the address decoding unit is used for selecting a memory cell needing programming operation in the NOR type memory array and providing a current channel from the output end of the charge pump to the memory cell needing programming;
the programming control circuit controls the maximum allowable connection quantity of the charge pump output end of the address decoding unit to the current channel of the bit line of the storage unit which corresponds to the same word line and needs to be programmed according to the real-time programming working power supply voltage of the charge pump input end detected by the power supply voltage detection circuit in a one-time programming pulse, namely, the maximum allowable connection quantity of the storage unit which corresponds to the same word line and is programmed is controlled, the higher the real-time programming working power supply voltage is, the larger the maximum allowable connection quantity of the charge pump output end of the address decoding unit to the current channel of the bit line of the storage unit which corresponds to the same word line and needs to be programmed is in the one-time programming pulse, namely, the more the maximum allowable quantity of the storage unit which corresponds to the same word line and is programmed in the one-time programming pulse.
Preferably, the current channel includes a voltage regulator for regulating the level of the programming voltage output by the charge pump to the bit line of the memory cell to be programmed.
Preferably, if the maximum allowable number in one programming pulse is smaller than the maximum number of memory cells to be programmed at the time corresponding to the same word line, in one programming pulse, the maximum allowable number of memory cell bit lines to be programmed at the time corresponding to the word line are programmed at first, and then in the next or more than one subsequent programming pulse, other memory cells to be programmed, which are not programmed at the maximum allowable number or are smaller than the maximum allowable number, corresponding to the word line are sequentially controlled to be programmed until all the memory cells to be programmed at the time corresponding to the word line are programmed.
As shown in fig. 3, the number of memory cells of a word (word) connected to the same word line is 16, where 5 bits need to be programmed, and when the programming operating power supply voltage at the input end of the charge pump is low, assuming that the maximum allowable number of connected cells in one programming pulse is 8, which is greater than the number of memory cells that need to be programmed, the programming control circuit may program all 5 memory cells that need to be programmed in the word in one programming pulse, and may complete programming of all 5 memory cells that need to be programmed in the word in one programming pulse.
As shown in fig. 4, when the number of memory cells of a word (word2) connected to the same word line is 16, where 10 bits need to be programmed, and the programming operating power supply voltage at the input end of the charge pump is low, assuming that the maximum allowable number of connected cells in one programming pulse is 8, which is less than the number of memory cells that need to be programmed, the program control circuit may first program the first 8 memory cells that need to be programmed in the word in one programming pulse, then complete programming of the remaining 2 memory cells that need to be programmed in the word in the next programming pulse, and complete programming of all the 10 memory cells that need to be programmed in the word connected to the same word line through two programming pulses.
In the NOR flash memory programming circuit of the first embodiment, the maximum allowable connected number of the current channels from the charge pump output terminal of the address decoding unit to the bit lines of the memory cells to be programmed corresponding to the same word line is controlled according to the real-time programming operating power supply voltage at the charge pump input terminal detected by the power supply voltage detection circuit, where the higher the real-time programming operating power supply voltage is, the maximum allowable connected number is (for example, when the programming operating power supply voltage at the charge pump input terminal is sufficiently high, the maximum allowable connected number of the memory cells corresponding to the same word line that can be programmed at the same time is 12, 16, or more); when the programming operation power supply voltage at the input end of the charge pump is low, the minimum driving capability of the programming charge pump is reduced (as shown in fig. 5, the minimum driving capability is shifted down from the curve), so that the maximum allowable number of the memory cells corresponding to the same word line which are programmed at the same time is reduced, only a small number of the memory cells which need to be programmed are programmed at the same time, and the remaining memory cells which need to be programmed and correspond to the word line are programmed when the next programming pulse comes.
The NOR flash memory programming circuit according to the first embodiment dynamically adjusts the maximum allowable number of memory cells corresponding to the same word line that can be programmed in one programming pulse according to different programming operating power supply voltages, so that the driving capability of the programming charge pump is fully utilized when the programming operating power supply voltage is high, the chip programming time is not sacrificed when the programming operating power supply voltage is high, the same programming practice effect can be achieved under a smaller charge pump area, the programming charge pump area is reduced, and the chip area is reduced; when the programming working power supply voltage is lower, the maximum allowable number of the storage units corresponding to the same word line which can be programmed in one programming pulse is reduced through dynamic adjustment, one or more programming pulses are increased, the purpose of successful final programming is achieved, and the NOR type flash memory can be effectively programmed even if the programming working power supply voltage connected to the input end of the charge pump is greatly changed under the condition of limited driving capability of the charge pump.
Example two
Based on the NOR type flash memory programming circuit implemented with the first step, the programming working power supply voltage is divided into M +2 intervals from low to high; the 0 th interval is smaller than the rated lowest programming working power supply voltage, and the M +1 th interval is larger than the rated highest programming working power supply voltage;
the memory cells which correspond to the same word line and need to be programmed sequentially have M groups, the M group has N or less than N memory cells, and N, M are positive integers;
in one programming pulse, when the real-time programming working power supply voltage at the input end of the charge pump is in the ith interval, the programming control circuit switches on a current channel from the output end of the charge pump of the address decoding unit to a bit line of a storage unit needing programming corresponding to the 1 st group to the ith group of the word line, wherein i is a positive integer less than or equal to M; and in the next programming pulse, controlling and switching on current channels from the output end of the charge pump of the address decoding unit to the bit lines of the rest storage units which are required to be programmed and correspond to other groups of the word lines according to the real-time programming working power supply voltage, wherein the number of the current channels switched on by the bit lines each time is i × N or a positive integer smaller than i × N.
Preferably, N is an even number.
Preferably, the programming control circuit outputs a low voltage alarm signal when the real-time programming working power supply voltage at the input end of the charge pump is in the 0 th interval.
Preferably, the programming control circuit outputs the high-voltage warning signal when the real-time programming working power supply voltage at the input end of the charge pump is in the (M + 1) th interval.
Preferably, the rated lowest programmed operating power supply voltage may be 1.6V, and the rated highest programmed operating power supply voltage may be 3.6V.
Preferably, if the number of memory cells connected to the same word line is 32, 17 bits of the memory cells need to be programmed, and if the real-time programming operating power voltage is low, the maximum number of memory cells capable of being programmed in one programming pulse is 8, three programming pulses are required to complete the programming.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (7)
1. A NOR flash memory programming circuit is characterized by comprising a power supply voltage detection circuit, a charge pump, an address decoding unit and a programming control circuit;
the power supply voltage detection circuit is used for detecting the programming working power supply voltage at the input end of the charge pump;
the address decoding unit is used for selecting a memory cell needing programming operation in the NOR type memory array and providing a current channel from the output end of the charge pump to the memory cell needing programming;
the programming control circuit controls the maximum allowable connection quantity of the charge pump output end of the address decoding unit to the current channel of the bit line of the storage unit which corresponds to the same word line and needs to be programmed according to the real-time programming working power supply voltage of the charge pump input end detected by the power supply voltage detection circuit in a one-time programming pulse, namely, the maximum allowable connection quantity of the storage unit which corresponds to the same word line and is programmed is controlled, the higher the real-time programming working power supply voltage is, the larger the maximum allowable connection quantity of the charge pump output end of the address decoding unit to the current channel of the bit line of the storage unit which corresponds to the same word line and needs to be programmed is in the one-time programming pulse, namely, the more the maximum allowable quantity of the storage unit which corresponds to the same word line and is programmed in the one-time programming pulse.
2. The NOR-type flash memory programming circuit of claim 1,
the current channel comprises a voltage regulator which is used for regulating the high and low of the programming voltage output by the charge pump to the bit line of the memory cell needing to be programmed.
3. The NOR-type flash memory programming circuit of claim 1,
if the maximum allowable number in one programming pulse is less than the maximum memory cell number corresponding to the same word line and needing programming at the time, in one programming pulse, the memory cell bit lines needing programming at the time of the word line with the maximum allowable number are programmed, and then in the next or more than one subsequent programming pulse, other memory cells which are not programmed and need programming and are corresponding to the word line with the maximum allowable number or less than the maximum allowable number are sequentially controlled to be programmed until all the memory cells needing programming at the time of the word line are programmed.
4. The NOR-type flash memory programming circuit of claim 1,
the programming working power supply voltage is divided into M +2 intervals from low to high; the 0 th interval is smaller than the rated lowest programming working power supply voltage, and the M +1 th interval is larger than the rated highest programming working power supply voltage;
the memory cells which correspond to the same word line and need to be programmed sequentially have M groups, the M group has N or less than N memory cells, and N, M are positive integers;
in one programming pulse, when the real-time programming working power supply voltage at the input end of the charge pump is in the ith interval, the programming control circuit switches on a current channel from the output end of the charge pump of the address decoding unit to a bit line of a storage unit needing programming corresponding to the 1 st group to the ith group of the word line, wherein i is a positive integer less than or equal to M; and in the next programming pulse, controlling and switching on current channels from the output end of the charge pump of the address decoding unit to the bit lines of the rest storage units which are required to be programmed and correspond to other groups of the word lines according to the real-time programming working power supply voltage, wherein the number of the current channels switched on by the bit lines each time is i × N or a positive integer smaller than i × N.
5. The NOR-type flash memory programming circuit of claim 4,
n is an even number.
6. The NOR-type flash memory programming circuit of claim 4,
and when the real-time programming working power supply voltage at the input end of the charge pump is in the 0 th interval, the programming control circuit outputs a low-voltage alarm signal.
7. The NOR-type flash memory programming circuit of claim 4,
and when the real-time programming working power supply voltage at the input end of the charge pump is positioned in the (M + 1) th interval, the programming control circuit outputs a high-voltage alarm signal.
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| CN202111459053.6A CN114203242A (en) | 2021-12-02 | 2021-12-02 | NOR type flash memory programming circuit |
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